KR20110111731A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
KR20110111731A
KR20110111731A KR1020100030957A KR20100030957A KR20110111731A KR 20110111731 A KR20110111731 A KR 20110111731A KR 1020100030957 A KR1020100030957 A KR 1020100030957A KR 20100030957 A KR20100030957 A KR 20100030957A KR 20110111731 A KR20110111731 A KR 20110111731A
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KR
South Korea
Prior art keywords
layer
sacrificial
pattern
forming
hard mask
Prior art date
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KR1020100030957A
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Korean (ko)
Inventor
김태형
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020100030957A priority Critical patent/KR20110111731A/en
Publication of KR20110111731A publication Critical patent/KR20110111731A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The present invention is to provide a method of manufacturing a semiconductor device that can prevent the CD from changing in forming a fine pattern by using a spacer patterning technology (SPT), the present invention for this purpose is a hard mask film on the etching target layer And sequentially forming an etch stop layer; Forming a first sacrificial pattern on the etch stop layer; Forming a spacer on both sidewalls of the first sacrificial pattern; forming a second sacrificial pattern on the etch stop layer to fill the spacers; Removing the spacers; And etching the etch stop layer and the hard mask layer using the first and second sacrificial patterns as etch barriers to form a hard mask pattern. According to the present invention, By forming the spacers so that the upper surface of the first sacrificial pattern is exposed before forming the sacrificial pattern, there is an effect of preventing the CD variation of the micropattern due to the step between them.

Description

Semiconductor device manufacturing method {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device using a spacer patterning technology (SPT).

In developing semiconductor devices, pattern shrinkage is the key to improving yield. Recently, Spacer Patterning Technology (SPT) has been introduced and applied as the photolithography process has reached a limit in reducing the size of patterns.

There are two types of spacer patterning techniques: positive type and negative type, and a lot of negative type spacer patterning techniques are used, which are relatively simpler to process than positive type.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, the first oxide layer 12, the first polysilicon layer 13 (Poly-Si), the amorphous carbon layer 14 (aC), and the silicon oxynitride layer 15 are disposed on the etching target layer 11. After the SiON is sequentially formed, the photoresist pattern 16 is formed on the silicon oxynitride film 15.

As shown in FIG. 1B, the silicon oxynitride layer 15 and the amorphous carbon layer 14 are sequentially etched using the photoresist pattern 16 as an etch barrier. Hereinafter, the reference numerals of the etched silicon oxynitride film 15 and the amorphous carbon film 14 are changed to '15A' and '14A', respectively.

Next, the photosensitive film pattern 16 is removed.

As shown in FIG. 1C, after etching the first polysilicon film 13 using the silicon oxynitride film 15A and the amorphous carbon film 14A as an etch barrier, the first oxide film 12 is partially recessed in succession. )do. Hereinafter, the reference numerals of the etched first polysilicon film 13 and the first oxide film 12 are changed to '13A' and '12A', respectively.

Next, the silicon oxynitride film 15A and the amorphous carbon film 14A are removed.

As shown in FIG. 1D, a second oxide film 17 is formed along the surfaces of the first polysilicon film 13A and the first oxide film 12A.

As shown in FIG. 1E, after the second polysilicon layer 18 is deposited on the entire surface of the second oxide layer 17, the entire surface etching process is performed. Hereinafter, the reference numeral of the second polysilicon film 18 embedded between the second oxide film 17 is changed to '18A' and described.

As illustrated in FIG. 1F, the second oxide layer 17 is etched to expose the first triangular layer 12A between the first and second polysilicon layers 13A and 18A. Hereinafter, the reference numeral of the second oxide film 17 remaining between the second polysilicon film 18A and the first oxide film 12A will be changed to '17A'.

As shown in FIG. 1G, the remaining first oxide film 12A is etched using the first and second polysilicon films 13A and 18A as an etch barrier. Hereinafter, the reference numeral of the etched first oxide film 12A is changed to '12B' and described.

Through the above-described process, the first pattern 19A, the second polysilicon film 18A, the second oxide film 17A, and the first polysilicon film 13A and the first oxide film 12B are stacked. The hard mask pattern 19 including the second pattern 19B having a structure in which the monooxide 12B is stacked may be formed.

Subsequently, although not shown in the drawing, the etching target layer 11 is etched using the hard mask pattern 19 as an etch barrier to form a fine pattern.

However, in the method of manufacturing a semiconductor device according to the related art, the first polysilicon film 13A is etched to prevent a step from occurring between the first polysilicon film 13A and the second polysilicon film 18A. The first oxide film 12A is partially recessed in the process. At this time, since the recess of the first oxide film 12A proceeds without the stop layer, there is a limit to forming the recess to have a uniform recess depth over the entire wafer. This uneven recess depth of the first oxide film 12A acts as a cause of deterioration of the characteristics of the semiconductor device.

In addition, in the prior art, since the first polysilicon film 13A formed during the entire etching of the second polysilicon film 18A is protected by the second oxide film 17, the first polysilicon is not lost. There is a problem that a step occurs between the film 13A and the second polysilicon film 18A. As such, when a step occurs between the first and second polysilicon films 13A and 18A, a problem of varying the CD (critical dimension) of the hard mask pattern 19 is caused.

In addition, in the related art, since the materials constituting the first pattern 19A and the second pattern 19B constituting the hard mask pattern 19 are different from each other, the hard mask pattern 19 may be due to physical property differences between the materials. ) CD is fluctuated.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent the CD from changing in forming a fine pattern using a spacer patterning technique. .

According to an aspect of the present invention, a hard mask layer and an etch stop layer are sequentially formed on an etching target layer; Forming a first sacrificial pattern on the etch stop layer; Forming a spacer on both sidewalls of the first sacrificial pattern; forming a second sacrificial pattern on the etch stop layer to fill the spacers; Removing the spacers; And etching the etch stop layer and the hard mask layer using the first and second sacrificial patterns as etch barriers to form a hard mask pattern.

When the step of forming the spacers on both side walls of the first sacrificial pattern is completed, it is preferable that the upper surface of the first sacrificial pattern is exposed.

The spacer is preferably removed using a wet etching method.

The forming of the second sacrificial pattern may include depositing a sacrificial layer on the entire surface of the substrate; And planarizing the sacrificial layer until the spacer is exposed. In this case, the first sacrificial pattern and the second sacrificial pattern may be formed of the same material, and the planarization may be performed using a chemical mechanical polishing method or an etch back.

The etch stop layer may be formed of a material having an etch selectivity with the hard mask layer, the first and second sacrificial patterns. For example, the etch stop layer may include a nitride layer, the first and second sacrificial patterns may include a polysilicon layer, and the hard mask layer may include an oxide layer.

The spacer may be formed of a material having an etch selectivity with the etch stop layer, the first and second sacrificial patterns. For example, the spacer may include an oxide layer, and the first and second sacrificial patterns may include a polysilicon layer.

According to the present invention based on the above-described problem solving means, by inserting an etch stop film between the hard mask film and the first sacrificial pattern, and forming a spacer so that the upper surface of the first sacrificial pattern is exposed, the first sacrificial pattern and the first There is an effect that can be prevented at the source of the step between the two sacrificial patterns. Therefore, there is an effect that the CD of the hard mask pattern can be prevented from changing.

In addition, the present invention does not need to partially recess the hard mask film during the first sacrificial pattern forming process in order to prevent the generation of the step between the first sacrificial pattern and the second sacrificial pattern. There is an effect that can prevent the deterioration of characteristics.

In addition, the present invention has an effect that the process can be simplified by providing an etch stop layer, so that the spacer can be removed using a wet etching method. In addition, it is possible to prevent the pre-formed structure is damaged, thereby preventing the CD of the hard mask pattern from changing.

In addition, the present invention has the effect that it is possible to prevent the CD fluctuation of the hard mask pattern due to the difference in physical properties between each material because the configuration of the material film remaining on the hard mask pattern are all the same.

As a result, the present invention has the effect of preventing the CD from changing at the same time to implement the line width of the fine pattern to be implemented.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention, which will be described later, can prevent CD (Critical Dimension) fluctuations in forming a fine pattern using a spacer patterning technology (SPT), in particular, a negative pattern spacer patterning technology. A method for manufacturing a semiconductor device is provided.

2A through 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the hard mask layer 32, the etch stop layer 33, the first sacrificial layer 34, the carbon-containing layer 35, and the anti-reflection layer 36 are formed on the etching target layer 31. Form sequentially. In this case, the etch stop layer 33 may be formed of a material having an etch selectivity with respect to the hard mask layer 32 and the first sacrificial layer 34. For example, the hard mask layer 32 may be formed of an oxide layer, the first sacrificial layer 34 may be formed of a polysilicon layer, and the etch stop layer 33 may be formed of a nitride layer. (Nitride) can be formed. The carbon-containing film 35 may be formed of an amorphous carbon layer (a-C), and the anti-reflection film 36 may be formed of a silicon oxynitride layer (SiON).

The etch stop layer 33 may be formed to have a thickness in the range of 20 kV to 500 kV.

Next, the photosensitive film pattern 37 is formed on the antireflection film 36.

As shown in FIG. 2B, the anti-reflection film 36 and the carbon-containing film 35 are etched using the photoresist pattern 37 as an etch barrier. Hereinafter, the reference numerals of the etched carbon-containing film 35 and the anti-reflection film 36 are changed to '35A' and '36A', respectively.

Here, the photoresist pattern 37 may be consumed and removed during the etching of the anti-reflection film 36A and the carbon-containing film 35A, or may be removed through a separate removal process after the etching process is completed.

As shown in FIG. 2C, the first sacrificial layer 34 is etched using the anti-reflection film 36A and the carbon-containing film 35A as an etch barrier to form the first sacrificial pattern 34A. In this case, the etching for forming the first sacrificial pattern 34A proceeds until the etch stop layer 33 is exposed, and since only the first sacrificial layer 34 is etched, the first sacrificial pattern 34A having the vertical sidewall 34A. ) Can be formed.

Here, the anti-reflection film 36A and the carbon-containing film 35A may be consumed and removed in the process of forming the first sacrificial pattern 34A, or may be removed through a separate de-icing process after the etching process is completed. .

As shown in FIG. 2D, spacers 38 are formed on both side walls of the first sacrificial pattern 34A. In this case, the spacer 38 may be formed of a material having an etch selectivity with respect to the first sacrificial pattern 34A and the etch stop layer 33. For example, the spacer 38 may be formed of an oxide film.

Here, the line width of the spacer 38 may be formed to be the same as the line width of the first sacrificial pattern 34A, and the top surface of the first sacrificial pattern 34A is exposed after the process of forming the spacer 38 is completed. .

The spacer 38 made of an oxide film is any one selected from the group consisting of C 4 F 8 , CHF 3 , CH 2 F 2 and C 4 F 6 after depositing an oxide film along the structure surface including the first sacrificial pattern 34A. It can be formed through a series of processes performed by full etching using one gas or two or more gases. In this case, the etching gas may be performed by adding oxygen gas (O 2 ) to the above-described gas combination. When using C 4 F 8 as an etching gas, the etching process may be performed for a time ranging from 10 seconds to 100 seconds using a flow rate ranging from 4 sccm to 500 sccm.

As shown in FIG. 2E, a second sacrificial layer 39 is formed on the entire surface of the substrate 31. In this case, the second sacrificial film 39 may be formed of the same material as the first sacrificial film 34. That is, the second sacrificial film 39 may be formed of a polysilicon film.

Next, the second sacrificial layer 39 is planarized until the spacers 38 are exposed to form the second sacrificial pattern 39A. At this time, in the process of forming the second sacrificial pattern 39A, the first sacrificial pattern 34A is partially etched. Hereinafter, the reference numeral of the etched first sacrificial pattern 34A is changed to '34B'.

The planarization process may be performed using chemical mechanical polishing (CMP) or etchback, and the upper surface of the first sacrificial pattern 34B and the upper surface of the second sacrificial pattern 39A may be on the same plane. It is desirable to proceed to position. This is because when a step occurs between the first sacrificial pattern 34B and the second sacrificial pattern 39A, the CD of the fine pattern to be formed through the subsequent process is changed by the step.

Typically, the hard mask film 32 is partially recessed in the process of forming the first sacrificial pattern 34B to prevent a step between the first sacrificial pattern 34B and the second sacrificial pattern 39A. In the embodiment, the hard mask layer 32 is not recessed in the process of forming the first sacrificial pattern 34B by the etch stop layer 33. However, in the exemplary embodiment of the present invention, when the spacer 38 is formed, the upper surface of the first sacrificial pattern 34B is exposed, and the first sacrificial pattern 34B and the second sacrificial pattern 39A are exposed. Since the same material may be formed in the above-described planarization process so that the upper surface is located on the same plane.

As shown in FIG. 2F, the spacer 38 is removed. In this case, the spacer 38 may be removed using a dry etch or a wet etch. Preferably, the spacer 38 is removed by a wet etch to prevent damage to the formed structure. desirable.

Here, in the present invention, even if the spacer 38 is removed by wet etching, the hard mask layer 32 is not damaged (or lost) due to the etch stop layer 33, and the first and second sacrificial patterns 34B and 39A are removed. Also, since the spacer 38 is formed of a material having an etching selectivity, the spacer 38 is not damaged during the wet etching process. As such, when the spacer 38 is removed by wet etching instead of dry etching, the process is simpler than dry etching, thereby improving productivity, and more effectively preventing damage to the deformed structure. In addition, by-products (or residues) may be more effectively prevented from remaining on the surfaces of the first and second sacrificial patterns 34B and 39A and the etching stop layer 33 than the dry etching.

As shown in FIG. 2G, the etch stop layer 33 and the hard mask layer 32 are sequentially etched using the first and second sacrificial patterns 34B and 39A as etch barriers to form the hard mask pattern 32A. do. Hereinafter, the reference numeral of the etched stop film 33 is changed to '33A' and described.

Next, although not shown in the drawing, the etching target layer 31 is etched using the hard mask pattern 32A as an etch barrier to form a fine pattern. Here, the etch stop layer 33A and the first and second sacrificial patterns 34B and 39A remaining on the hard mask pattern 32A also play the same role as the hard mask pattern 32A.

As described above, according to the present invention, the etch stop layer 33 is inserted between the hard mask layer 32 and the first sacrificial layer 34 and the spacer 38 is exposed so that the top surface of the first sacrificial pattern 34B is exposed. ), It is possible to fundamentally prevent the generation of a step between the first sacrificial pattern 34B and the second sacrificial pattern 39A. Therefore, the CD of the hard mask pattern 32A can be prevented from changing.

In addition, the present invention needs to partially recess the hard mask layer 32 during the process of forming the first sacrificial pattern 34B in order to prevent the generation of the step between the first sacrificial pattern 34B and the second sacrificial pattern 39A. In this case, the deterioration of characteristics of the semiconductor device due to the uneven recess depth can be prevented.

In addition, according to the present invention, since the spacer 38 is removed by using the wet etching method, the etching stop layer 33 may simplify the process. In addition, it is possible to prevent the pre-formed structure from being damaged, thereby preventing the CD of the hard mask pattern 32A from changing.

In addition, the present invention can prevent the CD variation of the hard mask pattern 32A due to the difference in physical properties between the respective materials because the configuration of the material films remaining on the hard mask pattern 32A are the same.

As a result, the present invention has the effect of preventing the CD from changing at the same time to implement the line width of the fine pattern to be implemented.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

31 substrate 32 hard mask film
32A: hard mask pattern 33, 33A: etch stop film
34: first sacrificial film 34A, 34B: first sacrificial pattern
35, 35A: carbon-containing film 36, 36A: antireflection film
37 photosensitive film pattern 38 spacer
39: second sacrificial film 39A: second sacrificial pattern

Claims (9)

Sequentially forming a hard mask layer and an etch stop layer on the etching target layer;
Forming a first sacrificial pattern on the etch stop layer;
Forming spacers on both sidewalls of the first sacrificial pattern;
Forming a second sacrificial pattern filling the spacers on the etch stop layer;
Removing the spacers; And
Forming a hard mask pattern by etching the etch stop layer and the hard mask layer using the first and second sacrificial patterns as etch barriers;
Semiconductor device manufacturing method comprising a.
The method of claim 1,
And forming a spacer on both sidewalls of the first sacrificial pattern, wherein the top surface of the first sacrificial pattern is exposed.
The method of claim 1,
The spacer is removed using a wet etching method. The method of claim 1,
Forming the second sacrificial pattern,
Depositing a sacrificial layer on the entire surface of the substrate; And
Planarizing the sacrificial layer until the spacer is exposed
Semiconductor device manufacturing method comprising a.
The method of claim 4, wherein
The first sacrificial pattern and the second sacrificial pattern are formed of the same material as each other.
The method of claim 1,
The etch stop layer is formed of a material having an etching selectivity with the hard mask layer, the first and second sacrificial patterns.
The method of claim 6,
The etch stop layer includes a nitride layer, the first and second sacrificial patterns include a polysilicon layer, and the hard mask layer includes an oxide layer.
The method of claim 1,
And the spacer is formed of a material having an etch selectivity with respect to the etch stop layer, the first and second sacrificial patterns.
The method of claim 8,
The spacer includes an oxide layer, and the first and second sacrificial patterns include a polysilicon layer.
KR1020100030957A 2010-04-05 2010-04-05 Method for forming semiconductor device KR20110111731A (en)

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KR1020100030957A KR20110111731A (en) 2010-04-05 2010-04-05 Method for forming semiconductor device

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