KR20110101541A - Flexible type semiconductor package and fabricating this - Google Patents

Flexible type semiconductor package and fabricating this Download PDF

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Publication number
KR20110101541A
KR20110101541A KR1020100020603A KR20100020603A KR20110101541A KR 20110101541 A KR20110101541 A KR 20110101541A KR 1020100020603 A KR1020100020603 A KR 1020100020603A KR 20100020603 A KR20100020603 A KR 20100020603A KR 20110101541 A KR20110101541 A KR 20110101541A
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KR
South Korea
Prior art keywords
wafer
film
semiconductor package
chip
input
Prior art date
Application number
KR1020100020603A
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Korean (ko)
Inventor
김영선
Original Assignee
김영선
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Priority to KR1020100020603A priority Critical patent/KR20110101541A/en
Publication of KR20110101541A publication Critical patent/KR20110101541A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

In general, semiconductor packages are manufactured using thermosetting epoxy mold compound (EMC), which keeps the finished products from bending. In contrast, the packaged product of the present invention allows the chip in the wafer state to be bent by grinding / polishing. In order to protect the chip, a heat resistant polyimide-based film is used to seal the chip.
The film used for sealing forms the necessary electrical circuits and input / output terminals (I / O), and bumps are formed on the input / output terminals necessary for the chip, and the connection to the input / output terminals of the electrical circuit of the sealing film Be sure to In addition, during sealing, epoxy or resin, flux, or the like may be completely sealed or adhered between the wafer and the film. If necessary, bumps, solder balls, and the like that are electrically conductive may be formed in the input / output terminals I / O formed on one surface of the film.
The wafer having the above-mentioned process is sawed to be separated into individual chips, thereby making a light and small flexible semiconductor package product.

Figure P1020100020603

Description

Flexible semiconductor package and its manufacturing method {Flexible Type Semiconductor Package and Fabricating this.}

The present invention relates to a structure of a semiconductor package and a manufacturing method thereof, and more particularly to a thin semiconductor chip and a polyimide film and an epoxy that can seal the semiconductor chip so as to bend. The present invention relates to a method for manufacturing a semiconductor package and its structure.

The prior art semiconductor package (semiconductor package) is manufactured in a rigid form, the semiconductor package manufacturing and structure having a solder ball of the prior art is generally as shown in Figure 4;

The semiconductor chip 1 is attached to the substrate 5 using an adhesive epoxy 6.

-Connect the I / O terminal (2) of the attached semiconductor chip and the internal I / O terminal (4) on the substrate by a gold wire or an aluminum wire (3).

Molding is carried out to protect the semiconductor chip and the fine metal wire by using an epoxy molding compound (EMC) (7).

Solder balls 9 are formed on the external I / O terminals 8 of the substrate.

In addition, in the structure of a semiconductor package product in the form of a bare chip using a flip-chip method, as shown in FIG. 5;

-Semiconductor chip (1)-bond pad (2)-bump (10)

-I / O terminal on substrate (4)-Under-fill epoxy (15)

Substrate (PCB) (5)

Consists of

Prior art semiconductor package products have been limited in the surface mounting and reliability of the packaged products due to the characteristics of the molding (molding) material and the thickness of the IC chip (chip). In particular, there is a difficulty when mounting on a flexible flexible PCB (flexible PCB).

In addition, defects due to warpage caused by thermal expansion in a mother board, a package product, or a package on package (PoP) product, which occur after surface mounting, may occur. do.

Therefore, there is a purpose to solve these problems.

The present invention eliminates the rigidity of the existing rigid, warp-free semiconductor package, and further makes the package even thinner to further increase the surface mountability of the semiconductor package product. That is, it is possible to facilitate a higher reliability and surface mount process than a bare chip using the flip-chip bonding of the prior art. In addition, surface mounting may be performed more naturally in a flexible display and a flexible PCB that will be commercialized in the future.

In addition, defects due to warpage occurring between the mother board and the package, and the package and the package can be naturally solved.

The present invention is compared to the conventional plastic package of a method of molding together a gold (aluminum wire), a chip (chip) and a substrate (substrate);

-Significantly reduce package volume and thickness

-Can improve the reliability of heat,

-It can flexibly cope with film type PCB which requires surface mounting on curved surface.

In addition, rather than bare chip (bare chip) to form and use only a simple bump (bump);

-It can improve reliability by protecting semiconductor chip from external environment,

-By not underfilling, manufacturing costs can be significantly reduced by simplifying the process and reducing defective rates.

Therefore, the semiconductor package product structure and manufacturing process of the present invention can be expected to be used in the packaged product of the semiconductor chip that can be surface-mounted on the curved surface while requiring a lighter reliability while achieving a light and small size. Can be.

1 is a cross-sectional view of a wafer state in accordance with an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.
3 is a cross-sectional view of another type of semiconductor package according to an embodiment of the present invention.
4 is a cross-sectional view of a semiconductor package according to an example of the prior art
5 is a package cross-sectional view of the use of a bare chip form according to an example of the prior art.
6A to 6F are cross-sectional views of a semiconductor package manufacturing process according to an embodiment of the present invention.

The wafer 11 with the integrated circuit (IC) is ground to allow bending using a back grinding & polishing machine, and one side of the very thinly ground wafer has good thermal properties and adhesion. Attached to a polyimide film 13 with material, the surface of the wafer 11 with integrated circuits (ICs) having electrical circuits and I / O terminals (4) (8) The thermally formed polyimide film 14 is attached or sealed to the polyimide film 14 by using epoxy or resin 12, wherein the chip I Solder ball pads are formed on the polyimide film of the sealed wafer so that the / O terminal and the I / O terminal of the polyimide film are connected to each other, and if necessary, heat-sealing the sealed or sealed wafer is performed. Solder balls 9 are formed on the I / O terminals 8, which may be ball pads 8. The. The sealed wafer is attached to a wafer sawing tape, and the wafer is cut in units of individual chips 1.

That is, as shown in Fig. 1, Fig. 2, and Fig. 3;

-Semiconductor chip (1)-wafer (11)

Bond pads (Chip I / O terminals) (2) Bumps (10)

-Epoxy (12)-polyimide film (13) (14)

-Solder ball (9)-solder ball pad (8)

Polyimide film I / O terminals (4) (8)

Etc.

In addition, as an example of the manufacturing process of the "semiconductor package of the method which can be bent" which is this invention, as FIG. 6A-FIG. 6F;

A tape for back grinding (bump) in a state in which a bump 10 is formed on a bond pad 2 on a wafer 11 on which a semiconductor chip is formed ( 15) or by attaching a glass or metal plate to grind the back side of the wafer to the required thickness. ------ (Figure 6a)

A polyimide film 13 is attached to the thinned wafer backside. ------ (Figure 6b)

-Epoxy (12) is applied on the thinned wafer top. ------ (Figure 6c)

Sealing the chips on the wafer by bringing the film 14 into close contact with the wafer 11 using a polyimide film 14 having electrical circuits and I / O terminals 4 and 8 formed thereon. After heat treatment, it is baked (cure). ------ (Figure 6d)

Solder balls 9 are formed on the I / O terminals 8 formed on the polyimide film. ------ (Fig 6e)

The semiconductor chips sealed in wafer shape are sawed to the required chip 1 size to complete the individual semiconductor package. ------ (Figure 6f)

Claims (6)

Wafers polished to the level where the integrated circuit (IC) is formed and can be bent, polyimide film having adhesives, electrical circuits, and I / O terminals, etc., and integrated circuits using polyimide films using epoxy or resin A semiconductor package product formed by sealing a wafer and heat-treating the wafer while the I / O terminals of the polyimide film are interconnected, and cutting the sealed wafer based on individual chips (ICs). The semiconductor package product according to claim 1, wherein an electrically conductive material such as bump is used for the I / O terminal formed on the wafer. The semiconductor package product of claim 1, wherein an electrically conductive material such as solder balls is used for the I / O terminal of the polyimide film. The semiconductor package product according to claim 1, wherein a material which can be bent, such as a film or a tape capable of forming an electric circuit and an I / O terminal, is used in addition to the polyimide film. The semiconductor package product of claim 1, wherein anisotropic electro-conductive material is used instead of epoxy, resin, or flux, or is sealed or attached only to a film or tape capable of warping. The semiconductor package product of claim 1, wherein the wafer is sealed using a film on one or both sides of the wafer.
KR1020100020603A 2010-03-09 2010-03-09 Flexible type semiconductor package and fabricating this KR20110101541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100020603A KR20110101541A (en) 2010-03-09 2010-03-09 Flexible type semiconductor package and fabricating this

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100020603A KR20110101541A (en) 2010-03-09 2010-03-09 Flexible type semiconductor package and fabricating this

Publications (1)

Publication Number Publication Date
KR20110101541A true KR20110101541A (en) 2011-09-16

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