KR20110079145A - Method for metal rework of semiconductor device generated metal corrosion - Google Patents
Method for metal rework of semiconductor device generated metal corrosion Download PDFInfo
- Publication number
- KR20110079145A KR20110079145A KR1020090136119A KR20090136119A KR20110079145A KR 20110079145 A KR20110079145 A KR 20110079145A KR 1020090136119 A KR1020090136119 A KR 1020090136119A KR 20090136119 A KR20090136119 A KR 20090136119A KR 20110079145 A KR20110079145 A KR 20110079145A
- Authority
- KR
- South Korea
- Prior art keywords
- metal
- corrosion
- rework
- cmp
- scrubber
- Prior art date
Links
- 239000002184 metal Substances 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 42
- 230000007797 corrosion Effects 0.000 title claims abstract description 31
- 238000005260 corrosion Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title description 3
- 239000013077 target material Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 9
- 229920000642 polymer Polymers 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 238000005201 scrubbing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 239000013317 conjugated microporous polymer Substances 0.000 claims 5
- IERHLVCPSMICTF-XVFCMESISA-N CMP group Chemical group P(=O)(O)(O)OC[C@@H]1[C@H]([C@H]([C@@H](O1)N1C(=O)N=C(N)C=C1)O)O IERHLVCPSMICTF-XVFCMESISA-N 0.000 claims 2
- 102100037064 Cytoplasmic dynein 2 light intermediate chain 1 Human genes 0.000 claims 1
- 101000954716 Homo sapiens Cytoplasmic dynein 2 light intermediate chain 1 Proteins 0.000 claims 1
- 239000000126 substance Substances 0.000 abstract description 8
- 238000001465 metallisation Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 2
- 238000006731 degradation reaction Methods 0.000 abstract 2
- 230000008021 deposition Effects 0.000 description 15
- 238000001020 plasma etching Methods 0.000 description 13
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004448 titration Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
The present invention relates to a metal rework method of a metal corrosion generating device, and more particularly, to remove the metal corrosion generated during the reactive ion etching to implement a sequence that can proceed from the metal deposition again, yield reduction and lot reject It relates to a metal rework method of a metal corrosion generating element that can be reduced.
In general, in the process for forming metal (metal) wiring, when the reactive ion etching (RIE) occurs in temperature or when the equipment trouble occurs during the process, metal corrosion occurs. Done.
If this phenomenon occurs, bridges between metal lines are generated, which causes about 100 ~ 200ea of rejection per year, and requires a rework process that requires rework of the corresponding layer.
That is, conventionally, as shown in FIG. 1, W-CMP (W-Chemical Mechanical Polish) is performed to form metal wires, followed by metal DEP (Deposition) to deposit the target material on the workpiece. After scraping through a titration scrubber, metal PEP (Photo Engraving Process) is processed.
Subsequently, metal RIE is performed, wherein the semiconductor device in which the metal corrosion occurs is rejected.
Such metal corrosion leads to a phenomenon in which the operation of the device becomes impossible due to the bridge state due to the corrosion between metal lines.
This can be seen that metal corrosion occurs and grows due to the following reaction without the removal of the CL group from the sidewall of the metal line due to the leakage of the HCL vapor pressure due to the leakage of the vacuum chamber or temperature.
However, this metal corrosion eventually leads to the disadvantage of lowering the yield and generating a lot reject, which leads to a sharp decrease in productivity.
The present invention was created in view of the above-described problems in the prior art, and solves this problem. The entire metal line in which the metal corrosion is generated is not rejected during the metal RIE during the metal wiring formation process. The main challenge is to provide a metal rework method for metal corrosion-producing devices that can improve productivity by preventing a poor yield or lot reject process by establishing a sequence that can be re-progressed from the metal DEP process after removal. have.
The present invention is a means for achieving the above-described problems, the step of performing W-CMP (W-Chemical Mechanical Polish) to form metal wiring, the deposition of the target material on the workpiece by performing metal DEP (Deposition) In the step of performing the metal RIE when the metal wiring forming process is performed, including the step of, appropriately scrubbing through a scrubber, metal PEP (Photo Engraving Process) processing step, and performing metal RIE If metal corrosion occurs, the metal layer of the metal corrosion generating device is configured to immediately remove the corrosion-prone layer from the corresponding lot, and then perform the metal DEP to return to the step of depositing a target material on the workpiece. Provide a rework method.
At this time, the process of removing the layer of the lot in which the metal corrosion is generated, the step of etching back the layer (ETCH BACK), the polymer and metal remaining after the etch back through the LIC3 (Low temp Inorganic Chemical 3 mixture) and scrubber Removing impurities, purifying through D-SONIC, removing convex phenomena around Ti / TiN and vias in fence form through Chemical Mechanical Polish (W-CMP) and Oxide CMP. It also has its features.
In addition, the step of removing the polymer and metal impurities is characterized in that the LIC3 is carried out in two steps before and after the scrubber treatment step.
In addition, in the pure water treatment step, the D-SONIC is characterized in that it is made by the method of spraying pure water by applying 0.8A (amps).
In addition, the step of eliminating the convex phenomena around the Ti / TiN and the via in the form of the fence is characterized in that the W-CMP is carried out in two steps before and after the oxide CMP.
According to the present invention, it is possible to resume the process immediately after removing the metal from the layer through the rework sequence without rejecting the defective lot caused by the corrosion generated in the metal RIE, thereby reducing the defect rate, reducing the process loss, preventing the yield loss, and improving the productivity. The effect of improving can be obtained.
Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment according to the present invention.
2 is a flowchart showing a rework method according to the present invention.
As shown in FIG. 2, the rework method according to the present invention removes the corrosion generated during the metal reactive ion etching (RIE) and proceeds from the metal DEP (Deposition) again. It is possible to increase the efficiency of the process by setting up to prevent yield loss and to eliminate lot rejects.
That is, as shown in Figure 2, the present invention is to perform a step W-CMP (W-Chemical Mechanical Polish) (W100) to form a metal wiring (S100), performing a metal DEP (Deposition) to target the target material Deposition to step (S110), appropriately scrubbing through a scrubber (Scrubber) (S120), metal PEP (Photo Engraving Process) processing step (S130), and then performing a metal RIE (S140) When the metal corrosion occurs in the metal RIE performing step (S140), unlike the conventional case in which the corresponding lot is rejected, the layer having the corrosion generated from the lot is immediately removed and then the metal DEP performing step (S110). It can be configured to regress and reprocess.
More specifically, referring to FIG. 2, when metal corrosion occurs during metal RIE, the lot in which corrosion is generated is sorted and then reworked.
Rework operations include ETCH BACK (S141), Primary LIC3 (S142), Z-SCRUBBER (S143), Secondary LIC3 (S144), D-SONIC (S145), Primary W-CMP (S146) , In order of Oxide CMP (S147), secondary W-CMP (S148), through which the corrosion-prone layer of the lot is completely removed, and then back to step S110, that is, metal DEP process By continuous treatment, the defects caused by corrosion can be healed.
At this time, step S141 is to perform an etch back (ETCH BACK), thereby removing the PR.
In addition, the step S142 is performed, which is to perform a first low temp inorganic chemical 3 mixture (LIC3), thereby removing the metal.
This is to remove the oxide (Oxide) step due to Ti / TiN remaining after the etch back due to the polymer, and the step S143 performing scrubbing through the scrubber and the second step LIC3 performing LIC3 once again, that is, the step S144 By doing so, the polymer and metal impurities can be more efficiently removed.
Subsequently, step S145 is performed.
Step S145 refers to a D-SONIC process, in which 0.8 A (amps) is added to pure water (DIW) and sprayed onto a target object (wafer) in a high frequency scrubber treatment of the scrubber nozzle.
This removes the large P / T.
Thereafter, step S146 for removing Ti / TiN present in a fence form through primary W-CMP (Chemical Mechanical Polish), step S147 for performing an oxide CMP process to remove the remaining step after this step, Finally, the S148 step is performed through a second W-CMP, which is a finishing operation to remove the block phenomenon caused by the loss of oxide around the via via the oxide CMP.
Through these steps, only the relevant layer of the defective lot caused by corrosion is completely removed, and then returned to methyl DEP, so that it can be regenerated without being rejected as before, contributing to yield improvement, productivity improvement, and process efficiency improvement. do.
1 is a schematic flowchart showing a metal wiring forming process according to a conventional method,
2 is a flowchart showing a rework method according to the present invention;
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090136119A KR20110079145A (en) | 2009-12-31 | 2009-12-31 | Method for metal rework of semiconductor device generated metal corrosion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090136119A KR20110079145A (en) | 2009-12-31 | 2009-12-31 | Method for metal rework of semiconductor device generated metal corrosion |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20110079145A true KR20110079145A (en) | 2011-07-07 |
Family
ID=44918555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020090136119A KR20110079145A (en) | 2009-12-31 | 2009-12-31 | Method for metal rework of semiconductor device generated metal corrosion |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20110079145A (en) |
-
2009
- 2009-12-31 KR KR1020090136119A patent/KR20110079145A/en not_active Application Discontinuation
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