KR20110078864A - Method manufactruing of flash memory device - Google Patents

Method manufactruing of flash memory device Download PDF

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KR20110078864A
KR20110078864A KR1020090135776A KR20090135776A KR20110078864A KR 20110078864 A KR20110078864 A KR 20110078864A KR 1020090135776 A KR1020090135776 A KR 1020090135776A KR 20090135776 A KR20090135776 A KR 20090135776A KR 20110078864 A KR20110078864 A KR 20110078864A
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film
forming
lower polysilicon
memory device
flash memory
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KR1020090135776A
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Korean (ko)
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김현태
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/954—Making oxide-nitride-oxide device

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE: A method manufacturing of a flash memory device is provided to prevent the residue of a polysilicon film from remaining on the both side wall of a lower polysilicon film in etching by forming an upper silicon film on the gate insulating layer to be relatively smaller than the lower polysilicon film. CONSTITUTION: In a method manufacturing of a flash memory device, an element isolation film(14) is formed in a semiconductor substrate(10) in which a first conductive well(11) and a second conductive well(12). A lower polysilicon layer(16) is formed on the semiconductor substrate. A sidewall(20) is formed in the both sidewall of the lower polysilicon layer. A gate insulating layer(18) is formed on the lower polysilicon layer. The upper polysilicon film(22) is formed on the gate insulating layer.

Description

플래시 메모리 소자의 제조방법{Method Manufactruing of Flash Memory Device} Manufacturing method of flash memory device {Method Manufactruing of Flash Memory Device}

본 발명은 플래시 메모리 소자의 제조방법에 관한 것으로, 특히 하부 폴리 실리콘에서의 사이드월 발생을 억제할 수 있는 플래시 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of suppressing sidewall generation in lower polysilicon.

반도체 메모리 장치는 데이타의 입출력이 빠르며 시간이 지남에 따라 데이타가 휘발되는 휘발성 메모리 장치 및 상대적으로 데이타의 입출력이 느리며 한번 데이터가 입력되면 그 상태가 유지되는 비휘발성 반도체 메모리(Non-Volatil e semiconductor Memory:NVM) 장치로 크게 구분된다. A semiconductor memory device is a volatile memory device in which data input and output is fast and data evolves over time, and a nonvolatile semiconductor memory in which a data input and output is relatively slow and is maintained once data is input. It is largely divided into: NVM) devices.

상기 비휘발성 반도체 메모리 장치로서 널리 사용되는 플래시 메모리 장치는 행들과 열들의 매트릭스로 배열된 복수개의 메모리 셀들을 포함한다. 상기 플래시 메모리 장치는 어레이 내의 하나 또는 그 보다 많은 메모리 셀들의 내용을 전기적으로 프로그램(program) 하거나 읽는 능력을 갖으며, 또한 동시에 메모리 셀들의 전 어레이를 동시에 소거(erase)하는 능력을 갖는다.A flash memory device widely used as the nonvolatile semiconductor memory device includes a plurality of memory cells arranged in a matrix of rows and columns. The flash memory device has the ability to electrically program or read the contents of one or more memory cells in an array, and at the same time erase the entire array of memory cells.

따라서, 상기와 같은 문제점을 해결하기 위하여, 본 발명은 하부 폴리 실리콘에서의 사이드월 발생을 억제할 수 있는 플래시 메모리 소자의 제조방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device that can suppress the occurrence of sidewalls in the lower polysilicon.

본 발명에 따른 플래시 메모리 소자의 제조방법은 액티브 영역과 필드 영역을 정의하기 위해 액티브 영역에 제 1 도전형 웰 및 제 2 도전형 웰이 각각 형성된 반도체 기판에 소자분리막을 형성하는 단계와, 상기 반도체 기판 상에 하부 폴리실리콘막을 형성하는 단계와, 상기 하부 폴리실리콘막의 양측벽에 사이드월을 형성하는 단계와, 상기 하부 폴리실리콘막 상에 게이트간 절연막을 형성하는 단계와, 상기 게이트간 절연막 상에 상부 폴리실리콘막을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a flash memory device according to the present invention includes forming a device isolation film on a semiconductor substrate each having a first conductivity type well and a second conductivity type well in an active region to define an active region and a field region; Forming a lower polysilicon film on a substrate, forming sidewalls on both sidewalls of the lower polysilicon film, forming an inter-gate insulating film on the lower polysilicon film, and forming an inter-gate insulating film on the lower polysilicon film. Forming an upper polysilicon film.

이상에서 설명한 바와 같이, 본 발명에 따른 플래시 메모리 소자의 제조방법은 하부 폴리실리콘의 양측벽에 형성된 사이드월로 인하여 상부 폴리실리콘을 하부 폴리실리콘보다 작게 식각하는 과정에서 하부 폴리실리콘의 양측벽에 상부 폴리실리콘의 잔여물이 남게되는 현상을 방지할 수 있다. 이로 인해, 의도하지 않은 상부 폴리실리콘의 잔여물로 인해 후속 이온 주입 공정에서 채널 길이가 일정하지 않게 되는 문제점을 해결할 수 있다. As described above, in the method of manufacturing the flash memory device according to the present invention, the upper side of the lower polysilicon is etched smaller than the lower polysilicon due to sidewalls formed on both sidewalls of the lower polysilicon. It is possible to prevent the residue of polysilicon remaining. This solves the problem that the channel length becomes inconsistent in subsequent ion implantation processes due to unintended residues of the upper polysilicon.

이하 상기의 목적을 구체적으로 실현할 수 있는 본 발명의 바람직한 실시 예를 첨부한 도면을 참조하여 설명한다. 이때 도면에 도시되고 또 이것에 의해서 설명되는 본 발명의 구성과 작용은 적어도 하나의 실시 예로서 설명되는 것이며, 이것에 의해서 상기한 본 발명의 기술적 사상과 그 핵심 구성 및 작용이 제한되지는않는다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

그리고 본 발명에서 사용되는 용어는 가능한 한 현재 널리 사용되는 일반적인 용어를 선택하였으나, 특정한 경우는 출원인이 임의로 선정한 용어도 있으며, 이 경우 해당되는 발명의 설명 부분에서 상세히 그 의미를 기재하였으므로, 단순한 용어의 명칭이 아닌 그 용어가 가지는 의미로서 본 발명을 파악하여야 함을 밝혀두고자 한다.In addition, the terminology used in the present invention is a general term that is currently widely used as much as possible, but in certain cases, the term is arbitrarily selected by the applicant. In this case, since the meaning is described in detail in the description of the present invention, It is to be understood that the present invention is to be understood as the meaning of the term rather than the name.

도 1a 내지 도 1d는 본 발명에 따른 플래시 메모리 소자의 제조 공정을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

여기서, 도 1a 내지 1d에서는 전체 플래시 메모리 소자 중 본 발명과 관련된 영역만을 도시하였다. 이외의 영역은 일반적인 플래시 메모리 소자와 동일한 구성을 가지므로 도시를 생략하기로 한다.1A to 1D show only regions related to the present invention among all flash memory devices. Since the other areas have the same configuration as a general flash memory device, illustration thereof will be omitted.

먼저, 도 1a에 도시된 바와 같이, 액티브 영역과 필드 영역으로 정의된 반도체 기판(10)의 액티브 영역 내부에 웰 형성을 위한 이온주입 공정을 통해 N웰(Nwell)(11) 및 P웰(Pwell)(12)을 각각 형성한다. First, as illustrated in FIG. 1A, an N well 11 and a P well through an ion implantation process for forming a well inside an active region of a semiconductor substrate 10 defined as an active region and a field region. 12) are formed respectively.

이후, STI(Shallow Trench Isolation) 공정을 실시하여 N웰(11) 및 P웰(12) 을 구분하는 소자분리막(14)를 형성한다. Thereafter, a shallow trench isolation (STI) process is performed to form an isolation layer 14 that separates the N well 11 and the P well 12.

이를 구체적으로 설명하면, N웰(11) 및 P웰(12)이 형성된 반도체 기판(10)상에 반도체 기판(10) 상부 표면의 결정 결함 억제 또는 표면처리를 위하여 패드 산화막(미도시)을 형성한 후, 패드 산화막(미도시) 상에 패드 질화막(미도시)을 형성하여 패드 산화막 및 패드 질화막이 순차적으로 적층된 하드 마스크막을 형성한다.Specifically, a pad oxide film (not shown) is formed on the semiconductor substrate 10 having the N wells 11 and the P wells 12 formed thereon to suppress crystal defects or surface treatment of the upper surface of the semiconductor substrate 10. Thereafter, a pad nitride film (not shown) is formed on the pad oxide film (not shown) to form a hard mask film in which the pad oxide film and the pad nitride film are sequentially stacked.

이 경우 패드질화막은 실리콘나이트라이드(SiN)로 형성되며, 후술할 공정에서 시행하는 화학 기계적 연마(Chemical Mechanical Polishing: CMP)시 정지막(Stop layer)으로 사용된다. 또한, 패드산화막은 이러한 패드 질화막으로 인한 스트레스를 제거하기 위한 버퍼(Buffer) 역할을 한다. In this case, the pad nitride film is formed of silicon nitride (SiN), and is used as a stop layer during chemical mechanical polishing (CMP). In addition, the pad oxide film serves as a buffer for removing stress caused by the pad nitride film.

이후, 액티브 영역을 형성하기 위해 포토레지스트막을 도포한 후, 노광 및 현상공정으로 하드마스크막 위에 소자분리막이 형성될 패드 질화막 표면을 노출시키는 개구부들을 갖는 포토레지스트막 패턴(미도시)을 형성한다. Thereafter, a photoresist film is applied to form an active region, and then a photoresist film pattern (not shown) having openings exposing the pad nitride film surface on which the device isolation film is to be formed is formed on the hard mask film by an exposure and development process.

그리고, 포토레지스트 패턴을 식각마스크로 이용하여 노출된 영역의 패드 산화막 및 패드 질화막을 선택적으로 제거하여 식각된 패드 산화막 패턴 및 패드 질화막 패턴으로 이루어진 하드마스크막 패턴을 형성한다. 그 다음, 포토레지스트 패턴을 제거하고, 하드 마스크막 패턴을 식각마스크로 이용하여 반도체 기판(10)의 노출 표면을 일정 깊이로 식각하여 트렌치를 형성한다. The pad oxide layer and the pad nitride layer of the exposed region are selectively removed using the photoresist pattern as an etching mask to form a hard mask layer pattern including the etched pad oxide layer pattern and the pad nitride layer pattern. Next, the photoresist pattern is removed, and the exposed surface of the semiconductor substrate 10 is etched to a predetermined depth using a hard mask layer pattern as an etching mask to form a trench.

다음으로, 트랜치가 매립되도록 반도체 기판(10) 전면에 매립 절연막을 형성한다. 이후, 매립 절연막에 CMP를 이용한 평탄화 공정을 수행하여 소자분리막(14)을 형성한 후, 질화막 패턴 상에 남아있을 수 있는 매립 절연막을 제거한다. 이어 서, 세정공정을 통해 패드 산화막 패턴, 질화막 패턴을 제거한다. Next, a buried insulating film is formed on the entire surface of the semiconductor substrate 10 to fill the trench. Subsequently, after forming the device isolation layer 14 by performing a planarization process using CMP on the buried insulating film, the buried insulating film that may remain on the nitride film pattern is removed. Subsequently, the pad oxide film pattern and the nitride film pattern are removed through a cleaning process.

이어서, 도 1b에 도시된 바와 같이, 소자분리막(14)을 포함한 반도체 기판(10) 전면에 산화공정(Oxidation)을 통해 게이트 산화막(15)을 형성한 후, 형성된 게이트 산화막(15) 전면에 폴리실리콘막을 형성한다. 이때, 폴리실리콘막은 포스포러스가 도핑된 폴리실리콘막이다. 이어서, 폴리실리콘막을 패터닝하여 N웰(11), P웰(12) 및 소자분리막(14) 상에 걸치는 하부 폴리실리콘막(16)을 형성한다.Subsequently, as shown in FIG. 1B, the gate oxide film 15 is formed on the entire surface of the semiconductor substrate 10 including the device isolation layer 14 through an oxidation process, and then the poly is formed on the entire surface of the formed gate oxide film 15. A silicon film is formed. In this case, the polysilicon film is a polysilicon film doped with phosphorus. Subsequently, the polysilicon film is patterned to form a lower polysilicon film 16 on the N well 11, the P well 12, and the device isolation film 14.

다음으로, 도 1c에 도시된 바와 같이, 형성된 하부 폴리실리콘막(16)을 포함한 반도체 기판(10) 전면에 질화막을 형성하고, 에치백 공정을 거쳐 하부 폴리실리콘막막(16)의 양측벽에 사이드월(20)을 형성한다. Next, as shown in FIG. 1C, a nitride film is formed on the entire surface of the semiconductor substrate 10 including the formed lower polysilicon film 16, and sidewalls are formed on both side walls of the lower polysilicon film 16 through an etch back process. Form month 20.

이후, 사이드월(20), 하부 폴리실리콘막(16)을 포함한 반도체 기판(10) 전면에 게이트간 절연막용 ONO막(Oxide/nitride/Oxide)을 형성하고, 형성된 ONO막을 하부 폴리실리콘막(16) 상에만 남도록 식각하여 하부 폴리실리콘막(16) 상에 게이트간 절연막(18)을 형성한다. Thereafter, an ONO film (Oxide / nitride / Oxide) for an inter-gate insulating film is formed on the entire surface of the semiconductor substrate 10 including the sidewall 20 and the lower polysilicon film 16, and the formed ONO film is formed on the lower polysilicon film 16. The gate-to-gate insulating film 18 is formed on the lower polysilicon film 16 by etching so as to remain only on the bottom surface.

그리고나서, 도 1d에 도시된 바와 같이, 상기 결과물 전면에 폴리실리콘막을 형성한 후 이어 형성된 폴리실리콘막을 식각하여 게이트간 절연막(18) 상에 하부 폴리실리콘막(16)보다 상대적으로 작게 상부 폴리실리콘막(22)을 형성한다. Then, as shown in FIG. 1D, the polysilicon film is formed on the entire surface of the resultant, and then the formed polysilicon film is etched to make the upper polysilicon relatively smaller than the lower polysilicon film 16 on the inter-gate insulating film 18. The film 22 is formed.

이때, 상부 폴리실리콘막(22)을 위한 식각공정시 게이트간 절연막(18)을 이루는 ONO막 중 탑산화막이 식각정지막 역할을 하게 되며, 하부 폴리실리콘(16)의 양측벽에 형성된 사이드월(20)로 인하여 상부 폴리실리콘막(22)을 하부 폴리실리콘 막(16)보다 작게 식각하는 과정에서 하부 폴리실리콘막(16)의 양측벽에 상부 폴리실리콘막(22)의 잔여물이 남게되는 현상을 방지할 수 있다. At this time, during the etching process for the upper polysilicon film 22, the top oxide film of the ONO film forming the inter-gate insulating film 18 serves as an etch stop film, the sidewalls formed on both side walls of the lower polysilicon 16 ( 20) a residue of the upper polysilicon layer 22 remains on both sidewalls of the lower polysilicon layer 16 during the etching of the upper polysilicon layer 22 smaller than the lower polysilicon layer 16. Can be prevented.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여 져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1a 내지 도 1d는 본 발명에 따른 플래시 메모리 소자의 제조 공정을 도시한 단면도.1A to 1D are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

Claims (6)

액티브 영역과 필드 영역을 정의하기 위해 액티브 영역에 제 1 도전형 웰 및 제 2 도전형 웰이 각각 형성된 반도체 기판에 소자분리막을 형성하는 단계와,Forming an isolation layer on a semiconductor substrate having a first conductivity type well and a second conductivity type well in the active region to define an active region and a field region, 상기 반도체 기판 상에 하부 폴리실리콘막을 형성하는 단계와,Forming a lower polysilicon film on the semiconductor substrate; 상기 하부 폴리실리콘막의 양측벽에 사이드월을 형성하는 단계와,Forming sidewalls on both sidewalls of the lower polysilicon film; 상기 하부 폴리실리콘막 상에 게이트간 절연막을 형성하는 단계와, Forming an inter-gate insulating film on the lower polysilicon film; 상기 게이트간 절연막 상에 상부 폴리실리콘막을 형성하는 단계를 포함하는 것을 특징으로 하는 플래시 메모리 소자의 제조방법. And forming an upper polysilicon film on the inter-gate insulating film. 제 1항에 있어서,The method of claim 1, 상기 하부 폴리실리콘막은 상기 제 1 도전형 웰, 제 2 도전형 웰 및 소자분리막에 걸쳐서 형성되는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.And the lower polysilicon layer is formed over the first conductivity type well, the second conductivity type well, and the device isolation film. 제 1항에 있어서,The method of claim 1, 상기 사이드월은 질화막(Nitride)으로 형성되는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.The sidewall is formed of a nitride film (Nitride), characterized in that the flash memory device manufacturing method. 제 1항에 있어서,The method of claim 1, 상기 게이트간 절연막은 ONO막(Oxide/Nitride/Oxide)로 형성되는 것을 특징 으로 하는 플래시 메모리 소자의 제조방법.And the inter-gate insulating film is formed of an ONO film (Oxide / Nitride / Oxide). 제 1항에 있어서,The method of claim 1, 상기 소자분리막을 형성한 후에 상기 반도체 기판 전면에 게이트 산화막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.And forming a gate oxide film on the entire surface of the semiconductor substrate after forming the device isolation film. 제 1항에 있어서,The method of claim 1, 상기 상부 폴리실리콘막은 상기 하부 폴리실리콘막에 비해 상대적으로 작게 형성되는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.And the upper polysilicon layer is formed to be relatively smaller than the lower polysilicon layer.
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