KR20100111008A - Circuit of regulating - Google Patents
Circuit of regulating Download PDFInfo
- Publication number
- KR20100111008A KR20100111008A KR1020090029356A KR20090029356A KR20100111008A KR 20100111008 A KR20100111008 A KR 20100111008A KR 1020090029356 A KR1020090029356 A KR 1020090029356A KR 20090029356 A KR20090029356 A KR 20090029356A KR 20100111008 A KR20100111008 A KR 20100111008A
- Authority
- KR
- South Korea
- Prior art keywords
- voltage
- output
- node
- input
- voltage divider
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
The present invention relates to a regulating circuit that separates the source voltage input and the regulating operation.
In the case of a semiconductor memory device, particularly a nonvolatile semiconductor memory device that can be electrically erased and programmed, FN tunneling (FN tunneling) may be performed to perform an erase operation for erasing data stored in a memory cell and a program operation for storing data in the memory cell. Fowler-Nordheim tunneling and hot electron injection are used.
An erase operation is performed before a program operation for storing data in the memory cell is performed through the F-N tunneling. The F-N tunneling means to discharge electrons accumulated on the floating gate of the memory cell to the source region, where a high voltage is applied to the source region of the memory cell.
When the erase operation is completed, the memory cell to be programmed is programmed, and the program method used here follows the hot electron injection method. The hot electron injection means that electrons in the channel region adjacent to the drain region of the memory cell are injected into the floating gate of the memory cell. At this time, a high voltage is applied to the control gate of the memory cell. In order to perform the erase and program operations according to the above scheme, a high voltage is typically required between 15V and 20V. In general, a semiconductor memory device operating under a low power supply voltage includes a high voltage generation circuit that generates the high voltage in a chip.
There is a need for a regulating circuit for constantly regulating a source voltage V source having a high voltage level for which a high voltage generating circuit is required.
In a nonvolatile memory device, a high voltage is used in operations such as program, data read and erase. Since the high voltage is continuously input while the program, data read or erase operation is performed, the input of the source voltage Vsource input to the regulating circuit and the operation of the regulating circuit are synchronized.
However, when the local self boosting method is used to prevent disturbance in the program operation of the nonvolatile memory device, the high voltage is not supplied constantly, but the high voltage is supplied or cut according to each operation.
Therefore, it is necessary to control the operation of the regulating circuit separately from the input of the source voltage Vsource.
Accordingly, an aspect of the present invention is to provide a regulating circuit capable of controlling the operation of the regulating circuit separately from the input of the source voltage.
Regulating circuit according to a feature of the invention,
A first voltage divider for distributing a source voltage; A switching element for outputting the source voltage through an output terminal in response to an output of the first voltage divider; A second voltage divider for dividing a voltage of the output terminal; And a controller for comparing the output voltage of the second voltage divider with a reference voltage and controlling the operation of the first voltage divider according to the output thereof. When outputting the source voltage through the output terminal, the second voltage When the output of the divider is cut off and the regulated voltage is output through the output terminal, the second voltage divider may operate normally.
The first voltage divider includes a first transistor and a diode having a degree of turning on according to an output of the controller and a first resistor connected in series between an input terminal of the source voltage and a ground node.
The second voltage divider may include: a second transistor operated by an enable signal and trimming resistors connected between the output terminal and the first node; And a third transistor operated by the enable signal and a second resistor connected between the first node and a ground node.
The control unit includes a comparator for comparing the voltage of the first node and the reference voltage of the second voltage divider and outputting the result.
The trimming resistors may be changed in resistance by a trimming control signal.
When the enable signal is input at a low level, the source voltage is output to the output terminal through the switching terminal.
As described above, the regulating circuit according to the present invention can protect the regulating circuit by controlling the operation of the regulating circuit regardless of the input of the source voltage.
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.
1 shows a regulating circuit according to an embodiment of the present invention.
Referring to FIG. 1, the regulating
The first resistor R1 is connected between the node K1 and the node K2, and the first and second NMOS transistors N1 and N2 are connected in series between the node K2 and the ground node. The first voltage V1 is input to the gate of the first NMOS transistor N1, and the second NMOS transistor N2 is input in the form of a diode.
The node K1 is a node into which a source voltage Vsource having a high voltage level is input, and the node K2 is a node from which a second voltage V2 is output.
The third NMOS transistor N3 is connected between the node K1 and the node K3, and the second voltage V2 of the node K2 is input to the gate of the third NMOS transistor N3. The third voltage V3, which is an output voltage of the regulating
The
The second resistor R2 and the fourth NMOS transistor N4 are connected in series between the node K4 and the ground node, and the enable signal EN is input to the gate of the fourth NMOS transistor N4.
At the node K4, the feedback voltage Vf is output. The feedback voltage Vf is input to the non-inverting terminal + of the comparator COM.
The input voltage Vi is input to the inverting terminal (-) of the comparator COM. The comparator COM1 compares the input voltage Vi and the feedback voltage Vf, and input voltage Vi and the feedback voltage Vf. The first voltage V1 is output according to the voltage difference of?
The operation of the regulating
First, the source voltage Vsource is input for the operation of the regulating
Initially, the comparator COM outputs a first voltage V1 that causes the first NMOS transistor N1 to remain turned off by the input voltage Vi because the feedback voltage Vf is at 0V.
When the first NMOS transistor N1 is turned off, the same voltage as the source voltage Vsource is input to the node K2 and the third NMOS transistor N3 is turned on by the source voltage Vsource level.
The voltage level of the third voltage V3, which is an output voltage, is a value of a resistance value obtained by combining the resistance value of the
When the source voltage Vsource is raised and the feedback voltage Vf is higher than the input voltage Vi, the comparator COM is configured to adjust the first voltage V1 according to the voltage difference between the input voltage Vi and the feedback voltage Vf. Change the voltage level to output.
The degree to which the first NMOS transistor N1 is turned on varies according to the voltage level of the first voltage V1, thereby changing the resistance of the first and second NMOS transistors N1 and N2.
Therefore, the voltage at the node K2 is a voltage obtained by dividing the source voltage Vsource according to the resistance of the first resistor R1 and the first and second NMOS transistors N1 and N2. The degree of turning on the third NMOS transistor N3 varies according to the second voltage level, thereby changing the resistance value of the third NMOS transistor N3.
Accordingly, the third voltage V3 is a voltage at which the source voltage Vsource is output through the third NMOS transistor N3.
When the third NMOS transistor N3 is completely turned on, the source voltage Vsource is output as it is to the node K3. At this time, the voltage level of the third voltage V3 is output as low as the threshold voltage of the third NMOS transistor N3.
The
The comparator COM receiving the feedback voltage Vf and the first and second NMOS transistors N1 and N2 serve to regulate the voltage level of the third voltage V3 to be kept constant.
The regulating
In this case, the source voltage Vsource is commonly input to all the regulating
However, when it is necessary to stop the operation of some regulating
When the enable signal EN becomes low while the source voltage Vsource is input, the fourth NMOS transistor N4 is turned off and the operation of the comparator COM is stopped. When the operation of the comparator COM is stopped, since the first NMOS transistor N1 is turned off, the source voltage Vsource is input to the node K2 as it is. Accordingly, the third NMOS transistor N3 is completely turned on at the high source voltage Vsource.
Therefore, the source voltage Vsource is output to the node K3 when the regulating operation is stopped. That is, a path through which the source voltage Vsource passes through the third NMOS transistor N3 is formed.
At this time, the third voltage V3 may flow into the comparator COM as the feedback voltage Vf through the trimming
As mentioned above, the third voltage V3 has a high voltage level because the source voltage Vsource is a voltage output with almost no voltage loss. When the high voltage is equal to or higher than the breakdown voltage of the comparator COM, the comparator COM is broken and does not operate normally.
Therefore, the comparator COM may be protected by configuring the trimming
2 illustrates the trimming
Referring to FIG. 2, the trimming
The first to Nth trimming resistors Rt1 to RtN are connected in series between the node K3 and the node K5, and the fifth NMOS transistor N5 is connected between the node K4 and the node K5. Connected. The enable signal EN is input to the gate of the fifth NMOS transistor N5.
Transistors are respectively connected between the contact point and the node K4 between the first to Nth trimming resistors Rt1 to RtN, and the trimming signals S <0: N> are input to the gates of the transistors.
When the enable signal EN is input at the low level from the trimming
Therefore, if the regulating
Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.
1 shows a regulating circuit according to an embodiment of the present invention.
2 illustrates a trimming resistor of FIG. 1.
* Brief description of the main parts of the drawings *
100: regulating circuit 110: trimming resistor
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090029356A KR20100111008A (en) | 2009-04-06 | 2009-04-06 | Circuit of regulating |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090029356A KR20100111008A (en) | 2009-04-06 | 2009-04-06 | Circuit of regulating |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20100111008A true KR20100111008A (en) | 2010-10-14 |
Family
ID=43131390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020090029356A KR20100111008A (en) | 2009-04-06 | 2009-04-06 | Circuit of regulating |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20100111008A (en) |
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2009
- 2009-04-06 KR KR1020090029356A patent/KR20100111008A/en not_active Application Discontinuation
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