KR20100100632A - Plasma etching method, plasma etching apparatus and computer-readable storage medium - Google Patents

Plasma etching method, plasma etching apparatus and computer-readable storage medium Download PDF

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KR20100100632A
KR20100100632A KR1020100018703A KR20100018703A KR20100100632A KR 20100100632 A KR20100100632 A KR 20100100632A KR 1020100018703 A KR1020100018703 A KR 1020100018703A KR 20100018703 A KR20100018703 A KR 20100018703A KR 20100100632 A KR20100100632 A KR 20100100632A
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plasma etching
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flow rate
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타카히토 무카와
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도쿄엘렉트론가부시키가이샤
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
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    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
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Abstract

PURPOSE: A plasma etching method, a plasma etching apparatus, and a computer storage media are provided to implement a plasma etching process with respect to an anti-reflective film at high etching rate by improving the roughness of an argon fluoride photo-resist. CONSTITUTION: An organic film(101) is formed on a semiconductor wafer(W). An anti-reflective film(102) including silicon is formed on the organic film. An argon fluoride photo-resist film(103) is formed on the anti-reflective film. An opening(104) is formed on the argon fluoride photo-resist film. An etching process with respect to the anti-reflective film is implemented using the argon fluoride photo-resist film as a mask.

Description

플라즈마 에칭 방법, 플라즈마 에칭 장치 및 컴퓨터 기억 매체{PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS AND COMPUTER-READABLE STORAGE MEDIUM}Plasma Etching Method, Plasma Etching Apparatus, and Computer Storage Media {PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS AND COMPUTER-READABLE STORAGE MEDIUM}

본 발명은 피처리 기판에 형성된 Si를 함유하는 반사 방지막을 ArF 포토레지스트를 마스크로 하여 에칭하는 플라즈마 에칭 방법, 플라즈마 에칭 장치 및 컴퓨터 기억 매체에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma etching method, a plasma etching apparatus, and a computer storage medium for etching an antireflection film containing Si formed on a substrate to be processed using ArF photoresist as a mask.

종래부터, 반도체 장치의 제조 공정에서는 포토레지스트 마스크를 개재하여 플라즈마 에칭 처리를 행하여, 실리콘 산화막 등의 피에칭막을 원하는 패턴으로 형성하는 것이 행해지고 있다. 또한, 이러한 플라즈마 에칭에서는 회로 패턴의 미세화에 대응하기 위하여, 보다 파장이 짧은 광에 의해 노광을 행하는 ArF 포토레지스트가 다용되도록 되어 있다. Conventionally, in the manufacturing process of a semiconductor device, plasma etching process is performed through a photoresist mask, and forming etching target films, such as a silicon oxide film, in a desired pattern is performed. In order to cope with miniaturization of the circuit pattern in such plasma etching, an ArF photoresist for exposing with light having a shorter wavelength is used abundantly.

상기의 ArF 포토레지스트를 마스크로서 사용하여 플라즈마 에칭을 행할 경우, ArF 포토레지스트의 플라즈마 내성이 낮기 때문에, ArF 포토레지스트에 대한 플라즈마에 의한 데미지를 경감시키기 위한 제안이 이루어져 있다. 이러한 기술로서, ArF 포토레지스트의 하층에 형성된 반사 방지막을 에칭할 때에 CF4 등의 CF계의 가스와 O2 가스를 포함하는 혼합 가스 등으로 이루어지는 에칭 가스를 이용하여, 저압에서 플라즈마 에칭을 행하는 기술이 알려져 있다(예를 들면, 특허 문헌 1 참조).
When plasma etching is performed using the ArF photoresist as a mask, since the plasma resistance of the ArF photoresist is low, a proposal has been made to reduce the damage caused by plasma to the ArF photoresist. As such a technique, a technique of performing plasma etching at low pressure using an etching gas composed of a CF-based gas such as CF 4 and a mixed gas containing O 2 gas, etc., when etching the antireflection film formed on the lower layer of the ArF photoresist. This is known (for example, refer patent document 1).

일본특허공개공보2006-32721호Japanese Patent Publication No. 2006-32721

상기와 같은 ArF 포토레지스트를 마스크로 한 플라즈마 에칭에서는, ArF 포토레지스트의 데미지(거칠기)를 억제하면, 높은 에칭 레이트 및 충분한 선택비를 얻을 수 없다고 하는 문제가 있다. 특히, 종래에는 실리콘을 함유하는 반사 방지막(Si-ARC)을 ArF 포토레지스트의 데미지(거칠기)를 억제하면서 높은 에칭 레이트 및 충분한 선택비로 플라즈마 에칭할 수 있는 기술이 없었으므로, 이러한 기술의 개발이 요망되었다. In plasma etching using the ArF photoresist as described above, there is a problem that if the damage (roughness) of the ArF photoresist is suppressed, a high etching rate and a sufficient selectivity cannot be obtained. In particular, since there is no conventional technique for plasma etching silicon-containing anti-reflective film (Si-ARC) at a high etching rate and sufficient selectivity while suppressing the damage (roughness) of ArF photoresist, development of such a technique is desired. It became.

본 발명은 상기 종래의 사정에 대처하여 이루어진 것으로, ArF 포토레지스트의 데미지(거칠기)를 억제하면서 실리콘을 함유하는 반사 방지막(Si-ARC)을 높은 에칭 레이트 및 충분한 선택비로 플라즈마 에칭할 수 있는 플라즈마 에칭 방법, 플라즈마 에칭 장치 및 컴퓨터 기억 매체를 제공하고자 하는 것이다.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and is capable of plasma etching an anti-reflection film (Si-ARC) containing silicon at a high etching rate and a sufficient selectivity while suppressing damage (roughness) of ArF photoresist. It is an object of the present invention to provide a method, a plasma etching apparatus and a computer storage medium.

청구항 1의 플라즈마 에칭 방법은, 처리 챔버 내에 배치되고 기판이 재치되는 하부 전극과, 상기 처리 챔버 내에 상기 하부 전극과 대향하도록 배치된 상부 전극과, 상기 처리 챔버 내로 처리 가스를 공급하는 처리 가스 공급 기구와, 상기 하부 전극과 상기 상부 전극의 사이에 고주파 전력을 인가하는 고주파 전원을 구비한 플라즈마 에칭 장치를 이용하고, 상기 기판에 형성된 ArF 포토레지스트를 마스크로 하여 상기 ArF 포토레지스트의 하층에 위치하는 Si를 함유한 반사 방지막을 상기 처리 가스의 플라즈마에 의해 에칭하는 플라즈마 에칭 방법으로서, 상기 처리 가스로서 CF계 가스 및 CHF계 가스 중 적어도 어느 하나와 CF3I 가스와 산소 가스를 포함한 혼합 가스를 사용하고, 또한 상기 상부 전극에 직류 전압을 인가하는 것을 특징으로 한다. The plasma etching method of claim 1 includes a lower electrode disposed in a processing chamber and on which a substrate is placed, an upper electrode disposed to face the lower electrode in the processing chamber, and a processing gas supply mechanism supplying a processing gas into the processing chamber. And Si positioned under the ArF photoresist using a ArF photoresist formed on the substrate as a mask, using a plasma etching apparatus having a high frequency power source for applying high frequency power between the lower electrode and the upper electrode. A plasma etching method for etching an anti-reflection film containing a film by the plasma of the processing gas, using at least one of a CF gas and a CHF gas, and a mixed gas including a CF 3 I gas and an oxygen gas as the processing gas. In addition, a DC voltage is applied to the upper electrode.

청구항 2의 플라즈마 에칭 방법은, 청구항 1에 기재된 플라즈마 에칭 방법으로서, 상기 상부 전극에 인가하는 직류 전압의 전압치가 -1000 V ~ -300 V의 범위인 것을 특징으로 한다.The plasma etching method of claim 2 is the plasma etching method according to claim 1, wherein the voltage value of the DC voltage applied to the upper electrode is in a range of -1000 V to -300 V.

청구항 3의 플라즈마 에칭 방법은, 청구항 1 또는 2에 기재된 플라즈마 에칭 방법으로서, 상기 처리 가스가 CF4 가스와 CF3I 가스와 산소 가스의 혼합 가스이며, CF4 가스 유량과 CF3I 가스 유량의 합계에 대한 CF3I 가스 유량의 비(CF3I 가스 유량 / (CF4 가스 유량 + CF3I 가스 유량))가 0.1 ~ 0.3의 범위인 것을 특징으로 한다.The plasma etching method of claim 3 is the plasma etching method according to claim 1 or 2, wherein the processing gas is a mixed gas of CF 4 gas, CF 3 I gas, and oxygen gas, and the CF 4 gas flow rate and CF 3 I gas flow rate The ratio of the CF 3 I gas flow rate to the sum (CF 3 I gas flow rate / (CF 4 gas flow rate + CF 3 I gas flow rate)) is in the range of 0.1 to 0.3.

청구항 4의 플라즈마 에칭 방법은, 청구항 1 내지 3 항 중 어느 한 항에 기재된 플라즈마 에칭 방법으로서, 상기 하부 전극에 전력치가 100 W ~ 300 W인 바이어스용 고주파 전력을 인가하는 것을 특징으로 한다.The plasma etching method of claim 4 is the plasma etching method according to any one of claims 1 to 3, wherein a bias high frequency power having a power value of 100 W to 300 W is applied to the lower electrode.

청구항 5의 플라즈마 에칭 방법은, 청구항 1 내지 4 중 어느 한 항에 기재된 플라즈마 에칭 방법으로서, 상기 Si를 함유한 반사 방지막의 에칭 전에 상기 ArF 포토레지스트를 트리트먼트하는 트리트먼트 공정을 행하는 것을 특징으로 한다.The plasma etching method of claim 5 is the plasma etching method according to any one of claims 1 to 4, wherein a treatment step of treating the ArF photoresist is performed before etching the antireflective film containing Si. .

청구항 6의 플라즈마 에칭 방법은, 청구항 5에 기재된 플라즈마 에칭 방법으로서, 상기 트리트먼트 공정은 H2 가스, 또는 H2 가스와 N2 가스, 또는 H2 가스와Ar 가스를 처리 가스로 하고 당해 처리 가스를 플라즈마화하여 상기 ArF 포토레지스트에 작용시키는 플라즈마 처리인 것을 특징으로 한다. The plasma etching method of claim 6 is the plasma etching method according to claim 5, wherein the treatment step is performed by using H 2 gas or H 2 gas and N 2 gas, or H 2 gas and Ar gas as the processing gas. It is characterized in that the plasma treatment to the plasma to act on the ArF photoresist.

청구항 7의 플라즈마 에칭 장치는, 처리 챔버 내에 배치되고 기판이 재치되는 하부 전극과, 상기 처리 챔버 내에 상기 하부 전극과 대향하도록 배치된 상부 전극과, 상기 처리 챔버 내로 처리 가스를 공급하는 처리 가스 공급 기구와, 상기 하부 전극과 상기 상부 전극의 사이에 고주파 전력을 인가하는 고주파 전원을 구비한 플라즈마 에칭 장치로서, 상기 기판에 형성된 ArF 포토레지스트를 마스크로 하여 상기 ArF 포토레지스트의 하층에 위치하는 Si를 함유한 반사 방지막을 상기 처리 가스의 플라즈마에 의해 에칭할 때에, 상기 처리 가스 공급 기구로부터 처리 가스로서 CF계 가스 및 CHF계 가스 중 적어도 어느 하나와 CF3I 가스와 산소 가스를 포함한 혼합 가스를 공급하고, 또한 상기 상부 전극에 직류 전원으로부터 직류 전압을 인가하도록 제어하는 제어부를 가지는 것을 특징으로 한다.The plasma etching apparatus of claim 7 includes a lower electrode disposed in a processing chamber and on which a substrate is placed, an upper electrode disposed in the processing chamber so as to face the lower electrode, and a processing gas supply mechanism supplying a processing gas into the processing chamber. And a high-frequency power source for applying high-frequency power between the lower electrode and the upper electrode, the plasma etching apparatus comprising Si positioned under the ArF photoresist using an ArF photoresist formed on the substrate as a mask. When the anti-reflection film is etched by the plasma of the processing gas, at least one of CF-based gas and CHF-based gas, mixed gas including CF 3 I gas and oxygen gas, is supplied from the processing gas supply mechanism as the processing gas. And controlling to apply a DC voltage from the DC power supply to the upper electrode. It characterized in that it has parts.

청구항 8의 컴퓨터 기억 매체는, 컴퓨터 상에서 동작하는 제어 프로그램이 기억된 컴퓨터 기억 매체로서, 상기 제어 프로그램은 실행 시에 청구항 1 내지 청구항 6 중 어느 한 항에 기재된 플라즈마 에칭 방법이 행해지도록 플라즈마 에칭 장치를 제어하는 것을 특징으로 한다.The computer storage medium of claim 8 is a computer storage medium in which a control program operating on a computer is stored, and the control program includes a plasma etching apparatus such that the plasma etching method according to any one of claims 1 to 6 is performed at the time of execution. It is characterized by controlling.

본 발명에 따르면, ArF 포토레지스트의 데미지(거칠기)를 억제하면서 실리콘을 함유한 반사 방지막(Si-ARC)을 높은 에칭 레이트 및 충분한 선택비로 플라즈마 에칭할 수 있는 플라즈마 에칭 방법, 플라즈마 에칭 장치 및 컴퓨터 기억 매체를 제공할 수 있다.According to the present invention, a plasma etching method, a plasma etching apparatus and a computer memory capable of plasma etching an anti-reflective film (Si-ARC) containing silicon at a high etching rate and a sufficient selectivity while suppressing damage (roughness) of ArF photoresist. A medium can be provided.

도 1a 및 1b는 본 발명의 플라즈마 에칭 방법의 실시예에 따른 반도체 웨이퍼의 단면 구성을 도시한 도이다.
도 2는 본 발명의 실시예에 따른 플라즈마 에칭 장치의 개략 구성을 도시한 도이다.
도 3a 및 3b는 실험예 1에 따른 ArF 포토레지스트 상태를 나타낸 현미경 사진이다.
도 4a 및 4b는 비교예에 따른 ArF 포토레지스트 상태를 나타낸 현미경 사진이다.
도 5는 바이어스용 고주파 전력과 에칭 레이트의 관계를 나타낸 그래프이다.
도 6은 바이어스용 고주파 전력과 선택비의 관계를 나타내는 그래프.
도 7은 직류 전압과 선택비의 관계를 나타낸 그래프이다.
도 8은 CF3I 유량비와 에칭 레이트의 관계를 나타낸 그래프이다.
도 9는 CF3I 유량비와 선택비의 관계를 나타낸 그래프이다.
도 10a 내지 도 10c는 CF3I 유량의 상위(相違)에 따른 ArF 포토레지스트 상태의 상위를 나타낸 현미경 사진이다.
도 11은 압력과 에칭 레이트의 관계를 나타낸 그래프이다.
도 12는 압력과 선택비의 관계를 나타낸 그래프이다.1A and 1B are cross-sectional views of a semiconductor wafer according to an embodiment of the plasma etching method of the present invention.
2 is a view showing a schematic configuration of a plasma etching apparatus according to an embodiment of the present invention.
3A and 3B are micrographs showing an ArF photoresist state according to Experimental Example 1. FIG.
4A and 4B are micrographs showing an ArF photoresist state according to a comparative example.
5 is a graph showing the relationship between the bias high frequency power and the etching rate.
6 is a graph showing a relationship between a bias high frequency power and a selectivity ratio;
7 is a graph showing the relationship between the DC voltage and the selection ratio.
8 is a graph showing the relationship between the CF 3 I flow rate ratio and the etching rate.
9 is a graph showing the relationship between the CF 3 I flow rate ratio and the selection ratio.
10A to 10C are micrographs showing differences in ArF photoresist states according to differences in CF 3 I flow rates.
11 is a graph showing the relationship between pressure and etching rate.
12 is a graph showing the relationship between pressure and selectivity.

이하, 본 발명의 실시예에 대하여 도면을 참조하여 설명한다. 도 1a 및 도1b는 본 실시예에 따른 플라즈마 에칭 방법에서의 피처리 기판으로서의 반도체 웨이퍼의 단면 구성을 확대하여 도시한 것이다. 또한, 도 2는 본 실시예에 따른 플라즈마 에칭 장치의 구성을 도시한 것이다. 우선, 도 2를 참조하여 플라즈마 에칭 장치의 구성에 대하여 설명한다.Best Mode for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B show an enlarged cross-sectional structure of a semiconductor wafer as a substrate to be processed in the plasma etching method according to the present embodiment. 2 shows the configuration of the plasma etching apparatus according to the present embodiment. First, the structure of a plasma etching apparatus is demonstrated with reference to FIG.

플라즈마 에칭 장치는 기밀하게 구성되고, 전기적으로 접지 전위로 된 처리 챔버(1)를 가지고 있다. 이 처리 챔버(1)는 원통 형상으로 되어, 예를 들면 알루미늄 등으로 구성되어 있다. 처리 챔버(1) 내에는 피처리 기판인 반도체 웨이퍼(W)를 수평하게 지지하는 재치대(2)가 설치되어 있다. 재치대(2)는, 예를 들면 알루미늄 등으로 구성되어 있고, 하부 전극으로서의 기능을 가진다. 이 재치대(2)는 절연판(3)을 개재하여 도체의 지지대(4)에 지지되어 있다. 또한, 재치대(2)의 상방의 외주에는, 예를 들면 단결정 실리콘으로 형성된 포커스 링(5)이 설치되어 있다. 또한, 재치대(2) 및 지지대(4)의 주위를 둘러싸도록, 예를 들면 석영 등으로 이루어지는 원통 형상의 내벽 부재(3a)가 설치되어 있다. The plasma etching apparatus is hermetically configured and has a processing chamber 1 which is electrically grounded. This processing chamber 1 has a cylindrical shape and is made of, for example, aluminum. In the processing chamber 1, a mounting table 2 for horizontally supporting a semiconductor wafer W as a substrate to be processed is provided. The mounting table 2 is made of aluminum, for example, and has a function as a lower electrode. This mounting table 2 is supported by the support base 4 of a conductor via the insulating plate 3. In addition, a focus ring 5 formed of, for example, single crystal silicon is provided on the outer circumference of the mounting table 2. Moreover, the cylindrical inner wall member 3a which consists of quartz etc. is provided so that the periphery of the mounting base 2 and the support stand 4 may be enclosed, for example.

재치대(2)에는 제 1 정합기(11a)를 개재하여 제 1 RF 전원(10a)이 접속되고, 또한 제 2 정합기(11b)를 개재하여 제 2 RF 전원(10b)이 접속되어 있다. 제 1 RF 전원(10a)은 플라즈마 발생용이며, 이 제 1 RF 전원(10a)으로부터는 소정 주파수(27 MHz 이상, 예를 들면 40 MHz)의 고주파 전력이 재치대(2)로 공급되도록 되어 있다. 또한, 제 2 RF 전원(10b)은 이온 주입용(바이어스용)이며, 이 제 2 RF 전원(10b)으로부터는 제 1 RF 전원(10a)보다 낮은 소정 주파수(13.56 MHz 이하, 예를 들면 2 MHz)의 고주파 전력이 재치대(2)로 공급되도록 되어 있다. 한편, 재치대(2)의 상방에는 재치대(2)와 평행하게 대향하도록 상부 전극으로서의 기능을 가지는 샤워 헤드(16)가 설치되어 있고, 샤워 헤드(16)와 재치대(2)는 한 쌍의 전극(상부 전극과 하부 전극)으로서 기능하도록 되어 있다.The mounting table 2 is connected to the first RF power supply 10a via the first matching unit 11a and further connected to the second RF power supply 10b via the second matching unit 11b. The first RF power supply 10a is for plasma generation, and high frequency power of a predetermined frequency (27 MHz or more, for example 40 MHz) is supplied to the mounting table 2 from the first RF power supply 10a. . The second RF power supply 10b is for ion implantation (for bias), and from this second RF power supply 10b, a predetermined frequency (13.56 MHz or less, for example, 2 MHz, lower than the first RF power supply 10a) is used. Is supplied to the mounting table 2. On the other hand, above the mounting table 2, a shower head 16 having a function as an upper electrode is provided so as to face in parallel with the mounting table 2, and the shower head 16 and the mounting table 2 are a pair. It serves to function as an electrode (upper electrode and lower electrode).

재치대(2)의 상면에는 반도체 웨이퍼(W)를 정전 흡착하기 위한 정전 척(6)이 설치되어 있다. 이 정전 척(6)은 절연체(6b) 사이에 전극(6a)을 개재하여 구성되어 있고, 전극(6a)에는 직류 전원(12)이 접속되어 있다. 그리고, 전극(6a)에 직류 전원(12)으로부터 직류 전압이 인가됨으로써, 쿨롱력에 의해 반도체 웨이퍼(W)가 흡착되도록 구성되어 있다. The electrostatic chuck 6 for electrostatically attracting the semiconductor wafer W is provided on the upper surface of the mounting table 2. The electrostatic chuck 6 is configured between the insulators 6b via an electrode 6a, and a DC power supply 12 is connected to the electrode 6a. Then, by applying a DC voltage from the DC power supply 12 to the electrode 6a, the semiconductor wafer W is absorbed by the Coulomb force.

지지대(4)의 내부에는 냉매 유로(4a)가 형성되어 있고, 냉매 유로(4a)에는 냉매 입구 배관(4b), 냉매 출구 배관(4c)이 접속되어 있다. 그리고, 냉매 유로(4a) 내에 적절한 냉매, 예를 들면 냉각수 등을 순환시킴으로써, 지지대(4) 및 재치대(2)를 소정의 온도로 제어 가능하도록 되어 있다. 또한, 재치대(2) 등을 관통하도록, 반도체 웨이퍼(W)의 이면측에 헬륨 가스 등의 냉열 전달용 가스(백 사이드 가스)를 공급하기 위한 백 사이드 가스 공급 배관(30)이 설치되어 있고, 이 백 사이드 가스 공급 배관(30)은 도시하지 않은 백 사이드 가스 공급원에 접속되어 있다. 이들 구성에 의해 재치대(2)의 상면에 정전 척(6)에 의해 흡착 보지(保持)된 반도체 웨이퍼(W)를 소정의 온도로 제어 가능하도록 되어 있다.A coolant flow path 4a is formed inside the support 4, and a coolant inlet pipe 4b and a coolant outlet pipe 4c are connected to the coolant flow path 4a. And the support stand 4 and the mounting stand 2 can be controlled to predetermined temperature by circulating a suitable refrigerant | coolant, for example, cooling water etc. in the refrigerant | coolant flow path 4a. Moreover, the back side gas supply piping 30 for supplying cold heat transfer gas (back side gas), such as helium gas, is provided in the back surface side of the semiconductor wafer W so that the mounting table 2 etc. may penetrate. This back side gas supply piping 30 is connected to the back side gas supply source which is not shown in figure. By these structures, the semiconductor wafer W attracted and held by the electrostatic chuck 6 on the upper surface of the mounting table 2 can be controlled at a predetermined temperature.

상기한 샤워 헤드(16)는 처리 챔버(1)의 천벽(天壁) 부분에 설치되어 있다. 샤워 헤드(16)는 본체부(16a)와 전극판을 이루는 상부 천판(16b)을 구비하고 있고, 절연성 부재(45)를 개재하여 처리 챔버(1)의 상부에 지지되어 있다. 본체부(16a)는 도전성 재료, 예를 들면 표면이 양극 산화 처리된 알루미늄으로 이루어지고, 그 하부에 상부 천판(16b)을 착탈 가능하게 지지할 수 있도록 구성되어 있다.The shower head 16 is provided in a ceiling wall portion of the processing chamber 1. The shower head 16 is provided with the upper top plate 16b which forms the main-body part 16a and an electrode plate, and is supported by the upper part of the processing chamber 1 via the insulating member 45. As shown in FIG. The main body portion 16a is made of a conductive material, for example, aluminum whose surface is anodized, and is configured to detachably support the upper top plate 16b at the lower portion thereof.

본체부(16a)의 내부에는 가스 확산실(16c)이 설치되고, 이 가스 확산실(16c)의 하부에 위치하도록, 본체부(16a)의 저부(底部)에는 다수의 가스 통류홀(16d)이 형성되어 있다. 또한, 상부 천판(16b)에는 당해 상부 천판(16b)을 두께 방향으로 관통하도록, 가스 도입홀(16e)이 상기한 가스 통류홀(16d)과 중첩되도록 설치되어 있다. 이러한 구성에 의해 가스 확산실(16c)로 공급된 처리 가스는 가스 통류홀(16d) 및 가스 도입홀(16e)을 거쳐 처리 챔버(1) 내로 샤워 형상으로 분산되어 공급되도록 되어 있다. 본체부(16a) 등에는 냉매를 순환시키기 위한 도시하지 않은 배관이 설치되어 있어 플라즈마 에칭 처리 중에 샤워 헤드(16)를 원하는 온도로 냉각할 수 있도록 되어 있다. A gas diffusion chamber 16c is provided inside the main body 16a, and a plurality of gas through holes 16d are provided at the bottom of the main body 16a so as to be located below the gas diffusion chamber 16c. Is formed. The upper top plate 16b is provided so that the gas introduction hole 16e overlaps the above-described gas flow hole 16d so as to penetrate the upper top plate 16b in the thickness direction. The process gas supplied to the gas diffusion chamber 16c by this structure is distributed and supplied to the process chamber 1 into the process chamber 1 via the gas flow hole 16d and the gas introduction hole 16e. Piping (not shown) for circulating the refrigerant is provided in the main body portion 16a and the like so that the shower head 16 can be cooled to a desired temperature during the plasma etching process.

상기한 본체부(16a)에는 가스 확산실(16c)로 처리 가스를 도입하기 위한 가스 도입구(16f)가 형성되어 있다. 이 가스 도입구(16f)에는 가스 공급 배관(15a)이 접속되어 있고, 이 가스 공급 배관(15a)의 타단(他端)에는 에칭용 또는 트리트먼트용의 처리 가스를 공급하는 처리 가스 공급원(15)이 접속되어 있다. 가스 공급 배관(15a)에는 상류측부터 차례로 매스 플로우 콘트롤러(MFC)(15b) 및 개폐 밸브(V1)가 설치되어 있다. 그리고, 처리 가스 공급원(15)으로부터 플라즈마 에칭을 위한 처리 가스로서, 예를 들면 CF4 가스와 CF3I 가스와 산소 가스의 혼합 가스가 가스 공급 배관(15a)을 거쳐 가스 확산실(16c)로 공급되고, 이 가스 확산실(16c)로부터 가스 통류홀(16d) 및 가스 도입홀(16e)을 거쳐 처리 챔버(1) 내로 샤워 형상으로 분산되어 공급된다.A gas introduction port 16f for introducing a processing gas into the gas diffusion chamber 16c is formed in the body portion 16a. A gas supply pipe 15a is connected to the gas inlet 16f, and a processing gas supply source 15 for supplying a processing gas for etching or treatment to the other end of the gas supply pipe 15a. ) Is connected. The gas supply piping 15a is provided with the mass flow controller (MFC) 15b and the opening / closing valve V1 sequentially from the upstream side. Then, as a processing gas for plasma etching from the processing gas supply source 15, for example, a mixed gas of CF 4 gas, CF 3 I gas, and oxygen gas passes through the gas supply pipe 15a to the gas diffusion chamber 16c. It is supplied and distributed in a shower shape from the gas diffusion chamber 16c to the processing chamber 1 via the gas through hole 16d and the gas introduction hole 16e.

상기한 상부 전극으로서의 샤워 헤드(16)에는 로우패스 필터(LPF)(51)를 개재하여 가변 직류 전원(52)이 전기적으로 접속되어 있다. 이 가변 직류 전원(52)은 온·오프 스위치(53)에 의해 급전(給電)의 온·오프가 가능하도록 되어 있다. 가변 직류 전원(52)의 전류·전압 및 온·오프 스위치(53)의 온·오프는, 후술하는 제어부(60)에 의해 제어되도록 되어 있다. 또한, 후술한 바와 같이, 제 1 RF 전원(10a), 제 2 RF 전원(10b)으로부터 고주파가 재치대(2)에 인가되어 처리 공간에 플라즈마가 발생할 때에는, 필요에 따라 제어부(60)에 의해 온·오프 스위치(53)가 온(on)으로 되어 상부 전극으로서의 샤워 헤드(16)에 소정의 직류 마이너스 전압이 인가된다.The variable direct current power supply 52 is electrically connected to the shower head 16 as the upper electrode via a low pass filter (LPF) 51. The variable DC power supply 52 is capable of turning on and off power feeding by the on / off switch 53. The current and voltage of the variable DC power supply 52 and the on / off of the on / off switch 53 are controlled by the control part 60 mentioned later. In addition, as described later, when a high frequency is applied to the mounting table 2 from the first RF power supply 10a and the second RF power supply 10b and a plasma is generated in the processing space, the control unit 60 as necessary. The on / off switch 53 is turned on, and a predetermined direct current negative voltage is applied to the shower head 16 as the upper electrode.

처리 챔버(1)의 측벽으로부터 샤워 헤드(16)의 높이 위치보다 상방으로 연장되도록 원통 형상의 접지 도체(1a)가 설치되어 있다. 이 원통 형상의 접지 도체(1a)는 그 상부에 천벽을 가지고 있다.A cylindrical ground conductor 1a is provided to extend upward from the side wall of the processing chamber 1 above the height position of the shower head 16. This cylindrical ground conductor 1a has a ceiling wall at its upper portion.

처리 챔버(1)의 저부에는 배기구(71)가 형성되어 있고, 이 배기구(71)에는 배기관(72)을 개재하여 배기 장치(73)가 접속되어 있다. 배기 장치(73)는 진공 펌프를 가지고 있어, 이 진공 펌프를 작동시킴으로써 처리 챔버(1) 내를 소정의 진공도까지 감압할 수 있도록 되어 있다. 한편, 처리 챔버(1)의 측벽에는 웨이퍼(W)의 반입출구(74)가 설치되어 있고, 이 반입출구(74)에는 당해 반입출구(74)를 개폐시키는 게이트 밸브(75)가 설치되어 있다.An exhaust port 71 is formed at the bottom of the processing chamber 1, and an exhaust device 73 is connected to the exhaust port 71 via an exhaust pipe 72. The exhaust device 73 has a vacuum pump so that the inside of the processing chamber 1 can be reduced to a predetermined degree of vacuum by operating the vacuum pump. On the other hand, the inlet / outlet 74 of the wafer W is provided in the side wall of the processing chamber 1, and the inlet / outlet 74 is provided with the gate valve 75 which opens and closes the inlet / outlet 74. .

도면 중 76, 77은 착탈 가능하게 된 퇴적물 실드(shield)이다. 퇴적물 실드(76)는 처리 챔버(1)의 내벽면을 따라 설치되어, 처리 챔버(1)에 에칭 부생물(퇴적물)이 부착되는 것을 방지하는 역할을 하고, 이 퇴적물 실드(76)의 반도체 웨이퍼(W)와 대략 동일한 높이 위치에는 그라운드에 DC적으로 접속된 도전성 부재(GND 블록)(79)가 설치되어 있어, 이에 의해 이상 방전이 방지된다.76 and 77 in the drawings are detachable deposit shields. The deposit shield 76 is provided along the inner wall surface of the processing chamber 1, and serves to prevent the etching by-products (sediments) from adhering to the processing chamber 1, and the semiconductor wafer of the deposit shield 76. The conductive member (GND block) 79 which is DC connected to the ground is provided in the substantially same height position as (W), and abnormal discharge is prevented by this.

상기 구성의 플라즈마 에칭 장치는 제어부(60)에 의해 그 동작이 통괄적으로 제어된다. 이 제어부(60)에는 CPU를 구비하고 플라즈마 에칭 장치의 각 부를 제어하는 프로세스 콘트롤러(61)와 유저 인터페이스(62)와 기억부(63)가 설치되어 있다.The operation of the plasma etching apparatus having the above configuration is controlled by the control unit 60 as a whole. The control unit 60 is provided with a CPU and is provided with a process controller 61 for controlling each unit of the plasma etching apparatus, a user interface 62, and a storage unit 63.

유저 인터페이스(62)는 공정 관리자가 플라즈마 에칭 장치를 관리하기 위하여 커멘드의 입력 조작을 행하는 키보드 또는 플라즈마 에칭 장치의 가동 상황을 가시화하여 표시하는 디스플레이 등으로 구성되어 있다. The user interface 62 is configured by a display for visualizing and displaying the operation status of a keyboard or a plasma etching apparatus for which a process manager performs a command input operation for managing the plasma etching apparatus.

기억부(63)에는 플라즈마 에칭 장치에서 실행되는 각종 처리를 프로세스 콘트롤러(61)의 제어로 실현시키기 위한 제어 프로그램(소프트웨어) 또는 처리 조건 데이터 등이 기억된 레시피가 저장되어 있다. 그리고, 필요에 따라 유저 인터페이스(62)로부터의 지시 등으로 임의의 레시피를 기억부(63)로부터 호출하여 프로세스 콘트롤러(61)에 실행시킴으로써, 프로세스 콘트롤러(61)의 제어 하에서 플라즈마 에칭 장치에서의 원하는 처리가 행해진다. 또한, 제어 프로그램 또는 처리 조건 데이터 등의 레시피는 컴퓨터에서 판독 가능한 컴퓨터 기억 매체(예를 들면, 하드 디스크, CD, 플렉서블 디스크, 반도체 메모리 등) 등에 저장된 상태의 것을 이용하거나, 혹은 다른 장치로부터, 예를 들면 전용 회선을 거쳐 수시 전송시켜 온라인에서 이용하는 것도 가능하다.The storage unit 63 stores recipes in which control programs (software), processing condition data, and the like are stored for realizing various processes executed in the plasma etching apparatus under the control of the process controller 61. Then, if necessary, an arbitrary recipe is called from the storage unit 63 by the instruction from the user interface 62 and executed by the process controller 61, thereby controlling the desired process in the plasma etching apparatus under the control of the process controller 61. The process is performed. In addition, recipes, such as a control program or process condition data, use the thing stored in the computer-readable medium (for example, a hard disk, CD, a flexible disk, a semiconductor memory, etc.) which can be read by a computer, or from another apparatus, for example, For example, it is also possible to transmit online via a dedicated line at any time.

이와 같이 구성된 플라즈마 에칭 장치에서, 반도체 웨이퍼(W)에 형성된 유기막 등을 플라즈마 에칭하는 순서에 대하여 설명한다. 우선, 게이트 밸브(75)가 열리고, 반도체 웨이퍼(W)가 도시하지 않은 반송 로봇 등에 의해 도시하지 않은 로드록실을 거쳐 반입출구(74)로부터 처리 챔버(1) 내로 반입되어 재치대(2) 상에 재치된다. 이 후, 반송 로봇을 처리 챔버(1) 밖으로 퇴피시키고, 게이트 밸브(75)를 닫는다. 그리고, 배기 장치(73)의 진공 펌프에 의해 배기구(71)를 거쳐 처리 챔버(1) 내가 배기된다.In the plasma etching apparatus configured as described above, a procedure of plasma etching the organic film or the like formed on the semiconductor wafer W will be described. First, the gate valve 75 is opened, and the semiconductor wafer W is loaded into the processing chamber 1 from the inlet / outlet 74 through a load lock chamber (not shown) by a transfer robot (not shown) or the like and placed on the mounting table 2. Is wit on. Thereafter, the transfer robot is evacuated out of the processing chamber 1 and the gate valve 75 is closed. And the inside of the processing chamber 1 is exhausted via the exhaust port 71 by the vacuum pump of the exhaust device 73.

처리 챔버(1) 내가 소정의 진공도가 된 후, 처리 챔버(1) 내에는 처리 가스 공급원(15)으로부터 소정의 처리 가스(에칭 가스)가 도입되고, 처리 챔버(1) 내가 소정의 압력, 예를 들면 6.7 Pa(50 mTorr)로 유지되고, 이 상태로 제 1 RF 전원(10a)으로부터 재치대(2)로 주파수가, 예를 들면 40 MHz인 고주파 전력이 공급된다. 또한, 제 2 RF 전원(10b)으로부터는 이온 주입을 위하여, 재치대(2)로 주파수가, 예를 들면 2.0 MHz인 고주파 전력(바이어스용)이 공급된다. 이 때, 직류 전원(12)으로부터 정전 척(6)의 전극(6a)에 소정의 직류 전압이 인가되어, 반도체 웨이퍼(W)는 쿨롱력에 의해 흡착된다.After the inside of the processing chamber 1 has a predetermined degree of vacuum, a predetermined processing gas (etching gas) is introduced into the processing chamber 1 from the processing gas supply source 15, and the inside of the processing chamber 1 has a predetermined pressure, for example. For example, it is maintained at 6.7 Pa (50 mTorr), and in this state, a high frequency power of 40 MHz is supplied from the first RF power supply 10a to the mounting table 2. In addition, from the second RF power supply 10b, high frequency power (for bias) having a frequency of, for example, 2.0 MHz is supplied to the mounting table 2 for ion implantation. At this time, a predetermined DC voltage is applied from the DC power supply 12 to the electrode 6a of the electrostatic chuck 6, and the semiconductor wafer W is attracted by the Coulomb force.

이 경우에, 상술한 바와 같이 하여 하부 전극인 재치대(2)에 고주파 전력이 인가됨으로써, 상부 전극인 샤워 헤드(16)와 하부 전극인 재치대(2) 사이에는 전계가 형성된다. 반도체 웨이퍼(W)가 존재하는 처리 공간에는 방전이 생기고, 이에 의해 형성된 처리 가스의 플라즈마에 의해 반도체 웨이퍼(W) 상에 형성된 실리콘을 함유하는 반사 방지막(Si-ARC) 등이 에칭 처리된다.In this case, high frequency power is applied to the mounting table 2 serving as the lower electrode as described above, so that an electric field is formed between the shower head 16 serving as the upper electrode and the mounting table serving as the lower electrode. Discharge occurs in the processing space in which the semiconductor wafer W exists, and the antireflection film (Si-ARC) containing silicon formed on the semiconductor wafer W is etched by the plasma of the processing gas formed thereby.

여기서, 상술한 바와 같이 플라즈마 처리 중에 샤워 헤드(16)에 직류 전압을 인가할 수 있기 때문에 다음과 같은 효과가 있다. 즉, 프로세스에 따라서는, 높은 전자 밀도이며 또한 낮은 이온 에너지인 플라즈마가 요구되는 경우가 있다. 이러한 경우에 직류 전압을 이용하면, 반도체 웨이퍼(W)에 주입되는 이온 에너지가 억제되면서 플라즈마의 전자 밀도가 증가됨으로써, 반도체 웨이퍼(W)의 에칭 대상이 되는 막의 에칭 레이트가 상승하고 또한 에칭 대상의 상부에 설치된 마스크가 되는 막에 대한 스퍼터링 레이트가 저하되어 선택성이 향상된다.Here, since the DC voltage can be applied to the shower head 16 during the plasma treatment as described above, the following effects are obtained. In other words, depending on the process, plasma having a high electron density and low ion energy may be required. In such a case, when the direct current voltage is used, the electron density of the plasma is increased while the ion energy injected into the semiconductor wafer W is suppressed, thereby increasing the etching rate of the film to be etched of the semiconductor wafer W and The sputtering rate for the film serving as the mask provided on the upper side is lowered, thereby improving the selectivity.

그리고, 상기한 에칭 처리가 종료되면, 고주파 전력의 공급, 직류 전압의 공급 및 처리 가스의 공급이 정지되고, 상기한 순서와는 반대의 순서로 반도체 웨이퍼(W)가 처리 챔버(1) 내로부터 반출된다.Then, when the above etching process is completed, supply of high frequency power, supply of DC voltage, and supply of processing gas are stopped, and the semiconductor wafer W is removed from the processing chamber 1 in the order opposite to that described above. It is taken out.

이어서, 도 1을 참조하여 본 실시예에 따른 플라즈마 에칭 방법에 대하여 설명한다. 도 1a 및 도 1b는 본 실시예에서의 피처리 기판으로서의 반도체 웨이퍼(W)의 주요부 구성을 확대하여 도시한 것이다. 도 1a에 도시한 바와 같이, 반도체 웨이퍼(W)에는 피에칭막으로서, 예를 들면 유기막(101)(두께가, 예를 들면 200 nm)이 형성되어 있고, 이 유기막(101)의 상층에는 실리콘을 함유하는 반사 방지막(Si-ARC)(102)(두께가, 예를 들면 40 nm)이 형성되어 있다. 이 실리콘을 함유하는 반사 방지막(Si-ARC)(102)은, 예를 들면 Si 함유율이 43% 정도인 유기막(도포막)으로 구성되어 있다. 그리고, 이 실리콘을 함유하는 반사 방지막(Si-ARC)(102) 상에 ArF 포토레지스트막(103)(두께가, 예를 들면 100 nm)이 형성되어 있다. ArF 포토레지스트막(103)에는 정밀 사진 전사(轉寫) 공정에 의해 패터닝되어 소정 형상의 개구(104)가 형성되어 있다.Next, a plasma etching method according to the present embodiment will be described with reference to FIG. 1. 1A and 1B show an enlarged view of the main part structure of the semiconductor wafer W as the substrate to be processed in this embodiment. As shown in FIG. 1A, an organic film 101 (for example, 200 nm in thickness) is formed on the semiconductor wafer W as an etching target film, and an upper layer of the organic film 101 is formed. An antireflection film (Si-ARC) 102 (thickness, for example, 40 nm) containing silicon is formed in the film. The anti-reflective film (Si-ARC) 102 containing this silicon is comprised from the organic film (coating film) whose Si content rate is about 43%, for example. An ArF photoresist film 103 (thickness, for example, 100 nm) is formed on the antireflection film (Si-ARC) 102 containing silicon. The ArF photoresist film 103 is patterned by a microphotographic transfer process to form openings 104 of a predetermined shape.

상기 구조의 반도체 웨이퍼(W)를 도 2에 도시한 장치의 처리 챔버(1) 내에 수용하여 재치대(2)에 재치하고, 도 1a에 도시한 상태로부터, ArF 포토레지스트막(103)을 마스크로 하여 실리콘을 함유하는 반사 방지막(Si-ARC)(102)을 에칭하여 도 1b의 상태로 한다. 또한, 실제로는 도 1b의 상태로부터 피에칭막으로서의 유기막(101)을 에칭한다. The semiconductor wafer W having the above structure is accommodated in the processing chamber 1 of the apparatus shown in FIG. 2, placed on the mounting table 2, and the ArF photoresist film 103 is masked from the state shown in FIG. 1A. As a result, the anti-reflective film (Si-ARC) 102 containing silicon is etched into the state shown in Fig. 1B. Further, in practice, the organic film 101 as an etching target film is etched from the state of FIG. 1B.

본 실시예에서는 상기 실리콘을 함유하는 반사 방지막(Si-ARC)(102)의 플라즈마 에칭을 행할 때에, 처리 가스로서 CF계 가스 및 CHF계 가스 중 적어도 어느 하나와 CF3I 가스와 산소 가스를 포함하는 혼합 가스를 사용하고, 또한 상부 전극으로서의 샤워 헤드(16)에 가변 직류 전원(52)으로부터 소정의 마이너스의 직류 전압을 인가한다.In this embodiment, when performing plasma etching of the silicon-containing anti-reflection film (Si-ARC) 102, at least one of CF gas and CHF gas, CF 3 I gas, and oxygen gas is included as the processing gas. A mixed negative gas is applied, and a predetermined negative DC voltage is applied from the variable DC power supply 52 to the shower head 16 as the upper electrode.

상기한 샤워 헤드(16)에 인가되는 마이너스의 직류 전압의 전압치는 -1000 V ~ -300 V의 범위로 하는 것이 바람직하고, -900 V ~ -600 V로 하는 것이 더욱 바람직하다.The voltage value of the negative DC voltage applied to the shower head 16 is preferably in the range of -1000 V to -300 V, more preferably -900 V to -600 V.

상기 처리 가스로서는, 예를 들면 CF4 가스와 CF3I 가스와 O2 가스의 혼합 가스를 적합하게 사용할 수 있다. 이 경우, CF4 가스 유량과 CF3I 가스 유량의 합계에 대한 CF3I 가스 유량의 비(CF3I 가스 유량 / (CF4 가스 유량 + CF3I 가스 유량))는 0.1 ~ 0.3의 범위로 하는 것이 바람직하다. 또한, O2 가스의 유량은 처리 가스 전체 유량의 1 ~ 3% 정도로 하는 것이 바람직하고, 대략 2% 정도로 하는 것이 더욱 바람직하다.As the processing gas, for example, a mixed gas of CF 4 gas, CF 3 I gas, and O 2 gas can be suitably used. In this case, CF 4 gas flow rate and CF 3 I ratio of the CF 3 I gas flow rate to the total gas flow rate (CF 3 I gas flow rate / (CF 4 gas flow rate + CF 3 I gas flow rate)) in the range of 0.1-0.3 It is preferable to set it as. In addition, the flow rate of the O 2 gas is preferably about 1% to 3% of the total flow rate of the processing gas, and more preferably about 2%.

또한, 상기한 플라즈마 에칭에서는 하부 전극으로서의 재치대(2)에 제 2 RF 전원(10b)으로부터 이온 주입용(바이어스용) 고주파 전력을 공급하는 것이 바람직하며, 이 이온 주입용(바이어스용) 고주파 전력의 전력치는 100 W ~ 300 W 정도로 하는 것이 바람직하다.In the above-mentioned plasma etching, it is preferable to supply a high frequency power for ion implantation (for bias) to the mounting table 2 serving as a lower electrode from the second RF power supply 10b. The power value of is preferably set to about 100 W to 300 W.

실험예 1로서, 도 2에 도시한 플라즈마 에칭 장치를 사용하여, 도 1에 도시한 구조의 반도체 웨이퍼에 상기한 실리콘을 함유하는 반사 방지막(Si-ARC)(102)의 플라즈마 에칭 처리 공정을 이하에 나타낸 바와 같은 레시피에 의해 실시했다.As Experimental Example 1, the plasma etching treatment step of the anti-reflection film (Si-ARC) 102 containing silicon described above in the semiconductor wafer having the structure shown in FIG. 1 using the plasma etching apparatus shown in FIG. It carried out by the recipe as shown to it.

또한, 이하에 나타낸 실험예 1의 처리 레시피는 제어부(60)의 기억부(63)로부터 독출되어 프로세스 콘트롤러(61)에 전달되고, 프로세스 콘트롤러(61)가 플라즈마 에칭 장치의 각 부를 제어 프로그램에 기초하여 제어함으로써, 독출된 처리 레시피대로의 플라즈마 에칭 처리 공정이 실행된다.In addition, the process recipe of Experimental example 1 shown below is read out from the memory | storage part 63 of the control part 60, and is transferred to the process controller 61, and the process controller 61 based each part of a plasma etching apparatus based on a control program. By performing the control, the plasma etching treatment step according to the read processing recipe is performed.

처리 가스 : CF4 / CF3I / O2 = 225 / 25 / 5 sccm Process gas: CF 4 / CF 3 I / O 2 = 225/25/5 sccm

압력 : 6.7 Pa(50 mTorr)Pressure: 6.7 Pa (50 mTorr)

고주파 전력(HF / LF) : 400 / 100 WHigh Frequency Power (HF / LF): 400/100 W

직류 전압 : -900 VDC voltage: -900 V

상기한 실험예 1에서의 ArF 포토레지스트의 에칭 레이트는 48.5 nm / min, 실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 레이트는 120.0 nm / min, 선택비(실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 레이트 / ArF 포토레지스트의 에칭 레이트)는 2.5가 되었다. 또한, SEM에 의해 관찰된 에칭 후의 ArF 포토레지스트 상태는 거칠기가 적고, CD(선폭)가 71.7 nm, LWR(Line Width Roughness)이 3.8 nm였다. 도 3a 및 도 3b에, 실험예 1의 SEM에 의해 확대된 ArF 포토레지스트의 단면 상태 및 상면 상태의 사진을 나타낸다. The etching rate of the ArF photoresist in Experimental Example 1 was 48.5 nm / min, the etching rate of the anti-reflective film (Si-ARC) containing silicon was 120.0 nm / min, and the selectivity (anti-reflective film containing silicon (Si -ARC) / etching rate of ArF photoresist) is 2.5. In addition, the ArF photoresist state after etching observed by SEM was low in roughness, 71.7 nm in CD (line width) and 3.8 nm in LWR (Line Width Roughness). 3A and 3B show photographs of the cross-sectional state and the top state of the ArF photoresist enlarged by the SEM of Experimental Example 1. FIG.

비교예로서, 이하의 조건에서 실리콘을 함유하는 반사 방지막(Si-ARC)(102)의 플라즈마 에칭 처리 공정을 실시했다. As a comparative example, the plasma etching treatment process of the anti-reflective film (Si-ARC) 102 containing silicon was implemented on condition of the following.

처리 가스 : CF4 / O2 = 250 / 5 sccm Process gas: CF 4 / O 2 = 250/5 sccm

압력 : 10 Pa(75 mTorr) Pressure: 10 Pa (75 mTorr)

고주파 전력(HF / LF) : 400 / 0 WHigh Frequency Power (HF / LF): 400/0 W

직류 전압 : 0 VDC voltage: 0 V

상기한 비교예에서의 ArF 포토레지스트의 에칭 레이트는 65.0 nm / min, 실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 레이트는 50.5 nm / min, 선택비(실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 레이트 / ArF 포토레지스트의 에칭 레이트)는 0.8이 되었다. 또한, SEM에 의해 관찰된 에칭 후의 ArF 포토레지스트 상태는 거칠기는 그렇게 많지 않았지만, CD(선폭)가 47.9 nm, LWR(Line Width Roughness)이 4.3 nm가 되어, ArF 포토레지스트가 많이 에칭되어 그 잔막량(殘膜量)이 적었다. 도 4a 및 도 4b에, 비교예의 SEM에 의해 확대된 ArF 포토레지스트의 단면 상태 및 상면 상태의 사진을 나타낸다. The etching rate of the ArF photoresist in the comparative example is 65.0 nm / min, the etching rate of the anti-reflective film (Si-ARC) containing silicon is 50.5 nm / min, the selectivity (anti-reflective film containing silicon (Si- ARC) etching rate / etching rate of ArF photoresist) was 0.8. In addition, the ArF photoresist state after etching observed by SEM was not so large, but the CD (line width) was 47.9 nm and the LWR (Line Width Roughness) was 4.3 nm, and the ArF photoresist was etched a lot so that the remaining film amount (殘膜 量) was less. 4A and 4B show photographs of the cross-sectional state and the top state of the ArF photoresist enlarged by the SEM of the comparative example.

상기와 같이, 실험예에서는 비교예의 경우에 비해, 실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 레이트가 높고, 선택비도 높고, ArF 포토레지스트의 LWR도 적었다. 또한, ArF 포토레지스트의 CD(선폭)도 컸다. As described above, in the experimental example, the etching rate of the anti-reflective film (Si-ARC) containing silicon was higher, the selectivity was higher, and the LWR of the ArF photoresist was smaller than in the comparative example. Moreover, the CD (line width) of ArF photoresist was also large.

또한, 상기의 실험예 1에서의 실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 전에, ArF 포토레지스트의 트리트먼트 공정을 추가한 실험예 2의 플라즈마 에칭을 행했다. 이 실험예 2에서의 트리트먼트 공정은, 예를 들면 수소 가스를 포함하는 트리트먼트 가스(H2 가스, H2 가스와 N2 가스, H2 가스와 Ar 가스 등)를 이용하여, 이 플라즈마를 ArF 포토레지스트에 작용시킴으로써, 이에 의해 ArF 포토레지스트 표면의 개질(改質)과 표면의 스무딩을 행하는 것이다. 이 실험예 2에서는 이하의 조건에서 트리트먼트 공정을 실시했다. In addition, the plasma etching of Experimental Example 2 to which the treatment process of ArF photoresist was added before the etching of the anti-reflective film (Si-ARC) containing silicon in Experimental Example 1 mentioned above was performed. In the treatment step of Experimental Example 2, the plasma is treated using, for example, a treatment gas containing hydrogen gas (H 2 gas, H 2 gas and N 2 gas, H 2 gas and Ar gas, etc.). By acting on the ArF photoresist, the surface of the ArF photoresist is modified and the surface is smoothed. In this Experimental Example 2, the treatment process was performed on condition of the following.

처리 가스 : H2 / N2 = 450 / 450 sccm Process gas: H 2 / N 2 = 450/450 sccm

압력 : 13.3 Pa(100 mTorr)Pressure: 13.3 Pa (100 mTorr)

고주파 전력(HF / LF) : 200 / 0 WHigh frequency power (HF / LF): 200/0 W

직류 전압 : 0 VDC voltage: 0 V

상기 트리트먼트 공정 후에, 실험예 1과 동일한 플라즈마 에칭을 행했다. 이 실험예 2에서 SEM에 의해 관찰된 에칭 후의 ArF 포토레지스트의 상태는 거칠기가 적고, CD(선폭)가 69.4 nm, LWR(Line Width Rougness)이 3.2 nm로, 실험예 1에서의 LWR치보다 더욱 개선되었다. After the treatment step, the same plasma etching as in Experimental Example 1 was performed. The ArF photoresist after etching observed by SEM in Experimental Example 2 had a low roughness, 69.4 nm of CD (line width) and 3.2 nm of LWR (Line Width Rougness), more than the LWR value of Experimental Example 1. Improvements were made.

상기의 각 실험예에서는 플라즈마 에칭 시에, 재치대(하부 전극)(2)에 제 2 RF 전원(10b)으로부터 이온 주입용(바이어스용) 고주파 전력을 인가하고 있다. 이는, 실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 레이트를 높이기 위해서이다. 도 5는 세로축을 에칭 레이트(nm / min), 가로축을 바이어스용 고주파 전력치(W)로 하고, 이하의 조건 (1)의 플라즈마 에칭 조건에서 바이어스용 고주파 전력만을 변화시켜, 각각의 고주파 전력치에서의 에칭 레이트를 조사한 결과를 나타낸 것이다. 도 5에 나타낸 바와 같이, 바이어스용 고주파 전력치가 높을수록 실리콘을 함유하는 반사 방지막(Si-ARC)의 에칭 레이트는 높아졌다. 이는, 샤워 헤드(상부 전극)(16)에 -600 V의 직류 전압을 인가했을 경우에 대해서도 완전히 동일했다. In each of the above experimental examples, high frequency power for ion implantation (for bias) is applied from the second RF power supply 10b to the mounting table (lower electrode) 2 during plasma etching. This is to increase the etching rate of the anti-reflective film (Si-ARC) containing silicon. Fig. 5 shows that the vertical axis is the etching rate (nm / min) and the horizontal axis is the bias high frequency power value (W), and only the high frequency power for bias is changed under the plasma etching conditions under the following condition (1). The result of having examined the etching rate in is shown. As shown in Fig. 5, the higher the high frequency power value for the bias, the higher the etching rate of the anti-reflective film (Si-ARC) containing silicon. The same was true for the case where a DC voltage of -600 V was applied to the shower head (upper electrode) 16.

조건 (1) Condition (1)

처리 가스 : CF4 / CF3I / O2 = 225 / 25 / 5 sccmProcess gas: CF 4 / CF 3 I / O 2 = 225/25/5 sccm

압력 : 10.0 Pa(75 mTorr) Pressure: 10.0 Pa (75 mTorr)

고주파 전력(HF / LF) : 400 / (변화) WHigh Frequency Power (HF / LF): 400 / (Change) W

직류 전압 : 0 VDC voltage: 0 V

한편, 상기와 같이 바이어스용 고주파 전력치를 높이면, ArF 포토레지스트의 거칠기가 발생한다. 또한, 세로축을 선택비, 가로축을 바이어스용 고주파 전력치(W)로 한 도 6에 나타낸 바와 같이, 선택비에 대해서는 샤워 헤드(상부 전극)(16)에 -600 V의 직류 전압을 인가함으로써, 직류 전압을 인가하지 않는 경우에 비해 높일 수 있다. On the other hand, when the high frequency power value for the bias is increased as described above, the roughness of the ArF photoresist occurs. As shown in Fig. 6 in which the vertical axis is the selection ratio and the horizontal axis is the bias high frequency power value W, by applying a DC voltage of -600 V to the shower head (upper electrode) 16 for the selection ratio, This can be increased as compared with the case where no DC voltage is applied.

상기와 같은 샤워 헤드(상부 전극)(16)에 인가되는 마이너스의 직류 전압과 선택비의 관계를 조사한 결과(LF = 200 W로 하고, 직류 전압 이외의 에칭 조건은 조건 (1)과 동일)를 세로축을 선택비, 가로축을 마이너스의 직류 전압치(절대치)(V)로 한 도 7의 그래프에 나타낸다. 도 7에 나타낸 바와 같이, 마이너스의 직류 전압치(절대치)가 높을수록 선택비는 향상된다. 그러나, 전압치가 -1000 V를 넘으면 ArF 포토레지스트의 위글링(Wiggling)이 발생한다. 이 때문에, 샤워 헤드(상부 전극)(16)에 인가되는 직류 전압은 -1000 V ~ -300 V의 범위로 하는 것이 바람직하고, -900 V ~ -600 V의 범위로 하는 것이 더욱 바람직하다.As a result of examining the relationship between the negative DC voltage applied to the shower head (upper electrode) 16 and the selection ratio as described above (LF = 200 W, the etching conditions other than the DC voltage were the same as in condition (1)). It is shown in the graph of FIG. 7 which made the vertical axis the selection ratio, and the horizontal axis the negative DC voltage value (absolute value) (V). As shown in Fig. 7, the higher the negative DC voltage value (absolute value), the better the selection ratio. However, when the voltage value exceeds -1000 V, Wigling of ArF photoresist occurs. For this reason, the DC voltage applied to the shower head (upper electrode) 16 is preferably in the range of -1000 V to -300 V, more preferably in the range of -900 V to -600 V.

또한, 재치대(하부 전극)(2)에 인가되는 바이어스용 고주파 전력은 필요한 에칭 레이트를 얻기 위하여 100 W 이상으로 하는 것이 바람직하고, 상기의 직류 전압치의 범위에서 충분한 선택비를 얻을 수 있고, 또한 ArF 포토레지스트의 거칠기를 억제하기 위해서는 300 W 이하로 하는 것이 바람직하다. 즉, 바이어스용 고주파 전력은 100 W ~ 300 W의 범위로 하는 것이 바람직하다.In addition, in order to obtain the required etching rate, the bias high frequency power applied to the mounting table (lower electrode) 2 is preferably set to 100 W or more, and a sufficient selectivity can be obtained within the above DC voltage value range. In order to suppress the roughness of an ArF photoresist, it is preferable to set it as 300 W or less. That is, the bias high frequency power is preferably in the range of 100 W to 300 W.

도 8은 세로축을 에칭 레이트, 가로축을 CF4 가스 유량과 CF3I 가스 유량의 합계에 대한 CF3I 가스 유량의 비(CF3I 가스 유량 / (CF4 가스 유량 + CF3I 가스 유량))로 하여, CF3I 가스의 유량비와 에칭 레이트의 관계를 조사한 결과를 나타내는 것이다. 또한, CF3I 가스 유량의 비 이외의 에칭 조건은 조건 (1)(단, LF = 200 W, 직류 전압 = -600 V)과 동일하다. 또한, 마찬가지로 도 9는 세로축을 선택비, 가로축을 CF4 가스 유량과 CF3I 가스 유량의 합계에 대한 CF3I 가스 유량의 비(CF3I 가스 유량 / (CF4 가스 유량 + CF3I 가스 유량))로 하여, CF3I의 유량비와 선택비의 관계를 조사한 결과를 나타내는 것이다. 이들 도 8, 9에 나타낸 바와 같이, CF3I 가스의 유량비가 높아지면 에칭 레이트도 선택비도 낮아진다. 따라서, CF3I 가스의 유량비는 0.3 이하로 하는 것이 바람직하다. Figure 8 is a horizontal axis to the vertical axis etching rate, CF 4 gas flow rate and the CF of the CF 3 I gas flow rate for a total of 3 I gas flow rate ratio (CF 3 I gas flow rate / (CF 4 gas flow rate + CF 3 I gas flow rate) ) Shows the result of examining the relationship between the flow rate ratio of the CF 3 I gas and the etching rate. Further, the etching conditions of the non-addition of CF 3 I gas flow rate is equal to the condition (1) (where, LF = 200 W, direct current voltage = -600 V). Also, as in Figure 9 to select the vertical axis ratio and the horizontal axis CF 4 gas flow rate and CF 3 I ratio of the CF 3 I gas flow rate to the total gas flow rate (CF 3 I gas flow rate / (CF 4 gas flow rate + CF 3 I Gas flow rate)), the relationship between the flow rate ratio and the selection ratio of CF 3 I is shown. 8 and 9, when the flow rate ratio of the CF 3 I gas increases, the etching rate and the selectivity also decrease. Therefore, the flow rate ratio of the CF 3 I gas is preferably 0.3 or less.

한편, 도 10a 내지 도 10c에 나타낸 바와 같이, CF3I의 유량비가 낮아지면 ArF 포토레지스트의 거칠기가 발생한다. 또한, 도 10a 내지 도 10c는 좌측으로부터 각각 차례대로 CF3I의 유량이 0 sccm, 19 sccm, 25 sccm 인 경우에서의 SEM에 의한 확대 사진을 나타내고 있다. 이 때문에 CF3I 가스의 유량비는 0.1 이상으로 하는 것이 바람직하다.On the other hand, as shown in FIGS. 10A to 10C, when the flow rate ratio of CF 3 I is lowered, roughness of the ArF photoresist occurs. 10A to 10C show enlarged photographs by SEM when the flow rates of CF 3 I are sequentially 0 sccm, 19 sccm, and 25 sccm, respectively, from the left side. Because of this flow rate ratio of CF 3 I gas is preferably not less than 0.1.

이상으로부터, CF4 가스 유량과 CF3I 가스 유량의 합계에 대한 CF3I 가스 유량의 비(CF3I 가스 유량 / (CF4 가스 유량 + CF3I 가스 유량))는 0.1 ~ 0.3(10% ~ 30%)의 범위로 하는 것이 바람직하다.From the above, CF 4 gas flow rate and the CF of the CF 3 I gas flow rate for a total of 3 I gas flow rate ratio (CF 3 I gas flow rate / (CF 4 gas flow rate + CF 3 I gas flow rate)) is 0.1 to 0.3 (10 % To 30%) is preferred.

도 11의 그래프는 세로축을 에칭 레이트, 가로축을 압력으로 하여, 압력과 에칭 레이트의 관계를 조사한 결과를 나타낸 것이다. 또한, 도 12는 세로축을 선택비, 가로축을 압력으로 하여, 압력과 선택비의 관계를 조사한 결과를 나타낸 것이다. 또한, 압력 이외의 에칭 조건은 조건 (1)(단, LF = 200 W, 직류 전압 = -600 V)과 동일하다. 이들 도 11, 12에 나타낸 바와 같이, 압력이 낮은 편이 에칭 레이트도 선택비도 높아진다. 이 때문에 압력은 4.0 Pa(30 mTorr) ~ 13.3 Pa(100 mTorr)의 범위로 하는 것이 바람직하고, 대략 6.7 Pa(50 mTorr) 정도로 하는 것이 더욱 바람직하다.The graph of FIG. 11 shows the result of having investigated the relationship between a pressure and an etching rate, with the vertical axis | shaft as the etching rate and the horizontal axis | shaft as the pressure. 12 shows the result of examining the relationship between the pressure and the selection ratio, with the vertical axis being the selection ratio and the horizontal axis being the pressure. In addition, etching conditions other than pressure are the same as condition (1) (LF = 200W, DC voltage = -600V). 11 and 12, the lower the pressure, the higher the etching rate and the selectivity. For this reason, the pressure is preferably in the range of 4.0 Pa (30 mTorr) to 13.3 Pa (100 mTorr), more preferably about 6.7 Pa (50 mTorr).

이상 설명한 바와 같이, 본 실시예에 따르면 ArF 포토레지스트의 데미지(거칠기)를 억제하면서 실리콘을 함유하는 반사 방지막(Si-ARC)을 높은 에칭 레이트로 플라즈마 에칭할 수 있다. 또한, 선택비가 높기 때문에, ArF 포토레지스트의 선폭(CD)을 좁게 하거나 거칠기(roughness)를 개선하는 것과 같은 ArF 포토레지스트의 장식(裝飾) 공정도 도입하는 것이 가능해진다. 또한, 본 발명은 상기의 실시예 및 실험예에 한정되지 않고 각종의 변형이 가능하다.As described above, according to this embodiment, the anti-reflective film (Si-ARC) containing silicon can be plasma-etched at a high etching rate while suppressing the damage (roughness) of the ArF photoresist. In addition, since the selectivity is high, it is possible to introduce a decoration process of the ArF photoresist such as narrowing the line width (CD) of the ArF photoresist or improving the roughness. In addition, this invention is not limited to the said Example and Experimental example, A various deformation | transformation is possible.

W : 반도체 웨이퍼,
10 : 유기막,
102 : 실리콘을 함유하는 반사 방지막(Si-ARC),
103 : ArF 포토레지스트막,
104 : 개구W: semiconductor wafer,
10: organic film,
102: anti-reflective film containing silicon (Si-ARC),
103: ArF photoresist film,
104: opening

Claims (8)

처리 챔버 내에 배치되고 기판이 재치되는 하부 전극과, 상기 처리 챔버 내에 상기 하부 전극과 대향하도록 배치된 상부 전극과, 상기 처리 챔버 내로 처리 가스를 공급하는 처리 가스 공급 기구와, 상기 하부 전극과 상기 상부 전극 사이에 고주파 전력을 인가하는 고주파 전원을 구비한 플라즈마 에칭 장치를 이용하고,
상기 기판에 형성된 ArF 포토레지스트를 마스크로 하여, 상기 ArF 포토레지스트의 하층에 위치하는 Si를 함유하는 반사 방지막을, 상기 처리 가스의 플라즈마에 의해 에칭하는 플라즈마 에칭 방법으로서,
상기 처리 가스로서, CF계 가스 및 CHF계 가스 중 적어도 어느 하나와 CF3I 가스와 산소 가스를 포함하는 혼합 가스를 사용하고, 상기 상부 전극에 직류 전압을 인가하는 것을 특징으로 하는 플라즈마 에칭 방법. A lower electrode disposed in the processing chamber and on which the substrate is placed, an upper electrode disposed to face the lower electrode in the processing chamber, a processing gas supply mechanism for supplying a processing gas into the processing chamber, the lower electrode and the upper portion Using a plasma etching apparatus having a high frequency power source for applying high frequency power between the electrodes,
A plasma etching method of etching an antireflection film containing Si positioned under an ArF photoresist with a plasma of the processing gas, using an ArF photoresist formed on the substrate as a mask,
And a direct current voltage is applied to the upper electrode using a mixed gas including at least one of a CF-based gas and a CHF-based gas, a CF 3 I gas, and an oxygen gas as the processing gas. 제 1 항에 있어서,
상기 상부 전극에 인가되는 직류 전압의 전압치가 -1000 V ~ -300 V의 범위인 것을 특징으로 하는 플라즈마 에칭 방법.The method of claim 1,
And a voltage value of the direct current voltage applied to the upper electrode is in the range of -1000 V to -300 V. 제 1 항 또는 제 2 항에 있어서,
상기 처리 가스는, CF4 가스와 CF3I 가스와 산소 가스의 혼합 가스이며,
CF4 가스 유량과 CF3I 가스 유량의 합계에 대한 CF3I 가스 유량의 비(CF3I 가스 유량 / (CF4 가스 유량 + CF3I 가스 유량))가 0.1 ~ 0.3의 범위인 것을 특징으로 하는 플라즈마 에칭 방법.The method according to claim 1 or 2,
The processing gas is a mixed gas of CF 4 gas, CF 3 I gas and oxygen gas,
Characterized in that the range of the CF 4 gas flow rate and CF 3 I gas ratio of the CF 3 I gas flow rate to the total flow rate (CF 3 I gas flow rate / (CF 4 gas flow rate + CF 3 I gas flow rate)) is 0.1 to 0.3 Plasma etching method. 제 1 항 또는 제 2 항에 있어서,
상기 하부 전극에 전력치가 100 W ~ 300 W인 바이어스용 고주파 전력을 인가하는 것을 특징으로 하는 플라즈마 에칭 방법. The method according to claim 1 or 2,
Plasma etching method characterized in that for applying a high-frequency power for bias having a power value of 100 W ~ 300 W to the lower electrode. 제 1 항 또는 제 2 항에 있어서,
상기 Si를 함유하는 반사 방지막의 에칭 전에, 상기 ArF 포토레지스트를 트리트먼트하는 트리트먼트 공정을 행하는 것을 특징으로 하는 플라즈마 에칭 방법. The method according to claim 1 or 2,
A treatment step of treating the ArF photoresist is performed before etching the antireflection film containing Si. 제 5 항에 있어서,
상기 트리트먼트 공정은, H2 가스, 또는 H2 가스와 N2 가스, 또는 H2 가스와 Ar 가스를 처리 가스로 하고, 상기 처리 가스를 플라즈마화하여 상기 ArF 포토레지스트에 작용시키는 플라즈마 처리인 것을 특징으로 하는 플라즈마 에칭 방법. The method of claim 5, wherein
The treatment step is a plasma treatment in which H 2 gas, or H 2 gas and N 2 gas, or H 2 gas and Ar gas are used as a processing gas, and the processing gas is converted into plasma to act on the ArF photoresist. A plasma etching method. 처리 챔버 내에 배치되고 기판이 재치되는 하부 전극과, 상기 처리 챔버 내에 상기 하부 전극과 대향하도록 배치된 상부 전극과, 상기 처리 챔버 내로 처리 가스를 공급하는 처리 가스 공급 기구와, 상기 하부 전극과 상기 상부 전극 사이에 고주파 전력을 인가하는 고주파 전원을 구비한 플라즈마 에칭 장치로서,
상기 기판에 형성된 ArF 포토레지스트를 마스크로 하여, 상기 ArF 포토레지스트의 하층에 위치하는 Si를 함유하는 반사 방지막을, 상기 처리 가스의 플라즈마에 의해 에칭할 때에,
상기 처리 가스 공급 기구로부터 처리 가스로서, CF계 가스 및 CHF계 가스 중 적어도 어느 하나와 CF3I 가스와 산소 가스를 포함하는 혼합 가스를 공급하고, 상기 상부 전극에 직류 전원으로부터 직류 전압을 인가하도록 제어하는 제어부를 가지는 것을 특징으로 하는 플라즈마 에칭 장치. A lower electrode disposed in the processing chamber and on which the substrate is placed, an upper electrode disposed to face the lower electrode in the processing chamber, a processing gas supply mechanism for supplying a processing gas into the processing chamber, the lower electrode and the upper portion A plasma etching apparatus having a high frequency power source for applying high frequency power between electrodes,
When etching the anti-reflection film containing Si located under the ArF photoresist by using the plasma of the processing gas, using the ArF photoresist formed on the substrate as a mask,
Supplying a mixed gas containing at least one of CF-based gas and CHF-based gas, CF 3 I gas and oxygen gas as the processing gas from the processing gas supply mechanism, and applying a direct-current voltage from the direct-current power supply to the upper electrode; Plasma etching apparatus characterized by having a control part to control. 컴퓨터 상에서 동작하는 제어 프로그램이 기억된 컴퓨터 기억 매체로서,
상기 제어 프로그램은 실행 시에 청구항 1 또는 2에 기재된 플라즈마 에칭 방법이 행해지도록 플라즈마 에칭 장치를 제어하는 것을 특징으로 하는 컴퓨터 기억 매체.A computer storage medium storing a control program running on a computer,
The control program controls the plasma etching apparatus so that the plasma etching method according to claim 1 or 2 is executed at the time of execution.
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KR20180043784A (en) * 2015-08-27 2018-04-30 도쿄엘렉트론가부시키가이샤 Plasma processing method

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