KR20100076692A - Nand flash memory device and method of writing data in nand flash memory device - Google Patents

Nand flash memory device and method of writing data in nand flash memory device Download PDF

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Publication number
KR20100076692A
KR20100076692A KR1020080134820A KR20080134820A KR20100076692A KR 20100076692 A KR20100076692 A KR 20100076692A KR 1020080134820 A KR1020080134820 A KR 1020080134820A KR 20080134820 A KR20080134820 A KR 20080134820A KR 20100076692 A KR20100076692 A KR 20100076692A
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KR
South Korea
Prior art keywords
block
spare
main
blocks
flash memory
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Application number
KR1020080134820A
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Korean (ko)
Inventor
최은석
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080134820A priority Critical patent/KR20100076692A/en
Publication of KR20100076692A publication Critical patent/KR20100076692A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: A NAND flash memory device and a writing method thereof are provided to enhance the write speed property by copying back the data written on a spare block with a main block. CONSTITUTION: A plurality of pages is arranged in main blocks. The page is a basic unit of the write operation. A spare block is copied back with the main block in a standby state(509). A write data is programmed during inputting the write command(502). Spare blocks have the same cell array size as main blocks. Spare blocks share the same page buffer.

Description

NAND flash memory device and method of writing data in NAND flash memory device

The present invention relates to a nonvolatile memory device, and more particularly, to a NAND flash memory device and a writing method with improved write speed characteristics.

Flash memory devices are widely used in many electronic applications in which nonvolatile memory devices are employed. Flash memory devices use one transistor cell as a unit cell, which provides high memory density, high reliability, and low power consumption. Flash memory devices are used in portable computers, personal digital assistants (PDAs), digital cameras and portable telephones. In addition, program code, system data such as basic input / output systems (BIOS), and other firmware may also be stored in flash memory devices. Among flash memory devices, especially NAND flash memory devices have been recently used in a wider range in that high memory density can be obtained at relatively low cost.

1 is a flowchart illustrating a program method of a general NAND flash memory device. Referring to FIG. 1, first, it is checked whether a write command is input while waiting in a standby state (step 101). If a write command is input (step 102), a block erase operation is performed (step 103). All data in the block including the address to be written by the block erase operation are erased. After the block erase is performed, a write operation is performed (step 104). After performing the write operation, it enters the standby state (step 105). Then, it is checked whether a new command is input while maintaining the standby state (step 106). When a new command is input, a command operation is performed (step 107). If no new command is entered, it stays in standby state.

As described above, the write operation of the NAND flash memory device is performed after block erase is performed. Therefore, the speed of the write operation depends on the block erase speed and the write operation speed. In general, the time tBER for block erasing is several msec, which is relatively longer than the time tPROG for performing a write operation. Therefore, the time until the entire write operation is completed by block erasing becomes longer, which worsens the speed characteristic even when the amount of write data is small. In addition, when a long erase time is required such as a NLC flash memory device having a multi-level cell (MLC) structure or a NAND flash memory device having a charge trap structure, such an unreasonable problem becomes even more serious.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a NAND flash memory device capable of improving write speed characteristics.

Another technical problem to be solved by the present invention is to provide a method of writing such a NAND flash memory device.

According to an embodiment, a NAND flash memory device includes a main block in which a plurality of pages, which are basic units of a write operation, are arranged, and a spare copying data back from the standby state to the main block after the write data is programmed when a write command is input. Contains blocks.

In one example, the spare blocks have the same cell array size as the main blocks and are arranged to share the same page buffer.

In one example, the main blocks and spare blocks are placed in the same plane.

In one example, the main blocks and the spare blocks are arranged in different planes.

According to an embodiment, a write operation of a NAND flash memory device may include inputting a write command to a main block, programming write data to a spare block corresponding to the main block according to the write command, and in a standby state. Copying write data in the spare block into the main block.

In one example, the method may further include checking whether the main block is in an erased state before copying, and performing an erase operation on the main block if the check result is not erased.

In this case, the erase operation on the main floc is performed in the standby state.

In an example, the method may further include performing an erase operation in the standby state with respect to the spare block which has performed copyback with respect to the main block.

According to the present invention, the write operation is performed on the spare block without the erase operation on the main block, and the write speed characteristic can be improved by copying back the data written to the spare block to the main block erased in the standby state. This provides the advantage of adopting a highly integrated MLC structure, which has a relatively low erase rate but an easy-to-write MLC structure, and a high-speed and reliable charge trap structure, especially in an application where a small write operation is performed.

2 is a block diagram schematically illustrating a structure of a NAND flash memory device. Referring to FIG. 2, a NAND flash memory device includes a plurality of blocks (blocks 0, 1,..., 1023). Each block includes a plurality of pages (pages 0, 1, ..., page 63). Each page includes a plurality of cell arrays and a spare array. For a 1024 Mbytes device, 1024 blocks are placed, 64 pages are placed within each block, and 4 sectors and 1 spare array are placed on each page. In some cases, the number of blocks may be increased, in which case the number of pages is further reduced. The write operation of the NAND flash memory device having such a structure is performed in units of pages, and the erase operation is performed in units of blocks. In order to perform a write operation on the cell array corresponding to the predetermined address, the block including the cell array must be erased.

3 is a block diagram illustrating a NAND flash memory device according to an embodiment of the present invention. Referring to FIG. 3, a NAND flash memory device according to an embodiment may include a memory area 310, a page buffer 320 for performing control operations of cell transistors in the memory area 310, and a memory area 310. A decoder 330 for addressing in the " The main block area 311 and the spare block area 312 are included in the memory area 310. A plurality of main blocks BLK0, BLK1, BLK2,... Are arranged in the main block area 311. The plurality of main blocks BLK0, BLK1, BLK2,... Are arranged to be distributed in a plurality of planes (plane 0, plane 1). The number of planes may vary depending on the capacity of the device. Within each main block, as shown in FIG. 2, a plurality of pages are included, and each page includes a plurality of cell arrays. Each cell array consists of a plurality of cell transistors, which may be a floating gate structure or a structure having a charge trap layer.

A plurality of spare blocks SBLK0, SBLK1, SBLK2,... Are arranged in the spare block area 312. Each spare block corresponds to each of the plurality of main blocks BLK0, BLK1, BLK2,... For example, the spare block SBLK-0 corresponds to the main block BLK0, and the spare block SBLK-1 corresponds to the main block BLK1. Corresponding main blocks and spare blocks are arranged in the same plane. For example, the corresponding main block BLK0 and the spare block SBLK-0 are disposed in the first plane (plane 0), and the corresponding main block BLK7 and the spare block SBLK-7 are two It is disposed in the first plane (plane 1). In addition, the corresponding main block and the spare block share the same page buffer 320, so that the write operation on the main block and the write operation on the spare block are performed through the same circuit operation.

4 is a block diagram illustrating a NAND flash memory device according to another embodiment of the present invention. Referring to FIG. 4, a NAND flash memory device according to another embodiment may include a memory area 410, a page buffer 420 performing control operations of cell transistors in the memory area 410, and a memory area 410. Decoder 430 for addressing in < RTI ID = 0.0 > The main block area 411 and the spare block area 412 are included in the memory area 410. A plurality of main blocks BLK0, BLK1, BLK2,... Are arranged in the main block area 411. The plurality of main blocks BLK0, BLK1, BLK2,... Are arranged to be distributed in a plurality of planes (plane 0, plane 1). The number of planes may vary depending on the capacity of the device. Within each main block, as shown in FIG. 2, a plurality of pages are included.

A plurality of spare blocks SBLK0, SBLK1, SBLK2,... Are arranged in the spare block area 412. Each spare block corresponds to each of the plurality of main blocks BLK0, BLK1, BLK2,... For example, the spare block SBLK-0 corresponds to the main block BLK0, and the spare block SBLK-1 corresponds to the main block BLK1. Corresponding main blocks and spare blocks are arranged in different planes. For example, the corresponding main block BLK0 and the spare block SBLK-0 are disposed in the first plane (plane 0) and the second plane (plane 1), respectively, and also correspond to the corresponding main block BLK7. The spare block SBLK-7 is also disposed in the second plane (plane 1) and the first plane (plane 0), respectively. In addition, the corresponding main block and the spare block share the same page buffer 420 so that the write operation on the main block and the write operation on the spare block are performed through the same circuit operation.

5 is a flowchart illustrating a method of writing a NAND flash memory device according to an embodiment of the present invention. Referring to FIG. 5, first, it is checked whether a write command is input while waiting in a waiting state (step 501). If a write command is input (step 502), a write operation is performed. In this embodiment, a case is described in which data is programmed in a cell of a specific address in the block BLK2. When a write command is input, the write operation is performed to the spare block SBLK-2 corresponding to the block BLK2 without performing an erase operation on the block including the cell of the corresponding address, that is, the block BLK2 ( Step 503). The spare block SBLK-2 is already erased with all data, and the erase of the spare block SBLK-2 is performed in the standby state. Therefore, the write operation according to the write command takes only the time required to perform the write operation on the spare block SBLK-2, and does not take the time required for any erase operation.

After performing a write operation on the spare block SBLK-2, the process enters a standby state (step 504). Then, it is checked whether a new command is input while maintaining the standby state (step 505). When a new command is input, a command operation is performed (step 506). If a new command is not input, it maintains the standby state again and checks whether the main block BLK2 to which the write operation should be performed is erased according to the write command (step 507). As a result of the check, if the main block BLK2 has already been erased, data copy back is performed from the spare block SBLK-2 to the main block BLK2 (step 509). That is, as indicated by arrows in FIGS. 3 and 4, the data programmed in the spare block SBLK-2 by the write command is copied into the main block BLK2. Next, the spare block SBLK-2 is erased to prepare for a write operation according to the next write command. The erase operation on the spare block SBLK-2 is also performed in the standby state. If the main block BLK2 is not erased as a result of the checking of the step 507, an erase operation is performed on the main block BLK2 (step 508). Even in this case, the erase operation on the main block BLK2 is performed in the standby state. After the main block BLK2 is executed, data copying of step 509 is performed.

According to the write method as described above, both the erase operation on the main block BLK2 and the erase operation on the spare block SBLK-2 are performed in the standby state. The data copyback from the spare block SBLK-2 to the main block BLK2 is also performed in the standby state. In one example, by utilizing appropriate software, the erase operation on the main block BLK2, the erase operation on the spare block SBLK-2, and the data copyback operation may be performed at the optimum timing even during the standby state. have. Therefore, since the time required for the write operation on the spare block SBLK-2 is only required for the write operation by the write command, the time for the write operation can be reduced. Also, in the present embodiment, the case in which the spare blocks are disposed in a separate area from the main block is taken as an example, but it is natural that some blocks in the main block may also be used as spare blocks.

1 is a flowchart illustrating a program method of a general NAND flash memory device.

2 is a block diagram schematically illustrating a structure of a NAND flash memory device.

3 is a block diagram illustrating a NAND flash memory device according to an embodiment of the present invention.

4 is a block diagram illustrating a NAND flash memory device according to another embodiment of the present invention.

5 is a flowchart illustrating a method of writing a NAND flash memory device according to an embodiment of the present invention.

Claims (8)

Main blocks having a plurality of pages arranged as basic units of a write operation; And And a spare block for copying the data to the main block in a standby state after writing data is programmed when a write command is input. The method of claim 1, The spare blocks have the same cell array size as the main blocks and are arranged to share the same page buffer. The method of claim 1, And the main blocks and the spare blocks are disposed in the same plane. The method of claim 1, And the main blocks and the spare blocks are disposed in different planes. Inputting a write command for the main block; Programming write data in a spare block corresponding to the main block according to the write command: And copying write data in the spare block into the main block in a standby state. The method of claim 5, Checking whether the main block is in an erased state before the copying step; And And performing an erase operation on the main block if the erase result is not erased. The method of claim 6, And an erase operation on the main block is performed in a standby state. The method of claim 5, And performing an erase operation in a standby state on a spare block in which copyback is performed on the main block.
KR1020080134820A 2008-12-26 2008-12-26 Nand flash memory device and method of writing data in nand flash memory device KR20100076692A (en)

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KR1020080134820A KR20100076692A (en) 2008-12-26 2008-12-26 Nand flash memory device and method of writing data in nand flash memory device

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