KR20100076556A - Method for manufacturing magnetic tunnel junction device - Google Patents

Method for manufacturing magnetic tunnel junction device Download PDF

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KR20100076556A
KR20100076556A KR1020080134653A KR20080134653A KR20100076556A KR 20100076556 A KR20100076556 A KR 20100076556A KR 1020080134653 A KR1020080134653 A KR 1020080134653A KR 20080134653 A KR20080134653 A KR 20080134653A KR 20100076556 A KR20100076556 A KR 20100076556A
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film
layer
pattern
forming
magnetic tunnel
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KR1020080134653A
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Korean (ko)
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김유송
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Abstract

PURPOSE: A manufacturing method of a magnetic tunnel bonding device is provided to prevent the short between a free layer and a pinned layer by forming an insulative polymer layer on both sidewalls of a first pattern comprising a free layer. CONSTITUTION: A stacked layer is formed in which a pinning layer(22), a pinned layer(23), a tunnel insulating layer(24) and a free layer(25) are successively stacked. A hard mask pattern(26) is formed on the stacked layer. The stacked layer is etched to the free layer using the hard mask pattern as an etching barrier to form a first pattern(27). A insulative polymer layer(28) is formed on both sidewalls of the first pattern.

Description

자기터널접합 장치 제조방법{METHOD FOR MANUFACTURING MAGNETIC TUNNEL JUNCTION DEVICE}Magnetic tunnel junction device manufacturing method {METHOD FOR MANUFACTURING MAGNETIC TUNNEL JUNCTION DEVICE}

본 발명은 반도체 장치의 제조 기술에 관한 것으로, 특히 자기터널접합(Magnetic Tunnel Junction, MTJ) 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of manufacturing a magnetic tunnel junction (MTJ) device.

최근 반도체 메모리 장치가 고집적화됨에 따라 셀 면적 축소에 유리하고, 고속동작 및 비휘발성을 갖는 차세대 반도체 메모리 장치로서 자기저항 메모리 장치(Magnetic Random Access Memory, MRAM)가 주목받고 있다. 자기저항 메모리 장치는 스윗칭 동작을 수행하는 트랜지스터와 정보를 저장하는 자기터널접합 장치(Magnetic Tunnel Junction, MTJ)로 구성되며, 자기터널접합 장치는 두개의 강자성막 사이에 터널절연막이 개재된 구조를 갖는다. 자기터널접합 장치는 두개의 강자성막의 자화방향(magnetization direction)에 따라 자기저항비(magnetoresistance, MR) 달라지는데, 이러한 자기저항비 변화에 따른 전압변화 또는 전류량의 변화를 이용하여 자기터널접합 장치에 저장된 정보가 논리 "1" 또는 논리 "0"인지를 판별할 수 있다.Recently, due to the high integration of semiconductor memory devices, magneto-resistive memory devices (MRAMs) are attracting attention as next-generation semiconductor memory devices that are advantageous in reducing cell area and have high-speed operation and non-volatility. The magnetoresistive memory device is composed of a transistor for switching operation and a magnetic tunnel junction device (MTJ) for storing information. The magnetic tunnel junction device has a structure in which a tunnel insulation layer is interposed between two ferromagnetic layers. Have The magnetic tunnel junction device varies in magnetoresistance (MR) according to the magnetization direction of the two ferromagnetic films. The magnetic tunnel junction device is stored in the magnetic tunnel junction device by using a voltage change or a current change according to the magnetoresistance change. It can be determined whether the information is logical "1" or logical "0".

도 1은 종래기술에 따른 자기터널접합 장치를 도시한 단면도이다. 1 is a cross-sectional view showing a magnetic tunnel junction device according to the prior art.

도 1을 참조하여 종래기술에 따른 자기터널접합 장치의 제조방법을 살펴보면, 소정의 구조물이 형성된 기판(11) 상에 피닝막(pinning layer, 12), 핀드막(pinned layer, 13), 터널절연막(tunnel insulator, 14) 및 자유막(free layer, 15)을 순차적으로 증착한다. 이때, 피닝막(12)은 반강자성(antiferromagnetic)을 갖는 금속화합물로 형성하고, 핀드막(13) 및 자유막(15)은 강자성(ferromagnetic)을 갖는 금속화합물로 형성한다.Looking at the manufacturing method of the magnetic tunnel junction device according to the prior art with reference to Figure 1, a pinning layer (12), pinned layer (13), a tunnel insulating film on a substrate 11 having a predetermined structure (tunnel insulator 14) and free layer 15 are sequentially deposited. At this time, the pinning film 12 is formed of a metal compound having antiferromagnetic, and the pinned film 13 and the free layer 15 is formed of a metal compound having ferromagnetic.

다음으로, 자유막(15) 상에 하드마스크패턴(미도시)을 형성한 후, 하드마스크패턴을 식각장벽(etch barrier)으로 자유막(15), 터널절연막(14), 핀드막(13) 및 피닝막(12)을 차례로 식각하여 자기터널접합 장치를 형성한다. 이때, 자기터널접합 장치가 정상적으로 동작하기 위해서는 터널절연막(14)에 의하여 자유막(15)과 핀드막(13)이 전기적으로 분리되어야 한다.Next, after the hard mask pattern (not shown) is formed on the free layer 15, the free layer 15, the tunnel insulating layer 14, and the pinned layer 13 are formed using the hard mask pattern as an etch barrier. And the pinning film 12 are sequentially etched to form a magnetic tunnel junction device. At this time, in order for the magnetic tunnel junction device to operate normally, the free layer 15 and the pinned layer 13 must be electrically separated by the tunnel insulating layer 14.

하지만, 종래기술은 자기터널접합 장치를 형성하기 위한 식각공정시 발생한 도전성부산물(P)로 인하여 자기터널접합 장치의 전기적인 특성이 열화되는 문제점이 있다. 이는 피닝막(12), 핀드막(13) 및 자유막(15)을 구성하는 금속화합물의 끓는점(boilimg point)이 높기 때문에 이들을 식각과정에서 발생된 도전성부산물(P)이 잘 휘발되지 않고, 자기터널접합 장치의 측벽에 재증착(redeposition)되기 때문이다. 특히, 도면부호 'A'와 같이 핀드막(13)과 자유막(15)을 쇼트(short)시키는 도전성부산물(P)로 인하여 자기터널접합 장치의 전기적 특성이 열화되고, 이는 자 기터널접합 장치를 이용하는 반도체 장치 예컨대, 자기저항 메모리 장치의 페일(fail)을 유발하여 반도체 장치의 신뢰성 및 제조 수율(yield)을 저하시키는 문제를 초래하게 된다. However, the related art has a problem in that electrical characteristics of the magnetic tunnel junction device are deteriorated due to the conductive by-product P generated during the etching process for forming the magnetic tunnel junction device. Since the boiling point of the metal compounds constituting the pinning film 12, the pinned film 13, and the free film 15 is high, the conductive by-products P generated during the etching process are hardly volatilized, This is because they are redeposited on the sidewall of the tunnel junction device. In particular, the electrical by-product P deteriorates the electrical characteristics of the magnetic tunnel junction device due to the conductive by-product P shorting the pinned layer 13 and the free layer 15 as shown by reference numeral 'A'. Causes a failure of a semiconductor device, for example, a magnetoresistive memory device, resulting in a problem of lowering the reliability and manufacturing yield of the semiconductor device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 자기터널접합 장치를 형성하기 위한 식각공정시 발생하는 도전성부산물로 인하여 자기터널접합 장치의 특성이 열화되는 것을 방지할 수 있는 자기터널접합 장치 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the problems of the prior art, a magnetic tunnel that can prevent the deterioration of the characteristics of the magnetic tunnel junction device due to the conductive by-products generated during the etching process for forming the magnetic tunnel junction device It is an object of the present invention to provide a method for manufacturing a bonding device.

상기 목적을 달성하기 위한 일 측면에 따른 본 발명의 자기터널접합 장치 제조방법은, 피닝막, 핀드막, 터널절연막 및 자유막이 순차적으로 적층된 적층막을 형성하는 단계; 상기 적층막 상에 하드마스크패턴을 형성하는 단계; 상기 적층막을 상기 하드마스크패턴을 식각장벽으로 상기 자유막까지 식각하여 제1패턴을 형성하는 단계; 상기 제1패턴 양측벽에 절연성 폴리머막을 형성하는 단계 및 상기 하드마스크패턴 및 상기 절연성 폴리머막을 식각장벽으로 나머지 상기 적층막을 식각하여 제2패턴을 형성하는 단계를 포함한다. According to one aspect of the present invention, there is provided a method of manufacturing a magnetic tunnel junction apparatus, including: forming a laminated film in which a pinning film, a pinned film, a tunnel insulating film, and a free film are sequentially stacked; Forming a hard mask pattern on the laminated film; Forming a first pattern by etching the stacked layer to the free layer using the hard mask pattern as an etch barrier; Forming an insulating polymer layer on both sidewalls of the first pattern, and etching the remaining layered layer using the hard mask pattern and the insulating polymer layer as an etch barrier to form a second pattern.

또한, 상기 제1패턴을 형성하는 단계는, 상기 적층막을 상기 하드마스크패턴을 식각장벽으로 상기 터널절연막까지 식각하여 형성할 수도 있다. In the forming of the first pattern, the laminate layer may be formed by etching the hard mask pattern to the tunnel insulating layer using an etch barrier.

상기 제1패턴을 형성하는 단계. 상기 절연성 폴리머막을 형성하는 단계 및 상기 제2패턴을 형성하는 단계는 동일 챔버에서 인시튜로 진행할 수 있다. Forming the first pattern. The forming of the insulating polymer film and the forming of the second pattern may be performed in situ in the same chamber.

상기 절연성 폴리머막은, 실리콘산화물(SixOy, x,y는 0을 제외한 자연수) 또는 실리콘질화물(SixNy, x,y는 0을 제외한 자연수)을 포함할 수 있다. 구체적으로, 상기 절연성 폴리머막을 형성하는 단계는, 챔버에 SiCl4가스와 산소가스(O2)가 혼합된 혼합가스 또는 SiCl4가스와 질소가스(N2)가 혼합된 혼합가스의 플라즈마를 사용하여 형성할 수 있다. The insulating polymer film may include silicon oxide (Si x O y , where x and y are natural numbers except 0) or silicon nitride (Si x N y and x and y are natural numbers except 0). Specifically, the forming of the insulating polymer film may be performed using a plasma of a mixed gas in which SiCl 4 gas and oxygen gas (O 2 ) are mixed in the chamber or a mixed gas in which SiCl 4 gas and nitrogen gas (N 2 ) are mixed. Can be formed.

상기 하드마스크패턴은 산화막, 질화막 및 산화질화막으로 이루어진 그룹으로부터 선택된 어느 하나 또는 이들이 적층된 적층막으로 형성하거나, 또는 금속성막으로 형성할 수 있다.The hard mask pattern may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a laminated film in which they are stacked, or a metal film.

상술한 과제 해결 수단을 바탕으로 하는 본 발명은, 자유막을 포함하는 제1패턴의 양측벽에 절연성 폴리머막을 형성함으로써, 제2패턴을 형성하는 과정에서 생성된 도전성부산물에 의하여 자유막과 핀드막 사이에 쇼트가 발생하는 것을 방지할 수 있는 효과가 있다.The present invention based on the above-described problem solving means, by forming an insulating polymer film on both side walls of the first pattern including the free film, between the free film and the pinned film by the conductive by-product generated in the process of forming the second pattern There is an effect that can prevent the short to occur.

이로써, 도전성부산물에 의해 자기터널접합 장치의 전기적인 특성이 열화되는 것을 방지할 수 있으며, 자기터널접합 장치를 구비하는 반도체 장치의 신뢰성 및 제조 수율을 향상시킬 수 있는 효과가 있다. As a result, the electrical by-products of the magnetic tunnel junction apparatus can be prevented from being deteriorated by the conductive by-product, and the reliability and manufacturing yield of the semiconductor device including the magnetic tunnel junction apparatus can be improved.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

후술한 본 발명은 자기터널접합 장치를 형성하는 과정에서 생성된 도전성부산물에 의하여 자기터널장치의 전기적인 특성 열화 특히, 도전성부산물에 의하여 자유막과 핀드막 사이가 쇼트되는 것을 방지할 수 있는 자기터널접합 장치 제조방법을 제공한다.The present invention described below is a magnetic tunnel capable of preventing the short circuit between the free film and the pinned film due to the deterioration of electrical characteristics of the magnetic tunnel device by the conductive by-product generated in the process of forming the magnetic tunnel junction device. Provided is a method for manufacturing a bonding device.

도 2a 내지 도 2d는 본 발명의 일실시예에 따른 자기터널접합 장치 제조방법을 도시한 공정단면도이다. 2A to 2D are cross-sectional views illustrating a method of manufacturing a magnetic tunnel junction apparatus according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 소정의 구조물이 형성된 기판(21) 상에 피닝막(pinning layer, 22), 핀드막(pinned layer, 23), 터널절연막(tunnel insulator, 24) 및 자유막(free layer, 25)이 순차적으로 적층된 적층막을 형성한다. 이때, 기판(11)은 스윗칭 동작을 수행하는 트랜지스터, 피닝막(22)과 트랜지스터의 접합영역 사이를 연결하는 하부전극 등을 포함할 수 있다. As shown in FIG. 2A, a pinning layer 22, a pinned layer 23, a tunnel insulator 24, and a free layer are formed on a substrate 21 on which a predetermined structure is formed. A layer 25 is formed by sequentially stacking layers 25). In this case, the substrate 11 may include a transistor performing a switching operation, a lower electrode connecting the pinning layer 22 and a junction region of the transistor, and the like.

피닝막(22)은 핀드막(23)의 자화방향을 고정시키는 역할을 수행하는 것으로, 반강자성(antiferromagnetic)을 갖는 물질을 사용하여 형성할 수 있다. 예를 들어, 반강자성을 갖는 물질로는 IrMn, PtMn, MnO, MnS, MnTe, MnF2, FeF2, FeCl2, FeO, CoCl2, CoO, NiCl2 또는 NiO 등을 사용할 수 있다. 피닝막(22)은 상술한 반강자성 물질들 중 어느 하나로 이루어진 단일막으로 형성하거나, 또는 이들이 적층된 적층 막으로 형성할 수 있다. The pinning layer 22 serves to fix the magnetization direction of the pinned layer 23 and may be formed using a material having antiferromagnetic. For example, as the material having antiferromagnetic properties, IrMn, PtMn, MnO, MnS, MnTe, MnF 2 , FeF 2 , FeCl 2 , FeO, CoCl 2 , CoO, NiCl 2, or NiO may be used. The pinning film 22 may be formed of a single film made of any one of the above-described antiferromagnetic materials, or may be formed of a laminated film in which they are stacked.

피닝막(22)에 의하여 자화방향이 고정된 핀드막(23) 및 외부자극 예컨대, 자기장(magnetic field) 또는 스핀전달토크(Spin Transfer Torque, STT)에 의하여 자화방향이 변화하는 자유막(25)은 강자성(ferromagnetic)을 갖는 물질을 사용하여 형성할 수 있다. 예를 들어, 강자성을 갖는 물질로는 Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb,CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO 또는 Y3Fe5O12 등을 사용할 수 있다. 이때, 핀드막(23) 및 자유막(25)은 상술한 강자성 물질들 중 어느 하나로 이루어진 단일막으로 형성하거나, 이들이 적층된 적층막으로 형성할 수 있다. 또한, 핀드막(23) 및 자유막(25)은 상술한 강자성 물질들 중 어느 하나와 루테늄막(Ru)이 적층된 적층막으로 형성할 수 있다(예컨대, CdFe/Ru/CoFe). The pinned film 23 whose magnetization direction is fixed by the pinning film 22 and the free layer 25 whose magnetization direction changes by an external stimulus, for example, a magnetic field or spin transfer torque (STT). Can be formed using a material having ferromagnetic. For example, ferromagnetic materials include Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO 2 , MnOFe 2 O 3 , FeOFe 2 O 3 , NiOFe 2 O 3 , CuOFe 2 O 3 , MgOFe 2 O 3 , EuO or Y 3 Fe 5 O 12 may be used. In this case, the pinned layer 23 and the free layer 25 may be formed of a single layer made of any one of the above-described ferromagnetic materials, or may be formed of a laminated layer in which these layers are stacked. In addition, the pinned layer 23 and the free layer 25 may be formed as a laminated layer in which any one of the above-described ferromagnetic materials and the ruthenium layer Ru are stacked (eg, CdFe / Ru / CoFe).

또한, 핀드막(23) 및 자유막(25)은 강자성막, 반강자성 커플링 스페이서막 (anti-ferromagnetic coupling spacer layer) 및 강자성막이 순차적으로 적층된 합성 반강자성막(synthetic anti-ferromagnetic layer, SAF layer)으로 형성할 수도 있다. In addition, the pinned layer 23 and the free layer 25 may include a synthetic anti-ferromagnetic layer (SAF) in which a ferromagnetic layer, an anti-ferromagnetic coupling spacer layer, and a ferromagnetic layer are sequentially stacked. layer).

터널절연막(24)은 핀드막(23)과 자유막(25) 사이의 터널링장벽(tunneling barrier)으로 작용하며, 절연특성을 갖는 물질은 모두 사용할 수 있다. 예를 들어, 터널절연막(24)은 마그네슘산화막(MgO)으로 형성할 수 있다.The tunnel insulating layer 24 serves as a tunneling barrier between the pinned layer 23 and the free layer 25, and any material having an insulating property may be used. For example, the tunnel insulating film 24 may be formed of a magnesium oxide film (MgO).

다음으로, 적층막 상에 즉, 자유막(25) 상에 하드마스크패턴(26)을 형성한 후, 하드마스크패턴(26)을 식각장벽(etch barrier)으로 적층막을 자유막(25)까지 식각하여 제1패턴(27)을 형성한다. 즉, 하드마스크패턴(26)을 식각장벽으로 자유막(25)을 식각하여 식각된 자유막(25)과 하드마스크패턴(26)이 적층된 제1패턴(27)을 형성한다. Next, after the hard mask pattern 26 is formed on the laminated film, that is, on the free layer 25, the laminate layer is etched to the free layer 25 using the hard mask pattern 26 as an etch barrier. Thus, the first pattern 27 is formed. That is, the free layer 25 is etched using the hard mask pattern 26 as an etch barrier to form a first pattern 27 in which the etched free layer 25 and the hard mask pattern 26 are stacked.

여기서, 하드마스크패턴(26)은 절연물질 예컨대, 산화막, 질화막 및 산화질화막(oxynitride)으로 이루어진 그룹으로부터 선택된 어느 하나 또는 이들이 적층된 적층막을 형성할 수 있다. Here, the hard mask pattern 26 may form any one selected from the group consisting of an insulating material, for example, an oxide film, a nitride film, and an oxynitride, or a laminated film in which these layers are stacked.

또한, 하드마스크패턴(26)은 금속성막으로 형성할 수도 있다. 금속성막으로는 티타늄(Ti), 탄탈륨(Ta), 백금(Pt), 구리(Cu), 텅스텐(W), 알루미늄(Al), 티타늄질화막(TiN), 탄탈륨질화막(TaN), 텅스텐실리사이드(WSi) 등을 사용할 수 있다. 이때, 금속성막으로 하드마스크패턴(26)을 형성한 경우에는 하드마스크패턴(26)을 자기터널접합 장치의 상부전극으로 사용할 수 있다.In addition, the hard mask pattern 26 may be formed of a metallic film. Metallic films include titanium (Ti), tantalum (Ta), platinum (Pt), copper (Cu), tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten silicide (WSi). ) Can be used. In this case, when the hard mask pattern 26 is formed of a metal film, the hard mask pattern 26 may be used as an upper electrode of the magnetic tunnel junction device.

한편, 도면에 도시하지는 않았지만, 제1패턴(27)은 하드마스크패턴(26)을 식각장벽으로 적층막을 터널절연막(24)까지 식각하여 형성할 수도 있다. 즉, 하드마스크패턴(26)을 식각장벽으로 자유막(25) 및 터널절연막(24)을 식각하여 식각된 터널절연막(24), 자유막(25) 및 하드마스크패턴(26)이 적층된 구조의 제1패턴(27)을 형성할 수 있다. Although not shown in the drawing, the first pattern 27 may be formed by etching the stacked layer to the tunnel insulating layer 24 using the hard mask pattern 26 as an etch barrier. That is, a structure in which the tunnel insulation layer 24, the free layer 25, and the hard mask pattern 26 etched by etching the free layer 25 and the tunnel insulation layer 24 by etching the hard mask pattern 26 as an etch barrier are stacked. The first pattern 27 may be formed.

도 2b에 도시된 바와 같이, 제1패턴(27)을 형성하기 위한 식각공정과 동일 챔버에서 인시튜(in-situ)로 제1패턴(27)을 포함하는 구조물 전면에 절연성 폴리머막(28)을 형성한다. 이때, 절연성 폴리머막(28)은 후속 공정간 발생될 도전성부산 물에 의하여 자기터널접합 장치의 특성이 열화되는 것을 방지하는 역할을 수행한다. 특히, 도전성부산물에 의하여 자유막(25)과 핀드막(23) 사이에 쇼트가 발생하는 것을 방지하는 역할을 수행한다. As shown in FIG. 2B, the insulating polymer film 28 is formed on the entire surface of the structure including the first pattern 27 in-situ in the same chamber as the etching process for forming the first pattern 27. To form. In this case, the insulating polymer film 28 serves to prevent deterioration of the characteristics of the magnetic tunnel junction device due to conductive by-products to be generated between subsequent processes. In particular, the conductive byproduct serves to prevent the short from occurring between the free layer 25 and the pinned layer 23.

절연성 폴리머막(28)은 실리콘산화물(SixOy, x,y는 0을 제외한 자연수) 또는 실리콘질화물(SixNy, x,y는 0을 제외한 자연수)로 형성할 수 있다. 구체적으로, 절연성 폴리머막(28)은 실리콘산화물로 형성하는 경우에는 SiCl4가스와 산소가스(O2)가 혼합된 혼합가스를 챔버에 주입한 후, 플라즈마를 형성하여 제1패턴(27)을 포함하는 구조물 전면에 실리콘산화물로 이루어진 절연성 폴리머막(28)을 형성할 수 있다. 또한, 절연성 폴리머막(28)은 실리콘질화물로 형성하는 경우에는 SiCl4가스와 질소가스(N2)가 혼합된 혼합가스를 챔버에 주입한 후, 플라즈마를 형성하여 제1패턴(27)을 포함하는 구조물 전면에 실리콘질화물로 이루어진 절연성 폴리머막(28)을 형성할 수 있다.The insulating polymer film 28 may be formed of silicon oxide (Si x O y , where x and y are natural numbers except zero) or silicon nitride (Si x N y and x and y are natural numbers except zero). In detail, when the insulating polymer layer 28 is formed of silicon oxide, a mixture gas of SiCl 4 gas and oxygen gas (O 2 ) is injected into the chamber, and then plasma is formed to form the first pattern 27. An insulating polymer film 28 made of silicon oxide may be formed on the entire surface of the structure including the silicon oxide. In addition, when the insulating polymer layer 28 is formed of silicon nitride, a mixture gas of SiCl 4 gas and nitrogen gas (N 2 ) is injected into the chamber, and then plasma is formed to include the first pattern 27. An insulating polymer film 28 made of silicon nitride may be formed on the entire surface of the structure.

도 2c에 도시된 바와 같이, 절연성 폴리머막(28) 형성공정과 동일 챔버에서 인시튜로 전면식각공정 예컨대, 에치백(etchback)공정을 실시하여 제1패턴(27) 양측벽에 절연성 폴리머막(28)을 잔류시킨다. 이하, 제1패턴(27) 양측벽에 잔류하는 절연성 폴리머막(28)의 도면부호를 '28A'로 변경하여 표기한다. As shown in FIG. 2C, an insulating polymer film (for example, an etchback process) is performed in-situ in the same chamber as the insulating polymer film 28 forming process. 28) is left. Hereinafter, the reference numerals of the insulating polymer film 28 remaining on both side walls of the first pattern 27 are changed to '28A'.

여기서, 제1패턴(27) 양측벽에 잔류하는 절연성 폴리머막(28A)은 스페이서 형태를 가질 수 있다.Here, the insulating polymer layer 28A remaining on both side walls of the first pattern 27 may have a spacer shape.

도 2d에 도시된 바와 같이, 하드마스크패턴(26) 및 절연성 폴리머막(28A)을 식각장벽으로 터널절연막(24), 핀드막(23) 및 피닝막(22)을 순차적으로 식각하여 제2패턴(29)을 형성한다. 이하, 식각된 터널절연막(24)의 도면부호를 '24A'로, 핀드막(23)의 도면부호를 '23A'로, 피닝막(22)의 도면부호를 '22A'로 변경하여 표기한다. As shown in FIG. 2D, the tunnel mask 24, the pinned film 23, and the pinning film 22 are sequentially etched using the hard mask pattern 26 and the insulating polymer film 28A as an etch barrier to form a second pattern. (29) is formed. Hereinafter, the reference numeral of the etched tunnel insulating film 24 is changed to '24A', the reference numeral of the pinned film 23 is changed to '23A', and the reference numeral of the pinning film 22 is changed to '22A'.

한편, 제1패턴(27)을 터널절연막(24A)까지 식각하여 형성한 경우에는 하드마스크패턴(26) 및 절연성 폴리머막(28A)을 식각장벽으로 핀드막(23A) 및 피닝막(22A)을 식각하여 제2패턴(29)을 형성할 수 있다. On the other hand, when the first pattern 27 is formed by etching the tunnel insulating film 24A, the pinned film 23A and the pinning film 22A are formed using the hard mask pattern 26 and the insulating polymer film 28A as etch barriers. The second pattern 29 may be formed by etching.

상술한 공정과정을 통해 제1패턴(27) 및 제2패턴(29)으로 이루어진 자기터널접합 장치를 완성할 수 있다. Through the above-described process, the magnetic tunnel junction device including the first pattern 27 and the second pattern 29 may be completed.

여기서, 제2패턴(29)을 형성하는 과정에서 도전성부산물(P)이 생성될 수 있으며, 생성된 도전성부산물(P)이 제2패턴(29) 측벽, 절연성 폴리머막(28A) 측벽에 재증착될 수 있다. 하지만, 본 발명은 절연성 폴리머막(28A)에 의하여 도전성부산물(P)이 자기터널접합 장치의 측벽에 재증착되더라도, 도전성부산물(P)에 의하여 자유막(25)과 핀드막(23A) 사이에 쇼트가 발생하는 것을 방지할 수 있다. Here, the conductive byproduct P may be generated in the process of forming the second pattern 29, and the conductive byproduct P may be redeposited on the sidewall of the second pattern 29 and the sidewall of the insulating polymer film 28A. Can be. However, in the present invention, even if the conductive by-product P is redeposited on the sidewall of the magnetic tunnel junction device by the insulating polymer film 28A, the conductive by-product P is formed between the free layer 25 and the pinned film 23A. Short can be prevented from occurring.

이로써, 도전성부산물에 의해 자기터널접합 장치의 전기적인 특성이 열화되는 것을 방지할 수 있으며, 자기터널접합 장치를 구비하는 반도체 장치의 신뢰성 및 제조 수율을 향상시킬 수 있다.Thereby, the electrical characteristics of the magnetic tunnel junction apparatus can be prevented from being deteriorated by the conductive by-product, and the reliability and manufacturing yield of the semiconductor device including the magnetic tunnel junction apparatus can be improved.

또한, 자기터널접합 장치를 형성하기 위한 식각공정 및 절연성 폴리머막(28A) 형성공정을 동일 챔버에서 인시튜로 진행함으로써, 자기터널접합 장치의 생산성을 향상시킬 수 있다. In addition, by performing the etching process for forming the magnetic tunnel bonding device and the insulating polymer film 28A in situ in the same chamber, the productivity of the magnetic tunnel bonding device can be improved.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술사상의 범위내의 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

도 1은 종래기술에 따른 자기터널접합 장치를 도시한 단면도. 1 is a cross-sectional view showing a magnetic tunnel junction device according to the prior art.

도 2a 내지 도 2d는 본 발명의 일실시예에 따른 자기터널접합 장치 제조방법을 도시한 공정단면도. Figure 2a to 2d is a process cross-sectional view showing a method for manufacturing a magnetic tunnel junction device according to an embodiment of the present invention.

*도면 주요 부분에 대한 부호 설명** Description of symbols on the main parts of the drawings *

21 : 기판 22, 22A : 피닝막21: substrate 22, 22A: pinning film

23, 23A : 핀드막 24, 24A : 터널절연막23, 23A: pinned film 24, 24A: tunnel insulation film

25 : 자유막 26 : 하드마스크패턴25: free layer 26: hard mask pattern

27 : 제1패턴 28, 28A : 절연성 폴리머막27: first pattern 28, 28A: insulating polymer film

29 : 제2패턴29: second pattern

Claims (6)

피닝막, 핀드막, 터널절연막 및 자유막이 순차적으로 적층된 적층막을 형성하는 단계;Forming a laminated film in which a pinning film, a pinned film, a tunnel insulating film, and a free film are sequentially stacked; 상기 적층막 상에 하드마스크패턴을 형성하는 단계;Forming a hard mask pattern on the laminated film; 상기 적층막을 상기 하드마스크패턴을 식각장벽으로 상기 자유막까지 식각하여 제1패턴을 형성하는 단계;Forming a first pattern by etching the stacked layer to the free layer using the hard mask pattern as an etch barrier; 상기 제1패턴 양측벽에 절연성 폴리머막을 형성하는 단계; 및Forming an insulating polymer film on both sidewalls of the first pattern; And 상기 하드마스크패턴 및 상기 절연성 폴리머막을 식각장벽으로 나머지 상기 적층막을 식각하여 제2패턴을 형성하는 단계Etching the remaining layered layer using the hard mask pattern and the insulating polymer layer as an etch barrier to form a second pattern 를 포함하는 자기터널접합 장치 제조방법. Magnetic tunnel junction device manufacturing method comprising a. 제1항에 있어서, The method of claim 1, 상기 제1패턴을 형성하는 단계는, Forming the first pattern, 상기 적층막을 상기 하드마스크패턴을 식각장벽으로 상기 터널절연막까지 식각하여 형성하는 자기터널접합 장치 제조방법. And forming the laminated layer by etching the hard mask pattern to the tunnel insulating layer using an etch barrier. 제1항 또는 제2항에 있어서, The method according to claim 1 or 2, 상기 제1패턴을 형성하는 단계. 상기 절연성 폴리머막을 형성하는 단계 및 상기 제2패턴을 형성하는 단계는 동일 챔버에서 인시튜로 진행하는 자기터널접합 장치 제조방법. Forming the first pattern. The forming of the insulating polymer film and the forming of the second pattern may be performed in-situ in the same chamber. 제1항 또는 제2항에 있어서, The method according to claim 1 or 2, 상기 절연성 폴리머막은,The insulating polymer film, 실리콘산화물(SixOy, x,y는 0을 제외한 자연수) 또는 실리콘질화물(SixNy, x,y는 0을 제외한 자연수)을 포함하는 자기터널접합 장치 제조방법. Method of manufacturing a magnetic tunnel junction device comprising a silicon oxide (Si x O y , x, y is a natural number except 0) or silicon nitride (Si x N y , x, y is a natural number except 0). 제4항에 있어서, The method of claim 4, wherein 상기 절연성 폴리머막을 형성하는 단계는, Forming the insulating polymer film, 챔버에 SiCl4가스와 산소가스(O2)가 혼합된 혼합가스 또는 SiCl4가스와 질소가스(N2)가 혼합된 혼합가스의 플라즈마를 사용하여 형성하는 자기터널접합 장치 제조방법. A method of manufacturing a magnetic tunnel junction apparatus using a plasma of a mixed gas in which SiCl 4 gas and oxygen gas (O 2 ) are mixed in a chamber or a mixed gas in which SiCl 4 gas and nitrogen gas (N 2 ) are mixed. 제1항에 있어서, The method of claim 1, 상기 하드마스크패턴은 산화막, 질화막 및 산화질화막으로 이루어진 그룹으로부터 선택된 어느 하나 또는 이들이 적층된 적층막으로 형성하거나, 또는 금속성막으로 형성하는 자기터널접합 장치 제조방법. And the hard mask pattern is formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a laminated film in which they are laminated, or a metal tunnel film.
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Cited By (8)

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US8420408B2 (en) 2010-07-21 2013-04-16 Hynix Semiconductor Inc. Semiconductor memory and manufacturing method thereof
US8823119B2 (en) 2012-03-09 2014-09-02 Samsung Electronics Co., Ltd. Magnetic device having a metallic glass alloy
US9029964B2 (en) 2011-09-28 2015-05-12 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
KR20160091504A (en) * 2015-01-23 2016-08-03 삼성전자주식회사 A method of forming fine patterns, a method of forming semiconductor devices using the same, and semiconductor devices manufactured using the same
KR20170039430A (en) * 2015-10-01 2017-04-11 삼성전자주식회사 Semiconductor device having a magnetic tunnel junction assembly and Method for fabricating the same
CN107623069A (en) * 2016-07-14 2018-01-23 上海磁宇信息科技有限公司 A kind of method for etching MTJ and its hearth electrode
CN107968150A (en) * 2016-09-06 2018-04-27 三星电子株式会社 The method for manufacturing magnetic memory device
US10431735B2 (en) 2017-05-19 2019-10-01 SK Hynix Inc. Electronic device and method for fabricating the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8420408B2 (en) 2010-07-21 2013-04-16 Hynix Semiconductor Inc. Semiconductor memory and manufacturing method thereof
US9029964B2 (en) 2011-09-28 2015-05-12 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
US8823119B2 (en) 2012-03-09 2014-09-02 Samsung Electronics Co., Ltd. Magnetic device having a metallic glass alloy
KR20160091504A (en) * 2015-01-23 2016-08-03 삼성전자주식회사 A method of forming fine patterns, a method of forming semiconductor devices using the same, and semiconductor devices manufactured using the same
KR20170039430A (en) * 2015-10-01 2017-04-11 삼성전자주식회사 Semiconductor device having a magnetic tunnel junction assembly and Method for fabricating the same
CN107623069A (en) * 2016-07-14 2018-01-23 上海磁宇信息科技有限公司 A kind of method for etching MTJ and its hearth electrode
CN107968150A (en) * 2016-09-06 2018-04-27 三星电子株式会社 The method for manufacturing magnetic memory device
US10177307B2 (en) 2016-09-06 2019-01-08 Samsung Electronics Co., Ltd. Methods of fabricating magnetic memory devices
CN107968150B (en) * 2016-09-06 2023-04-07 三星电子株式会社 Method of manufacturing magnetic memory device
US10431735B2 (en) 2017-05-19 2019-10-01 SK Hynix Inc. Electronic device and method for fabricating the same

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