KR20100070601A - Method for producing solar cell device - Google Patents

Method for producing solar cell device Download PDF

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KR20100070601A
KR20100070601A KR1020080129222A KR20080129222A KR20100070601A KR 20100070601 A KR20100070601 A KR 20100070601A KR 1020080129222 A KR1020080129222 A KR 1020080129222A KR 20080129222 A KR20080129222 A KR 20080129222A KR 20100070601 A KR20100070601 A KR 20100070601A
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solar cell
electrode
cell device
forming
doped
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Korean (ko)
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김강필
김재현
우성호
류홍근
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재단법인대구경북과학기술원
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    • H—ELECTRICITY
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    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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Abstract

PURPOSE: A method for manufacturing a solar cell device is provided to simplify a manufacturing process using a nano-structure which is formed by an electrochemical etching process. CONSTITUTION: A first electrode(102) is formed on a silicon substrate(104). A nano-structure(112) including a plurality of rods is formed on the surface of the silicon substrate. An n-type silicon layer(106) is formed on the surface of the silicon substrate. A transparent conductive film(108) is formed on the n-type silicon layer. A second electrode(110) is formed on the transparent conductive film.

Description

태양전지 소자의 제조방법{Method for producing solar cell device}Method for producing solar cell device {Method for producing solar cell device}

본 발명은 전기화학적 에칭으로 형성된 나노구조체를 이용한 태양전지 소자에 관한 것이다. The present invention relates to a solar cell device using a nanostructure formed by electrochemical etching.

현재 Si 태양전지는 가장 일반적으로 사용되는 태양전지이다. Currently, Si solar cells are the most commonly used solar cells.

종래의 Si 나노구조체를 이용한 태양전지, 예를 들어 대한민국 특허공개공보 제2008-0044181호(발명의 명칭: 구배된 하이브리드 비정질 규소 나노와이어 태양광 전지)는 일반적으로 금속 촉매를 이용하여 Si 나노구조체를 성장시켜 태양전지에 응용하고 있다. A solar cell using a conventional Si nanostructure, for example, Korean Patent Publication No. 2008-0044181 (name of the invention: gradient hybrid amorphous silicon nanowire photovoltaic cell) generally uses a metal catalyst to form a Si nanostructure. It is growing and applied to solar cells.

이런 Si 나노구조체를 이용한 태양전지의 장점은 표면 단면적의 증가에 따른 광흡수 면적의 증가로 태양전지의 효율이 향상될 수 있다. 그러나, Si 나노구조체를 성장시켜 태양전지 소자를 제작할 경우, Si 나노구조체의 위치 정렬과 간격유지의 어려움이 있으며 수직 방향성의 유지에도 어려움이 발생한다.The advantage of the solar cell using such a Si nanostructure is that the efficiency of the solar cell can be improved by increasing the light absorption area according to the increase in the surface cross-sectional area. However, when manufacturing a solar cell device by growing the Si nanostructure, there is a difficulty in the alignment and spacing of the Si nanostructure and there is also a difficulty in maintaining the vertical orientation.

본 발명은 Si 기판의 전기화학적 에칭(electrochemical etching)을 이용하여 형성된 Si 나노구조체를 이용한 태양전지 소자를 제작하므로, 마스크 패턴의 모양에 따른 원하는 형상의 Si 나노구조체를 제작하고, 마스크 패턴과 전기화학적 에칭 용액의 조성 조절을 통해 Si 나노구조체의 위치 및 간격의 유지와 수직 방향성을 얻는데 그 목적이 있다. Since the present invention manufactures a solar cell device using a Si nanostructure formed by using electrochemical etching of the Si substrate, to produce a Si nanostructure of the desired shape according to the shape of the mask pattern, the mask pattern and the electrochemical The purpose of the composition of the etching solution is to maintain the position and spacing of the Si nanostructures and to obtain vertical orientation.

본 발명은 제1타입으로 도핑된 반도체 재료를 제공하는 단계와, 상기 도핑된 반도체 재료 상에 제1전극을 형성하는 단계와, 상기 반도체 재료의 표면에 에칭 용액에서 전기화학적 에칭에 의해 다수의 로드(rod)를 갖는 나노구조체를 형성하는 단계와, 상기 에칭된 반도체 재료 상에 상기 반도체 재료와 다른 타입의 레이어(layer)를 형성하는 단계와, 상기 레이어 상에 제2전극을 형성하는 단계를 포함하는 태양전지 소자의 제조방법을 제공한다.The present invention provides a plurality of rods by providing a doped semiconductor material of a first type, forming a first electrode on the doped semiconductor material, and electrochemical etching in an etching solution on the surface of the semiconductor material. forming a nanostructure having a rod, forming a layer of a different type from the semiconductor material on the etched semiconductor material, and forming a second electrode on the layer. It provides a method of manufacturing a solar cell device.

이때, 상기 에칭 용액은 HF:DMSO(Dimethyl Sulfoxide):H2O 조성을 가질 수 있다. 상기 에칭 용액 중 DMSO(Dimethyl Sulfoxide)과 H2O의 상대적인 조성비는 1~99%의 DMSO와 1~99%의 H2O일 수 있다. In this case, the etching solution may have a composition of HF: DMSO (Dimethyl Sulfoxide): H 2 O. The relative composition ratio of DMSO (Dimethyl Sulfoxide) and H 2 O in the etching solution may be 1 to 99% DMSO and 1 to 99% H 2 O.

또한, 상기 반도체 재료는 p-도핑되고 상기 레이어는 n-도핑된 n-Si일 수 있다. 상기 n-Si와 상기 제2전극 사이에 Al 도핑된 ZnO 투명전도막을 형성하는 단계 를 추가로 포함할 수 있다. In addition, the semiconductor material may be p-doped and the layer may be n-doped n-Si. The method may further include forming an Al doped ZnO transparent conductive film between the n-Si and the second electrode.

또한, 상기 전기화학적 에칭시 1~100mA/cm2 의 전류밀도가 인가될 수 있다. 상기 나노구조체의 로드들은 1nm~100um 의 지름을 갖고, 상기 나노구조체의 로드들 사이 간격은 1nm~100um일 수 있다.In addition, a current density of 1 ~ 100mA / cm 2 may be applied during the electrochemical etching. Rods of the nanostructures may have a diameter of 1nm ~ 100um, the interval between the rods of the nanostructures may be 1nm ~ 100um.

본 발명은 전기화학적 에칭으로 형성된 나노구조체를 이용한 태양전지 소자에 관한 것으로, 태양전지의 효율을 향상시키고, 공정을 단순화할 수 있으며 나노구조체의 위치 및 간격을 제어할 수 있는 효과가 있다.The present invention relates to a solar cell device using a nanostructure formed by electrochemical etching, it is possible to improve the efficiency of the solar cell, simplify the process and control the position and spacing of the nanostructure.

이하, 본 발명의 일부 실시예들을 예시적인 도면을 통해 설명한다. 각 도면의 구성요소들에 참조부호를 부가함에 있어서, 동일한 구성요소들에 대해서는 비록 다른 도면상에 표시되더라도 가능한 한 동일한 부호를 가지도록 하고 있음에 유의해야 한다. 또한, 본 발명을 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명은 생략한다.Hereinafter, some embodiments of the present invention will be described by way of example. In adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are assigned to the same components as much as possible even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

또한, 본 발명의 구성 요소를 설명하는 데 있어서, 제 1, 제 2, A, B, (a), (b) 등의 용어를 사용할 수 있다. 이러한 용어는 그 구성 요소를 다른 구성 요소와 구별하기 위한 것일 뿐, 그 용어에 의해 해당 구성 요소의 본질이나 차례 또는 순서 등이 한정되지 않는다. 어떤 구성 요소가 다른 구성요소에 "연결", "결합" 또는 "접속"된다고 기재된 경우, 그 구성 요소는 그 다른 구성요소에 직접적으로 연결되거나 또는 접속될 수 있지만, 각 구성 요소 사이에 또 다른 구성 요소가 "연결", "결합" 또는 "접속"될 수도 있다고 이해되어야 할 것이다.In addition, in describing the component of this invention, terms, such as 1st, 2nd, A, B, (a), (b), can be used. These terms are only for distinguishing the components from other components, and the nature, order or order of the components are not limited by the terms. If a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to that other component, but there may be another configuration between each component. It is to be understood that the elements may be "connected", "coupled" or "connected".

도 1은 본 발명의 일 실시예에 따른 태양전지 소자의 단면도이다.1 is a cross-sectional view of a solar cell device according to an embodiment of the present invention.

도 1을 참조하면, 본 발명의 일 실시예에 따른 태양전지 소자(100)는 제1전극(102)과 Si 기판(104), n-Si 레이어(106), 투명전도막(108), 제2전극(110)을 포함한다.Referring to FIG. 1, a solar cell device 100 according to an embodiment of the present invention may include a first electrode 102, an Si substrate 104, an n-Si layer 106, a transparent conductive film 108, and a first electrode 102. And two electrodes 110.

제1전극(102)는 Si 기판(104) 상에 증착된 전극으로 어떠한 금속재료, 예를 들어 구리나 알루미늄, 은 등일 수 있다. 본 명세서에서는 제1전극을 Al 전극인 것으로 예시하여 설명한다. 제1전극은 아래에서 설명한 Si 기판의 전기화학적 에칭시 전극으로 사용된다. The first electrode 102 is an electrode deposited on the Si substrate 104 and may be any metal material, for example, copper, aluminum, silver, or the like. In the present specification, the first electrode will be described as being an Al electrode. The first electrode is used as an electrode in the electrochemical etching of the Si substrate described below.

Si 기판(104)은 p 도판트를 포함하는 p-도핑된 단결정 Si 기판이다. 물론, Si 기판은 n-도핑된 단결정 Si 기판이어도 무방하다. 이때 반도체 재료는 Si에 제한되지 않고 다른 반도체 재료, 예를 들어 SiGe, 갈륨 아르세나이드(GaAs), 갈륨 포스파이드(GaP), 인듐 포스파이드(InP), GaInP, 게르마늄(Ge), GaInAs, 알루미늄 갈륨 아르세나이드(AlGaAs), 산화 아연(ZnO), 질화 갈륨(GaN), 질화 알루미늄(AlN), 질화 인듐(InN), 질화 붕소(BN), 셀레늄(Se), 카드뮴 셀레나이드(CdSe), 카드뮴 텔루라이드(CdTe), Cd-O-Te, Cd-Mn-O-Te, ZnTe, Zn-O-Te, Zn-Mn-O-Te, MnTe, Mn-O-Te, 구리 산화물, 탄소, Cu-In-Ga-Se, Cu-In-Se 및 유사한 조성물, 및 이들의 조합일 수 있다. Si substrate 104 is a p-doped single crystal Si substrate comprising a p dopant. Of course, the Si substrate may be an n-doped single crystal Si substrate. The semiconductor material is not limited to Si and other semiconductor materials, such as SiGe, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), GaInP, germanium (Ge), GaInAs, aluminum Gallium arsenide (AlGaAs), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), boron nitride (BN), selenium (Se), cadmium selenide (CdSe), Cadmium Telluride (CdTe), Cd-O-Te, Cd-Mn-O-Te, ZnTe, Zn-O-Te, Zn-Mn-O-Te, MnTe, Mn-O-Te, Copper Oxide, Carbon, Cu-In-Ga-Se, Cu-In-Se and similar compositions, and combinations thereof.

Si 기판(104)의 표면에는 다수의 로드들을 갖는 나노구조체(112)가 다수 형성되어 있다. 결과적으로 나노구조체(112)의 로드들 사이는 n-Si 레이어(106) 및/또는 투명전도막이 마련되는 공간(114)을 형성한다. On the surface of the Si substrate 104, a plurality of nanostructures 112 having a plurality of rods are formed. As a result, the space 114 between the n-Si layer 106 and / or the transparent conductive film is formed between the rods of the nanostructure 112.

n-Si 레이어(106)는 나노구조체(112)가 형성된 Si 기판(104)의 표면 상에 증착되어 있다. n 도판트, 예를 들어 N, P, As 등을 포함하는 n-도핑된 n-Si 레이어(106)는 p-도핑된 단결정 Si 기판(104)과 태양전지 소자용 p-n junction을 형성하게 되는 것이다. 따라서, 단결정 Si 기판(104)이 n-도핑되어 있는 경우에 p-n junction을 형성을 형성할 수 있도록 Si 레이어는 p-Si일 수도 있다. An n-Si layer 106 is deposited on the surface of the Si substrate 104 on which the nanostructures 112 are formed. The n-doped n-Si layer 106 comprising n dopants, for example N, P, As, etc., will form a p-doped single crystal Si substrate 104 and a pn junction for the solar cell device. . Therefore, the Si layer may be p-Si so as to form a p-n junction when the single crystal Si substrate 104 is n-doped.

이때 n-Si 레이어(106)의 반도체 재료는 Si에 제한되지 않고 다른 반도체 재료, 예를 들어 SiGe, 갈륨 아르세나이드(GaAs), 갈륨 포스파이드(GaP), 인듐 포스파이드(InP), GaInP, 게르마늄(Ge), GaInAs, 알루미늄 갈륨 아르세나이드(AlGaAs), 산화 아연(ZnO), 질화 갈륨(GaN), 질화 알루미늄(AlN), 질화 인듐(InN), 질화 붕소(BN), 셀레늄(Se), 카드뮴 셀레나이드(CdSe), 카드뮴 텔루라이드(CdTe), Cd-O-Te, Cd-Mn-O-Te, ZnTe, Zn-O-Te, Zn-Mn-O-Te, MnTe, Mn-O-Te, 구리 산화물, 탄소, Cu-In-Ga-Se, Cu-In-Se 및 유사한 조성물, 및 이들의 조합일 수 있다. 본 명세서에서는 레이어(106)의 재료로 n-Si인 것으로 예시적으로 설명하였으나, 본 발명은 이에 제한되지 않는다.  At this time, the semiconductor material of the n-Si layer 106 is not limited to Si, and other semiconductor materials such as SiGe, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), GaInP, Germanium (Ge), GaInAs, Aluminum Gallium Arsenide (AlGaAs), Zinc Oxide (ZnO), Gallium Nitride (GaN), Aluminum Nitride (AlN), Indium Nitride (InN), Boron Nitride (BN), Selenium (Se) , Cadmium selenide (CdSe), cadmium telluride (CdTe), Cd-O-Te, Cd-Mn-O-Te, ZnTe, Zn-O-Te, Zn-Mn-O-Te, MnTe, Mn-O -Te, copper oxide, carbon, Cu-In-Ga-Se, Cu-In-Se and similar compositions, and combinations thereof. In the present specification, the material of the layer 106 is exemplarily described as being n-Si, but the present invention is not limited thereto.

투명전도막(108)은 n-Si 레이어(106) 상에 형성되어 있다. 투명전도막은 투명도전성 산화물(TCO), 예를 들어 ITO나 ZnO 등 일반적으로 디스플레이 소자에서 사용하는 어떠한 형태의 투명전도막 또는 투명전극 재료이더라도 무방하다. The transparent conductive film 108 is formed on the n-Si layer 106. The transparent conductive film may be any type of transparent conductive film or transparent electrode material generally used in display devices such as transparent conductive oxide (TCO), for example, ITO or ZnO.

제2전극(110)은 투명전도막(108) 상에 형성되어 있다. 제2전극은 제1전극과 마찬가지로 어떠한 금속재료, 예를 들어 구리나 알루미늄, 은 등일 수 있다. 본 명세서에서는 제1전극을 Ag 전극인 것으로 예시하여 설명한다. The second electrode 110 is formed on the transparent conductive film 108. Like the first electrode, the second electrode may be any metal material, for example, copper, aluminum, silver, or the like. In the present specification, the first electrode will be described as an Ag electrode.

본 발명의 다른 실시예에 따른 태양전지 소자의 제조방법(200)은 Si 기판 준비단계(S202)와, 제1전극 형성단계(S204), 나노구조체 형성 단계(S206), Si 레이어 형성단계(S207), 투명전도막 형성단계(S208), 제2전극 형성단계(S210)를 포함한다.Method of manufacturing a solar cell device 200 according to another embodiment of the present invention 200 is Si substrate preparation step (S202), the first electrode forming step (S204), nanostructure forming step (S206), Si layer forming step (S207) ), The transparent conductive film forming step (S208), and the second electrode forming step (S210).

도 1 및 도 2를 참조하면, Si 기판 준비단계(S202)는 n 또는 p-도핑된 단결정 Si 기판을 준비하는 단계이다. 1 and 2, the Si substrate preparation step S202 is a step of preparing an n or p-doped single crystal Si substrate.

제1전극 형성단계(S204)는 Si 기판(104) 상에 제1전극(102)를 형성하는 단계이다. Si 기판(104) 상에 제1전극(102)에 형성하는 방법은 일반적인 반도체 공정 또는 디스플레이 소자의 전극 형성방법, 예를 들어 플라즈마 증착방법일 수 있다. The first electrode forming step S204 is a step of forming the first electrode 102 on the Si substrate 104. The method of forming the first electrode 102 on the Si substrate 104 may be a general semiconductor process or an electrode forming method of a display device, for example, a plasma deposition method.

나노구조체 형성단계(S206)는 Si 기판(104)의 표면에 다수의 로드들를 갖는 나조구조체(112)를 형성하는 단계이다. The nanostructure forming step (S206) is a step of forming a spiral structure 112 having a plurality of rods on the surface of the Si substrate 104.

이 단계(S206)에서 도핑된, 예를 들어 p-도핑된 단결정 Si 기판(100)을 HF:DMSO(Dimethyl Sulfoxide):H2O 조성의 용액에서 나노 필름(nano film)을 마스크로 사용하여 전기화학적 에칭에 의해 다수의 로드들를 갖는 나노구조체(112)가 형성된 p-Si 나노구조체(nanostructure)를 제작한다. 이때, p-Si 기판(104)의 반대쪽 에 증착된 Al 전극(102)은 전기화학적 에칭시 전극으로 사용된다. 전기화학적 에칭시 1~100mA/cm2 의 전류밀도가 인가되나 이에 제한되지 않는다. 에칭 후 나노 필름들을 제거되어 나노구조체에서 남겨지지 않는다.In this step S206, the doped, for example, p-doped single crystal Si substrate 100 was fabricated using a nano film as a mask in a solution of HF: DMSO (Dimethyl Sulfoxide): H 2 O composition. A p-Si nanostructure in which a nanostructure 112 having a plurality of rods is formed by chemical etching is manufactured. At this time, the Al electrode 102 deposited on the opposite side of the p-Si substrate 104 is used as an electrode during the electrochemical etching. In the electrochemical etching, a current density of 1 to 100 mA / cm 2 is applied, but not limited thereto. After etching, the nano films are removed so that they are not left in the nanostructures.

이때, 에칭 용액 중 DMSO(Dimethyl Sulfoxide)과 H2O는 나노구조체의 로드들의 지름이나 로드들 사이의 간격을 조절하기 위해 다양한 상대적인 조성비를 가질 수 있다. 예를 들어, DMSO(Dimethyl Sulfoxide)과 H2O의 상대적인 조성비는 1~99%의 DMSO와 1~99%의 H2O를 갖지만 이에 제한되지 않는다. In this case, DMSO (dimethyl sulfoxide) and H 2 O in the etching solution may have various relative composition ratios in order to control the diameter of the rods of the nanostructure or the gap between the rods. For example, the relative composition ratio of DMSO (Dimethyl Sulfoxide) and H 2 O has, but is not limited to, 1-99% DMSO and 1-99% H 2 O.

전기화학적 에칭시 인가된 전류밀도나 DMSO(Dimethyl Sulfoxide)과 H2O의 상대적인 조성비, 반도체 재료를 조절하여, 나노구조체(112)의 로드들의 지름은 1nm~100um, 나노구조체(112)의 로드들 사이 간격은 1nm~100um인 나노구조체를 형성할 수 있다. By adjusting the current density applied to the electrochemical etching, the relative composition ratio of DMSO (dimethyl sulfoxide) and H 2 O, and the semiconductor material, the diameter of the rods of the nanostructure 112 is 1 nm ~ 100um, the rods of the nanostructure 112 The interval between the nanostructures can form 1nm ~ 100um.

Si 레이어 형성단계(S207)는 다수의 로드들을 갖는 나노구조체(112)가 형성된 Si 기판(104)의 표면 상에 n-Si 레이어(106)를 형성하는 단계이다. 앞에서 설명한 바와 같이, 이 단계(S208)에서 형성된 n-Si 레이어(106)는 p-도핑된 단결정 Si 기판(104)과 태양전지 소자용 p-n junction을 형성하게 된다. The Si layer forming step S207 is a step of forming the n-Si layer 106 on the surface of the Si substrate 104 on which the nanostructure 112 having a plurality of rods is formed. As described above, the n-Si layer 106 formed in this step S208 forms a p-doped single crystal Si substrate 104 and a p-n junction for a solar cell device.

투명전도막 형성단계(S208)는 n-Si 레이어(106) 상에 ITO나 ZnO, ITZnO 등 의 투명전도막(108)을 형성하는 단계이다. 이 단계(S208)에서 투명전도막(108)에 형성하는 방법은 일반적인 반도체 공정 또는 디스플레이 소자의 전극 형성방법, 예 를 들어 습식 또는 건식에칭 방법일 수 있다. The transparent conductive film forming step (S208) is a step of forming a transparent conductive film 108 such as ITO, ZnO, or ITZnO on the n-Si layer 106. The method of forming the transparent conductive film 108 in this step S208 may be a general semiconductor process or a method of forming an electrode of a display device, for example, a wet or dry etching method.

S207 단계와 S208 단계에서 n-Si 레이어(106)와 투명전도막(108)은 각각 나노구조체(112)의 표면과 이들 사이 공간(114)에 형성된다. In steps S207 and S208, the n-Si layer 106 and the transparent conductive film 108 are formed in the surface of the nanostructure 112 and the space 114 therebetween, respectively.

제2전극 형성단계(S210)는 투명전도막(108) 상에 구리나 알루미늄, 은 등의 제2전극(110)을 형성하는 단계이다. 제2전극(110)을 형성하는 방법도 일반적인 반도체 공정 또는 디스플레이 소자의 전극 형성방법일 수 있다. The second electrode forming step S210 is a step of forming the second electrode 110 of copper, aluminum, silver, or the like on the transparent conductive film 108. The method of forming the second electrode 110 may also be a general semiconductor process or an electrode forming method of a display device.

비교실시예1Comparative Example 1

p-Si 기판(104)의 뒷면에 Al 전극(102)을 100~500nm 증착 후 HF:DMSO:H2O 조성의 용액에서 1~100mA/cm2 의 인가 전류밀도로 전기화학적 에칭을 통해 나노 노드들(112)을 형성하고, 다른 구성요소들, n-Si(106), Al 도핑된 투명도전막(108), Ag 전극(110)을 위에서 설명한 제조방법에 따라 형성한 나노구조체의 SEM 영상이 도3이다. After depositing 100-500 nm of the Al electrode 102 on the back of the p-Si substrate 104, the nano-nodes were subjected to electrochemical etching at an applied current density of 1-100 mA / cm 2 in a solution of HF: DMSO: H 2 O composition. SEM image of a nanostructure formed with the same structure as the above-described method for forming the field 112, and other components, n-Si 106, Al doped transparent conductive film 108, Ag electrode 110, 3

한편, HF:DMSO:H2O 조성의 용액 대신 HF:Ethanol:H2O 와 HF:Acetone:H2O 조성의 에칭용액에서 전기화학적 에칭으로 제작된 나노구조체의 SEM 영상이 도4이다.Meanwhile, FIG. 4 is an SEM image of a nanostructure fabricated by electrochemical etching in an etching solution of HF: Ethanol: H 2 O and HF: Acetone: H 2 O instead of a solution of HF: DMSO: H 2 O.

다른 한편, HF:DMSO:H2O 조성의 용액 대신 HF:DMSO 조성의 에칭용액에서 전기화학적 에칭으로 제작된 너노 구조체의 SEM 영상이 도5이다.On the other hand, FIG. 5 is an SEM image of a nuno structure fabricated by electrochemical etching in an etching solution of HF: DMSO composition instead of a solution of HF: DMSO: H 2 O composition.

도 3과 도 4를 비교하므로 알 수 있는 바와 같이, HF:Ethanol:H2O 또는 HF:Acetone:H2O 조성을 이용한 p-Si 나노구조체를 제작하는 경우, HF:DMSO:H2O 조성에서 제작된 경우보다 구멍의 방향성이 좋지 않으며 로드나 벽의 표면 거칠기가 좋지 않아 균일한 나노구조체를 제작할 수 없다. As can be seen by comparing FIG. 3 with FIG. 4, when fabricating a p-Si nanostructure using the HF: Ethanol: H 2 O or HF: Acetone: H 2 O composition, the HF: DMSO: H 2 O composition was used. The hole orientation is better than the fabricated case, and the surface roughness of the rod or the wall is not good, so that a uniform nanostructure cannot be produced.

반대로, 본 발명에 따라 제조한 p-Si 나노구조체는 HF:Ethanol:H2O 또는 HF:Acetone:H2O 조성의 에칭용액 이용한 p-Si 나노구조체보다 구멍들(pores)의 방향성이나 나노구조체의 표면, 예를 들어 전기화학적 에칭 후 남겨진 로드(rod)나 로드의 벽(wall)의 표면 거칠기가 좋을 것을 확인할 수 있었다. On the contrary, p-Si nanostructures prepared according to the present invention are more directional or nanostructures of pores than p-Si nanostructures using an etching solution of HF: Ethanol: H 2 O or HF: Acetone: H 2 O composition. It can be confirmed that the surface roughness of the surface of the rod, for example, a rod or a wall of the rod, remaining after the electrochemical etching.

도 3 및 도 5를 비교하므로 알 수 있는 바와 같이, H2O가 함유되지 않은 HF:DMSO 조성의 에칭용액을 이용하여 제작된 나노구조체의 경우, 에탄올이나 아세톤이 함유된 조성의 경우보다도 더 불균일한 구멍들(pores)를 형성하였다. As can be seen by comparing FIG. 3 and FIG. 5, in the case of the nanostructure fabricated using the etching solution of HF: DMSO composition containing no H 2 O, it is more heterogeneous than the composition containing ethanol or acetone. Pores were formed.

본 발명과 같이, DMSO 또는 DMF와 같은 aportic 특성을 가지는 용매를 함유한 에칭용액은 전기화학적 에칭시 aprotic한 특성에 의해 Si과의 반응성은 빠르나 대신 거친 표면을 형성하는데 HF과 DMSO와 H2O의 적당한 비율조절을 통해 반응성을 조정하여 에칭의 방향성을 한방향으로 조정하고 에칭된 표면의 거칠기도 부드럽게 조정할 수 있었다.As in the present invention, an etching solution containing a solvent having aportic properties, such as DMSO or DMF, has a fast reactivity with Si due to aprotic properties during electrochemical etching, but instead forms a rough surface. HF, DMSO and H 2 O By adjusting the reactivity through proper ratio adjustment, the directionality of the etching could be adjusted in one direction and the roughness of the etched surface could be smoothly adjusted.

또한, 본 발명에 따라 형성된 Si 나노구조체는, 일반적인 Si의 전기화학적 에칭을 통해 형성된 다른 나노구조체와 달리 전기화학적 에칭 후 벽(Wall) 형태의 구조체가 형성되는 것이 아닌 로드(Rod) 형태의 나노구조체가 형성된다. In addition, the Si nanostructures formed according to the present invention, unlike other nanostructures formed through electrochemical etching of general Si, rod-shaped nanostructures in which wall-shaped structures are not formed after electrochemical etching. Is formed.

이상에서, 본 발명의 실시예를 구성하는 모든 구성 요소들이 하나로 결합되거나 결합되어 동작하는 것으로 설명되었다고 해서, 본 발명이 반드시 이러한 실시예에 한정되는 것은 아니다. 즉, 본 발명의 목적 범위 안에서라면, 그 모든 구성 요소들이 하나 이상으로 선택적으로 결합하여 동작할 수도 있다. In the above description, all elements constituting the embodiments of the present invention are described as being combined or operating in combination, but the present invention is not necessarily limited to the embodiments. In other words, within the scope of the present invention, all of the components may be selectively operated in combination with one or more.

또한, 이상에서 기재된 "포함하다", "구성하다" 또는 "가지다" 등의 용어는, 특별히 반대되는 기재가 없는 한, 해당 구성 요소가 내재될 수 있음을 의미하는 것이므로, 다른 구성 요소를 제외하는 것이 아니라 다른 구성 요소를 더 포함할 수 있는 것으로 해석되어야 한다. 기술적이거나 과학적인 용어를 포함한 모든 용어들은, 다르게 정의되지 않는 한, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가진다. 사전에 정의된 용어와 같이 일반적으로 사용되는 용어들은 관련 기술의 문맥상의 의미와 일치하는 것으로 해석되어야 하며, 본 발명에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다.In addition, the terms "comprise", "comprise" or "having" described above mean that the corresponding component may be included, unless otherwise stated, and thus excludes other components. It should be construed that it may further include other components instead. All terms, including technical and scientific terms, have the same meanings as commonly understood by one of ordinary skill in the art unless otherwise defined. Terms used generally, such as terms defined in a dictionary, should be interpreted to coincide with the contextual meaning of the related art, and shall not be interpreted in an ideal or excessively formal sense unless explicitly defined in the present invention.

이상의 설명은 본 발명의 기술 사상을 예시적으로 설명한 것에 불과한 것으로서, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자라면 본 발명의 본질적인 특성에서 벗어나지 않는 범위에서 다양한 수정 및 변형이 가능할 것이다. 따라서, 본 발명에 개시된 실시예들은 본 발명의 기술 사상을 한정하기 위한 것이 아니라 설명하기 위한 것이고, 이러한 실시예에 의하여 본 발명의 기술 사상의 범위가 한정되는 것은 아니다. 본 발명의 보호 범위는 아래의 청구범위에 의하여 해석되어야 하며, 그와 동등한 범위 내에 있는 모든 기술 사상은 본 발명의 권리범위에 포함되는 것으로 해석되어야 할 것이다.The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

도 1은 본 발명의 일 실시예에 따른 태양전지 소자의 단면도.1 is a cross-sectional view of a solar cell device according to an embodiment of the present invention.

도 2는 본 발명의 다른 실시예에 따른 태양전지 소자의 제조방법의 흐름도.2 is a flow chart of a method of manufacturing a solar cell device according to another embodiment of the present invention.

도 3은 본 발명의 일 실시예에 따른 태양전지 소자의 SEM 영상.3 is an SEM image of a solar cell device according to an embodiment of the present invention.

도 4는 다른 방법에 의해 제조된 태양전지 소자의 SEM 영상.4 is an SEM image of a solar cell device manufactured by another method.

도 5는 또다른 방법에 의해 제조된 태양전지 소자의 SEM 영상.5 is an SEM image of a solar cell device manufactured by another method.

Claims (8)

제1타입으로 도핑된 반도체 재료를 제공하는 단계와;Providing a semiconductor material doped with a first type; 상기 도핑된 반도체 재료 상에 제1전극을 형성하는 단계와;Forming a first electrode on the doped semiconductor material; 상기 반도체 재료의 표면에 에칭 용액에서 전기화학적 에칭에 의해 다수의 로드(rod)를 갖는 나노구조체를 형성하는 단계와;Forming a nanostructure having a plurality of rods by an electrochemical etching in an etching solution on a surface of the semiconductor material; 상기 에칭된 반도체 재료 상에 상기 반도체 재료와 다른 타입로 도핑된 레이어(layer)를 형성하는 단계와;Forming a layer doped on the etched semiconductor material, the layer being different from the semiconductor material; 상기 레이어 상에 제2전극을 형성하는 단계를 포함하는 태양전지 소자의 제조방법.Forming a second electrode on the layer method of manufacturing a solar cell device. 제 1 항에 있어서,The method of claim 1, 상기 에칭 용액은 HF:DMSO(Dimethyl Sulfoxide):H2O 조성을 갖는 것을 특징으로 하는 태양전지 소자의 제조방법.The etching solution is a manufacturing method of a solar cell device, characterized in that the HF: DMSO (Dimethyl Sulfoxide): H 2 O composition. 제 2 항에 있어서,The method of claim 2, 상기 에칭 용액 중 DMSO(Dimethyl Sulfoxide)과 H2O의 상대적인 조성비는 1~99%의 DMSO와 1~99%의 H2O인 것을 특징으로 하는 태양전지 소자의 제조방법.The relative composition ratio of DMSO (Dimethyl Sulfoxide) and H 2 O in the etching solution is 1 ~ 99% DMSO and 1 ~ 99% H 2 O characterized in that the manufacturing method of the solar cell device. 제 1 항에 있어서,The method of claim 1, 상기 반도체 재료는 p-도핑되고 상기 레이어는 n-도핑된 n-Si인 것을 특징으로 하는 태양전지 소자의 제조방법.Said semiconductor material is p-doped and said layer is n-doped n-Si. 제 4 항에 있어서,The method of claim 4, wherein 상기 n-Si와 상기 제2전극 사이에 Al 도핑된 ZnO 투명전도막을 형성하는 단계를 추가로 포함하는 태양전지 소자의 제조방법.And forming an Al-doped ZnO transparent conductive film between the n-Si and the second electrode. 제 1 항에 있어서,The method of claim 1, 상기 전기화학적 에칭시 1~100mA/cm2 의 전류밀도가 인가되는 것을 특징으로 하는 태양전지 소자의 제조방법.The method of manufacturing a solar cell device characterized in that the current density of 1 ~ 100mA / cm 2 is applied during the electrochemical etching. 제 1 항에 있어서,The method of claim 1, 상기 나노구조체의 로드들은 1nm~100um 의 지름을 갖는 것을 특징으로 하는 태양전지 소자의 제조방법. Rods of the nanostructures manufacturing method of a solar cell device, characterized in that having a diameter of 1nm ~ 100um. 제 1 항에 있어서,The method of claim 1, 상기 나노구조체의 로드들 사이 간격은 1nm~100um인 것을 특징으로 하는 태양전지 소자의 제조방법.The gap between the rods of the nanostructures is a method for manufacturing a solar cell device, characterized in that 1nm ~ 100um.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210376180A1 (en) * 2020-05-29 2021-12-02 Globalfoundries U.S. Inc. Photodiode and/or pin diode structures
US11424377B2 (en) 2020-10-08 2022-08-23 Globalfoundries U.S. Inc. Photodiode with integrated, light focusing element
US11611002B2 (en) * 2020-07-22 2023-03-21 Globalfoundries U.S. Inc. Photodiode and/or pin diode structures
US11949034B2 (en) 2022-06-24 2024-04-02 Globalfoundries U.S. Inc. Photodetector with dual doped semiconductor material

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210376180A1 (en) * 2020-05-29 2021-12-02 Globalfoundries U.S. Inc. Photodiode and/or pin diode structures
CN113745364A (en) * 2020-05-29 2021-12-03 格芯(美国)集成电路科技有限公司 Photodiode and/or PIN diode structure
US11316064B2 (en) * 2020-05-29 2022-04-26 Globalfoundries U.S. Inc. Photodiode and/or PIN diode structures
US11611002B2 (en) * 2020-07-22 2023-03-21 Globalfoundries U.S. Inc. Photodiode and/or pin diode structures
US11424377B2 (en) 2020-10-08 2022-08-23 Globalfoundries U.S. Inc. Photodiode with integrated, light focusing element
US11664470B2 (en) 2020-10-08 2023-05-30 Globalfoundries U.S. Inc. Photodiode with integrated, self-aligned light focusing element
US11949034B2 (en) 2022-06-24 2024-04-02 Globalfoundries U.S. Inc. Photodetector with dual doped semiconductor material

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