KR20100050847A

KR20100050847A - Resistive memory chip

Info

Publication number: KR20100050847A
Application number: KR1020080109945A
Authority: KR
Inventors: 김호정
Original assignee: 삼성전자주식회사
Priority date: 2008-11-06
Filing date: 2008-11-06
Publication date: 2010-05-14

Abstract

PURPOSE: A resistance memory chip is provided to share not only an address pin and data pin, but also a command pin and a control pin by physically including one memory access interface. CONSTITUTION: A first memory(100) comprises a first array(110) having a plurality of resistance memory cells. The resistance memory cells comprise a plurality of bit lines and a plurality of word lines. Each resistance memory cell is coupled with each bit line and each word line. A second memory(600) comprises a second array(610) having a plurality of resistance memory cells. The resistance memory cells comprise a plurality of bit lines and a plurality of word lines.

Description

Resistive memory chip

The present invention relates to a resistive memory chip, and more particularly, to a resistive memory chip having improved performance and reduced manufacturing cost.

Nonvolatile memory chips using a resistive material include a resistive memory chip (RRAM), a phase change random access memory (PRAM), and a magnetic memory chip (MRAM). Dynamic memory (DRAM) or flash memory devices use charge to store data, while nonvolatile memory devices using resistors are used for resistive change (RRAM) and chalcogenide alloys in variable resistors. Data is stored using a state change (PRAM) of a phase change material such as an alloy), a resistance change (MRAM) of a magnetic tunnel junction (MTJ) thin film according to a magnetization state of a ferromagnetic material, and the like.

Here, the resistive memory cell includes a variable resistance material between the upper electrode and the lower electrode, and has a characteristic that the resistance level of the variable resistance material changes according to voltages provided to the upper and lower electrodes. Examples of such a resistive memory cell are disclosed in US Patent Publication No. 2005-58009, US Patent Publication No. 2004-27849, and the like. In particular, a filament is formed in the variable resistance material to serve as a current path of the cell current, and the state in which the filament is partially broken is defined as a reset state, a high resistance state, and reset data (1 data). The filament connected state is defined as set state, low resistance state and set data (0 data).

Write reset data to a resistor memory cell by providing a reset voltage having a voltage level sufficient to break the filament, and write set data to a resistor memory cell by providing a set voltage having a voltage level that can connect the filament again. . In addition, a voltage having a voltage level low enough that the filament state does not change is provided to read whether the stored data is reset data or set data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a resistive memory chip having improved performance and reduced manufacturing cost.

The problem to be solved by the present invention is not limited to the above-mentioned problem, another task that is not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the resistive memory chip of the present invention for solving the above problems is a plurality of resistive memory cells in which a plurality of bit lines, a plurality of word lines and each resistive memory cell are coupled with each bit line and each word line. A first memory comprising a first array comprising: And a second array including a plurality of bit lines, a plurality of word lines, and a plurality of resistive memory cells coupled to each bit line and each word line, the second array having a different array size from the first array. And a second memory comprising an array.

Another aspect of the resistive memory chip of the present invention for solving the above problems includes a first array and a second array having a different array size from the first array. The resistive memory chip includes a memory interface in which a first interface that accesses the first array and a second interface that access the second array are physically integrated into one.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

1 is a block diagram illustrating a resistive memory chip according to example embodiments.

Referring to FIG. 1, the resistive memory chip 10 may include a storage memory 100 having a large array size, a random access memory 600 having a small array size, and a peripheral circuit area in one chip. 800).

The resistive memory chip 10 may include resistive memories 100 and 600 having different array sizes according to an application in one chip.

In the present invention, an array may be defined as a set of resistive memory cells that become a minimum operation unit. Here, the minimum operation unit may be a minimum unit that is activated to read data from a cell or write data to a cell. In this case, active means applying a voltage to a word line and a bit line. After activation, data may be read from or written to selected cells included in the array. Or an array is a set of cells that can be selected by either X-decoder 120 or 620 along with any one of the Y-decoders 130 or 630 that selects a resistive memory cell to be read / written with. can do. For example, in FIG. 1, the resistive memories 100 and 600 each include four arrays.

The memory 100 for storage may include a high density array 110, an X-decoder 120, a Y-decoder 130, a sense amplifier, and a write driver 200. The high density array 110 may store a large amount of user data due to a large array size. The storage memory 100 may be implemented in the form of, for example, a NAND flash memory.

The high density array 110 may have a memory capacity of 16Gbit, for example, as shown. For example, the high density array 110 may have a structure in which an array having 1 Gbit each is stacked in four layers, as shown. The high density array 110 has a large length of the bit line and the word line, and thus has a large time constant τ, which is calculated by multiplying the resistance value and the capacitance. Therefore, it operates at low speed and can be used for storage in which user data is stored.

Although not shown exactly in the figure, the high density array 110 includes a plurality of bit lines, a plurality of word lines, and a plurality of resistive memory cells, each resistive memory cell coupled with each of the bit lines and each word line. .

The resistive memory cell may include a variable resistance element having different resistance levels according to data, and an access element for controlling a cell current flowing through the variable resistance element. The variable resistance element may have a filament formed as a current path of the cell current inside. The reset data may be defined as a case where the filament is partially broken, and the set data may be defined as a case where the filament is connected. have. Such a variable resistance element may use, for example, a material such as NiO. In addition, the access element may be a FET transistor, a diode, a PNP bipolar transistor, an NPN bipolar transistor, or the like.

The X-decoder 120 and the Y-decoder 130 designate rows and columns of resistive memory cells, respectively, to select at least one or more resistive memory cells to be written / read out of a plurality of resistive memory cells.

The sense amplifier and write driver 200 perform write and read operations on the selected resistive memory cell. That is, the reset data is written to the resistive memory cell by providing a reset voltage having a voltage level enough to break the filament, and the set data is provided to the resistive memory cell by providing a set voltage having a voltage level sufficient to connect the filament again. Write. In addition, a voltage having a voltage level low enough that the filament state does not change is provided to read whether the stored data is reset data or set data. Here, the set voltage is higher than the reset voltage.

The random access memory 600 may include a high speed array 610, an X-decoder (not shown), a Y-decoder (not shown), a sense amplifier, and a write driver 600. The fast array 610 has a small array size and thus has fast access speed, and OS data and code data may be stored. The random access memory 600 may be implemented in the form of, for example, a NOR flash memory or a dynamic random access memory (DRAM).

The high speed array 610 may have a memory capacity of 16 Mbit, for example, as shown. Although not illustrated, the high speed array 610 may have a structure in which arrays each having 1 Mbit are stacked in four layers. The high speed array 610 has a short time constant τ because the length of the bit line and the word line is short. Therefore, because it can operate at high speed, it can be used to store OS data, code data, or cache memory.

The high speed array 610 may include a plurality of bit lines, a plurality of word lines, and a plurality of resistive memory cells. Since the dense array 110 is described in detail, the plurality of bit lines, the plurality of word lines, and the plurality of resistive memory cells described above are substantially the same, and a detailed description thereof will be omitted for convenience.

The X-decoder 620 and the Y-decoder 630, the sense amplifier and the write driver 700 included in the random access memory 600 include the X-decoder 120 and the Y-decoder of the memory 100 for storage. Since the 130 and the sense amplifier and the write driver 200 are substantially the same, detailed description thereof will be omitted for convenience.

The resistive memories 100 or 600 included in the resistive memory chip 10 described above with reference to FIG. 1 may include other memories (eg, DRAM, NAND flash memory, NOR flash memory, and phase change memory). Alternatively, the access speed can be controlled by adjusting the size of the array relatively freely.

Specifically, a DRAM will be described in detail. In the DRAM, a refresh operation is essential. The refresh operation is described below. Each memory cell of a DRAM is composed of one switching transistor and one information storage capacitor. The DRAM also includes a sense amplifier consisting of a pair of bit lines and bit bar lines. When the refresh command is input to the DRAM, the selected word line is boosted to turn on the switching transistor. Then, the data stored in the information storage capacitor is moved to the bit line or bit bar line. At this point, the potential difference between the bit line and the bitbar line is small, but the slight difference is sensed by the sense amplifier and amplified by information of '1' or '0', respectively. After amplification, when the word line is pushed down and the switching transistor is turned off, the information in the memory cell is preserved as amplified data. However, as the array size of the DRAM increases, the bit line may become longer and the capacitance of the bit line may increase. If the capacitance of this bit line is too large, the noise for the potential difference that the sense amplifier senses can be large. Therefore, in the case of DRAM, there is a limitation as described above for adjusting the array size.

Unlike these, the resistive memory 100 or 600 may operate at a low speed when the array size is increased, but may implement a storage memory 100 capable of storing a large amount of data, and may operate at a high speed when the array size is reduced. Random access memory 600 may be implemented. In this way, by adjusting the array size of the resistive memory (100 or 600) to include the storage memory 100 and the random access memory 600 in a single chip at the same time, reducing the manufacturing cost, high performance and simple memory structure The resistive memory chip 10 may be implemented.

In the peripheral circuit area 800, the X-decoder 120 (see 620 of FIG. 2), the Y-decoder 130 (see 630 of FIG. 2), the sense amplifier and the light driver 200, 600, etc. are operated. A plurality of logic circuit blocks and voltage generators are disposed.

FIG. 2 is a block diagram illustrating the high speed array of FIG. 1 included in the resistive memory chip according to the first exemplary embodiment of the present invention. 2 illustrates an X-decoder 620 and a Y-decoder 630 which are not shown in FIG. 1.

Referring to FIG. 2, the random access memory 600 includes four high speed arrays 610 arranged in a 2 × 2 matrix, and a sense amplifier and a write driver 700 are disposed at the bottom of the second row of the matrix. have.

According to the structure shown in FIG. 2, for example, a global bit line (not shown) may be provided to reduce the number of cells of the sense amplifier and write driver 700 required. Therefore, the size of the resistive memory chip 10 may be reduced by reducing the area occupied by the sense amplifier and the write driver 700.

3 is a block diagram illustrating the high speed array of FIG. 1 included in a resistive memory chip according to a second exemplary embodiment of the present invention. 3 illustrates an X-decoder 620 and a Y-decoder 630 which are not shown in FIG. 1.

Referring to FIG. 3, the random access memory 601 includes four high speed arrays 610 arranged in a 2 × 2 matrix, and the sense amplifier and write driver 700 of the first row and the second row of the matrix are described. It is arranged in between.

According to the structure shown in FIG. 3, compared to the structure shown in FIG. 2, since the sense amplifier and the write driver 700 are close to each of the high speed arrays 610, the distance from the resistive memory cell to read data is shortened. The smaller load allows for faster data sensing.

In a resistive memory chip according to example embodiments, different sensing schemes may be used according to each resistive memory. 4 to 14, different sensing schemes are used according to each resistance memory.

Fig. 4 is a circuit diagram showing one cell of a read sense amplifier and a write driver used in a storage memory.

The read sense amplifier and write driver 200 used for the memory for storage should be able to read / write a large number of data at a time.

If the high density array has a memory capacity of, for example, 16Gbit, the read sense amplifier and write driver used for the memory for storage need cells of 4Kbyte to 16Kbyte, so the size of each cell must be made small.

Referring to FIG. 4, the read sense amplifier and the write driver 200 are integrated into each cell. When the two interposers shown in FIG. 4 are composed of one nMOS and one pMOS, 16 cells may be used to implement each cell of the read sense amplifier and the write driver 200. Accordingly, each cell of the read sense amplifier and the write driver (see 700 of FIG. 11) used in the random access memory to be described later can be implemented in a smaller size compared to that of 20 MOSFETs.

5 to 7, the write method in the read sense amplifier and the write driver 200 shown in FIG. 4 will be described. 5 to 7 are circuit diagrams for describing a write method of the read sense amplifier and the write driver illustrated in FIG. 4. In FIG. 5, a plurality of bit lines BL, unselected word lines UnSel. WL, selected word lines Sel. WL, and a plurality of resistive memory cells RMC are illustrated. An example of a resistor and a diode connected in series is shown to represent a variable resistance element and an access element included in each resistive memory cell RMC.

First, referring to FIG. 5, an address for writing data is set up, the transistor Den is turned on, and the data is stored in a latch through the transistor DI / transistor nDI (Data Loading). .

Subsequently, referring to FIG. 6, the word line WL and the bit line BL are precharged (BL precharge). The voltage Vpp may be applied to the gate of the transistor BLSi, and each word line WL may be a ground voltage (for example, 0V) by the charge path illustrated in FIG. 6.

Subsequently, referring to FIG. 7, zero or one data is written by adjusting a voltage applied to the gate of the transistor SET / transistor RESET and a current flowing through the drain / source of the transistor SET / transistor RESET. (WL Enable). At this time, the voltage of the selected word line (Sel. WL) may be Vwrite.

Subsequently, the write process is terminated through a recovery period.

Meanwhile, the read sense amplifier and the write driver 200 shown in FIG. 4 may perform voltage sensing using a coupling ratio at the time of reading. 8 to 10, a read method in the read sense amplifier and the write driver 200 illustrated in FIG. 4 will be described in detail. 8 through 10 are circuit diagrams for describing a read method of the read sense amplifier and the write driver illustrated in FIG. 4.

First, referring to FIG. 8, the transistor Den is turned on and a latch is reset through the transistor nDI. At the same time, the bit line is discharged through the transistor DIS.

9, the word line is enabled (WL Enable), and the bit line connected to the resistive memory cell to read data is developed. At this time, the voltage of the selected word line Sel. WL may be Vread.

Next, referring to FIG. 10, sensing and data latching are performed. A transistor connected in series with the transistor BLSi, the transistor LCH and the transistor LCH is turned on, and a closed loop shown by an arrow in FIG. 10 is formed to form a bit line connected with a resistive memory cell to read data. The voltage level is sensed and can also latch data.

This completes the read process.

Fig. 11 is a circuit diagram showing one cell of a read sense amplifier and a write driver used in the random access memory.

The read sense amplifier and write driver 700 used in the random access memory should be able to read data at high speed.

When the high speed array has a memory capacity of, for example, 16 Mbit, the read sense amplifier and write driver 700 used for the random access memory needs a cell corresponding to 16 to 128 bytes.

Referring to FIG. 11, unlike in FIG. 4, the read sense amplifier 710 and the write driver 720 are separated in each cell. Assuming that two inverters shown in FIG. 11 each consist of one nMOS and one pMOS, 20 cells may be used to implement each cell of the read sense amplifier 710 and the write driver 720.

Since the write method of the write driver 720 is substantially the same as the write method of the read sense amplifier and the write driver 200 described with reference to FIGS. 5 to 7, a detailed description thereof will be omitted for convenience.

The read sense amplifier 710 illustrated in FIG. 11 may perform current sensing at the time of reading. 12 to 14, a read method of the read sense amplifier 710 illustrated in FIG. 11 will be described in detail. 12 to 14 are circuit diagrams for describing a read method of the read sense amplifier illustrated in FIG. 11.

First, referring to FIG. 12, an address for reading data is set up, and a bit line is discharged through a transistor DIS (BL Discharge).

13, the word line is enabled (WL Enable). At this time, the voltage of the selected word line Sel. WL may be Vread.

14, the bit line BL is set up (BL Set-up) and data is output through the comparator (Data Out).

In more detail, a constant current may flow in a transistor Vbias in which a constant bias voltage is applied to the gate and a transistor connected in series with the drain and the gate. In addition, a variable current may flow in the transistor REN to which the read enable signal is applied to the gate and the transistor connected in series. The magnitude of the variable current depends on the resistance level of the resistive memory cell to be read, resulting in the magnitude of the voltage applied to the plus terminal of the comparator. The comparator may output a logic high or logic low value to the output terminal Dout of the comparator by comparing the magnitude of the voltage applied to the plus terminal and the reference voltage ref applied to the minus terminal.

This completes the read process.

According to the current sensing, data can be read at a higher speed than in the case of voltage sensing. This is because voltage sensing does not require the required developer time. Therefore, such a current sensing can improve the data rate in the random access memory.

Referring to FIG. 15, a memory interface of a resistive memory chip according to an exemplary embodiment will be described. 15 is a block diagram illustrating a memory interface of a resistive memory chip according to an exemplary embodiment of the present invention.

In the resistive memory chip 10 according to an exemplary embodiment, a storage access interface for accessing a memory for storage and a random access interface for accessing a random access memory are physically integrated. An access interface of may be used.

Referring to FIG. 15, it may be configured to physically include one memory access interface (Memory I / F), but logically operate as if it includes two memory access interfaces. Specifically, the access mode may be switched by providing a mode selection signal to control data latency and data access speed of the mode controller 500.

Alternatively, you can switch the access mode by changing the pin map. For example, if the mode selection signal is logical 0, it has a pin map of the storage access interface, and if the logic 1, it has a pin map of a random access interface. Can be. In this manner, the host 20 may operate as a storage access interface when accessing the high density core 110 and as a random access interface when accessing the high speed core 610. have.

By physically including only one memory access interface (Memory I / F), not only the address pin and the data pin can be shared, but also the command pin and the control pin can be shared, thereby reducing manufacturing costs.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

FIG. 2 is a block diagram illustrating the high speed array of FIG. 1 included in the resistive memory chip according to the first exemplary embodiment of the present invention.

3 is a block diagram illustrating the high speed array of FIG. 1 included in a resistive memory chip according to a second exemplary embodiment of the present invention.

5 to 7 are circuit diagrams for describing a write method of the read sense amplifier and the write driver illustrated in FIG. 4.

8 through 10 are circuit diagrams for describing a read method of the read sense amplifier and the write driver illustrated in FIG. 4.

12 to 14 are circuit diagrams for describing a read method of the read sense amplifier illustrated in FIG. 11.

15 is a block diagram illustrating a memory interface of a resistive memory chip according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: resistive memory chip 20: host

100: memory for storage 110: high density array

120: X-decoder 130: Y-decoder

200: sense amplifier and light driver

500: mode controller 600: random access memory

800: peripheral circuit area

Claims

A first memory including a first array comprising a plurality of bit lines, a plurality of word lines, and each resistive memory cell comprising a plurality of resistive memory cells coupled with each of the bit lines and each word line; And

A second array comprising a plurality of bit lines, a plurality of word lines, and a plurality of resistive memory cells coupled to each of the bit lines and each word line, wherein the second array has a different array size. A resistive memory chip comprising a second memory that includes.

According to claim 1,

Wherein each array is a set of cells that are the smallest unit that is active for reading data from or writing data to a resistive memory cell.

According to claim 1,

The first and second memories further comprise an X-decoder and a Y-decoder for specifying rows and columns of the resistive memory cell to be read or written, respectively,

Wherein each array is a collection of cells that can be selected by the X-decoder and the Y-decoder.

According to claim 1,

And the first array is a high density array and the second array is a high speed array having a smaller array size than the first array.

According to claim 1,

Read data from the first array using voltage sensing;

A resistive memory chip that reads data from the second array using current sensing.

According to claim 1,

The first memory includes a plurality of read amplifiers and write driver cells in which each read amplifier and write driver cell are integrated with a read sense amplifier and a write driver.

The second memory is a resistive memory chip comprising a plurality of read amplifiers and write driver cells in which each read amplifier and write driver cell are separated into a read sense amplifier and a write driver.

A first array and a second array having a different array size from the first array,

And a memory interface in which a first interface accessing the first array and a second interface accessing the second array are physically integrated into one.

The method of claim 7, wherein

And a mode controller in which data latency and data access speed are controlled according to the mode selection signal.

The method of claim 7, wherein

The resistive memory chip changes the pin map of the memory interface to switch to the first interface or the second interface according to a mode selection signal.

The method of claim 7, wherein

And a resistive memory chip that shares an address pin, a data pin, a command pin, and a control pin used for the first interface and the second interface.