KR20100050471A

KR20100050471A - Intelligent control of program pulse duration

Info

Publication number: KR20100050471A
Application number: KR1020107001506A
Authority: KR
Inventors: 준 완; 유핀 퐁
Original assignee: 샌디스크 코포레이션
Priority date: 2007-06-21
Filing date: 2008-06-18
Publication date: 2010-05-13
Also published as: CN101779250A; WO2008157606A1; CN101779250B; TW200907976A; EP2160735A4; TWI378457B; JP2010530596A; EP2160735A1

Abstract

To program the set of nonvolatile storage elements, a set of programming pulses is applied to the control gate (or other terminal) of the nonvolatile storage elements. The programming pulses have a constant pulse width and increasing magnitude until the maximum voltage is reached. At that point, the increase in the magnitude of the programming pulses stops, and the programming pulses are applied in a manner that provides a change in the duration of the programming signal between verify operations. In one embodiment, for example, after the pulses reach their maximum magnitude, the pulse width increases. In another embodiment, after the pulses have reached their maximum magnitude, a plurality of program pulses are applied between the verify operations.

Description

INTELLIGENT CONTROL OF PROGRAM PULSE DURATION}

The present invention relates to nonvolatile storage technology.

Semiconductor memory is becoming more and more widely used in various electronic devices. For example, non-volatile semiconductor memory may include cellular telephones, digital cameras, personal digital assistants (PDAs), mobile computing devices, and non-mobile computing devices. mobile computing devices) and other devices. Electronic Erasable Programmable Read Only Memory (EEPROM) and flash memory are one of the most widely used nonvolatile semiconductor memories.

Both the EEPROM and the flash memory are located on top of the channel region in the semiconductor substrate and use a floating gate insulated from the channel region. The floating gate is located between the source region and the drain region. A control gate is provided over the floating gate and is insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on and conduction between the source and drain occurs is controlled by the level of charge on the floating gate. Thus, the memory cell (which may include one or more transistors) may be programmed and / or erased by changing the level of charge on the floating gate to change the threshold voltage.

Each memory cell can store data (analog or digital). When storing one bit of digital data (called a binary memory cell), the possible threshold voltages of the memory cell are divided into two ranges assigned to logic data " 1 " and " 0 ". In one example of a NAND type flash memory, the threshold voltage after the memory cell is erased is negative and is defined as logic " 1. " After programming, the threshold voltage is positive and defined as logic "0". When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell is turned on to indicate that logic 1 is stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell is not turned on, indicating that logic 0 is stored.

Memory cells may also store multiple levels of information (called multi-state memory cells). In the case of storing multiple levels of data, the range of possible threshold voltages is divided by the number of data levels. For example, if four levels of information are stored, there may be four threshold voltage ranges assigned to the data values "11", "10", "01" and "00". As an example of a NAND type memory, the threshold voltage after the erase operation is negative and is defined as "11". Positive threshold voltages are used for the states of "10", "01" and "00". If eight levels of information (or state) are stored in each memory cell (e.g., for three bits of data), the data values "000", "001", "010", "011", There may be eight threshold voltage ranges assigned to "100", "101", "110" and "111". The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the memory cell depends on the data encoding scheme adopted for the memory cells. For example, US Pat. No. 6,222,762 and US Patent Application Publication No. 2004/0255090 describe various data encoding schemes for multi-state flash memory cells, which are incorporated herein by reference in their entirety. Included. In one embodiment, data values are assigned to threshold voltage ranges using Gray code assignment, and if one of the floating gate's threshold voltages incorrectly shifts to a neighboring physical state, only one bit is affected. Receive. In some embodiments, the data encoding scheme may be changed for other word-lines, or the data encoding scheme may change over time, or data bits for arbitrary word lines may be It may be inverted to reduce even wear and data pattern sensitivity on the memory cell. Different encoding schemes can be used.

When programming a flash memory device, such as an EEPROM, or a NAND flash memory device, a program voltage is generally applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate is negatively charged and the threshold voltage of the memory cell is raised, leaving the memory cell in a programmed state. For more information on programming, see US Pat. No. 6,859,397, entitled "Source Side Self Boosting Technique For Non-Volatile Memory," and US Patent Application Publication No. 2005/0024939, entitled "Detecting Over Programmed Memory." "), All of which are incorporated herein by reference in their entirety.

In general, the program voltage applied to the control gate during a program operation is applied in a series of pulses. In many embodiments, the magnitude of the pulses increases to a predetermined step size in the form of each successive pulse.

Because multi-state memory cells have multiple ranges of possible threshold voltages, some memory cells need to be programmed to higher threshold voltages as compared to binary memory cells. Larger magnitude programming pulses are needed to program the memory cells to higher threshold voltages. Additionally, as techniques for more sophisticated structures are applied, it can be more difficult to maintain the same cell coupling ratio, which results in larger voltages for the programming pulses to achieve the same programming effect. It is necessary. However, the voltage of the programming pulses is limited by practical constraints in the design of the charge pump on the memory chip, and by several factors including junction and oxide breakdown.

Thus, higher voltage programming pulses are needed, but there is a limit to the maximum voltage achievable.

The technique signed herein relates to an intelligent way to control the duration of program pulses applied to the memory cell (s). For example, if there are memory cells in which the programming signal has reached its maximum voltage but still has not terminated programming, controlling the duration of program pulses applied to the memory cell (s) to ensure effective programming continues. Intelligent methods can be used. One example of an intelligent way to control the duration of program pulses applied to the memory cell (s) includes using wider program pulses. Another example uses a plurality of consecutive program pulses between verification operations. Other intelligent ways to control the duration of program pulses can also be used. In addition, an intelligent scheme for controlling the duration of program pulses can also be used in situations other than the previously signed situation.

One embodiment includes applying a programming signal to a nonvolatile storage element. Applying the program signal includes applying programming pulses having a constant pulse width to the non-volatile storage device prior to one or more pulses reaching a maximum magnitude, and one or more pulses reaching a maximum magnitude. Thereafter thereafter applying one or more programming pulses to the non-volatile storage element that provide a change in the duration of the programming signal between verify operations.

One embodiment includes applying a programming signal to a plurality of nonvolatile storage elements as a set of pulses, and performing one or more verify operations to determine whether the nonvolatile storage elements are properly programmed. Applying a programming signal to the plurality of nonvolatile storage elements as the set of pulses applies pulses with increasing duration and constant magnitudes between verify operations before one or more pulses reach their maximum magnitude. It includes. Also, applying a programming signal to a plurality of nonvolatile storage elements as the set of pulses includes changing the duration of the programming signal between verify operations after one or more pulses have reached the maximum magnitude. do.

One embodiment includes applying programming pulses to the nonvolatile storage device having increasing magnitude and constant pulse width until one or more pulses reach their maximum magnitude. This procedure also includes applying programming pulses with increasing pulse widths to the nonvolatile storage element after one or more pulses have reached the maximum magnitude.

One embodiment includes applying programming pulses to the nonvolatile storage device having increasing magnitude and constant pulse width until one or more pulses reach their maximum magnitude. This procedure also includes applying one or more groups of different numbers of programming pulses to the nonvolatile storage element after one or more pulses have reached the maximum magnitude. Each group is applied between verify operations.

Some example embodiments include a plurality of nonvolatile storage elements and one or more management circuits in communication with the nonvolatile storage elements. The one or more management circuits perform the procedures described herein.

1 is a top view of a NAND string.
2 is an equivalent circuit diagram of the NAND string.
3 is a block diagram of a nonvolatile memory system.
4 is a block diagram illustrating an embodiment of a memory array.
5 is a block diagram illustrating an embodiment of a sense block.
6 shows an exemplary set of threshold voltage distributions and shows a procedure for programming a nonvolatile memory.
7A-7I illustrate various threshold voltage distributions and illustrate a procedure for programming a nonvolatile memory.
8 is a table illustrating an example of a procedure of programming a nonvolatile memory.
9 is a flow chart describing one embodiment of a procedure for programming a nonvolatile memory.
10 is a flow chart describing one embodiment of a procedure for programming nonvolatile memory elements.
11A is a flow diagram illustrating one embodiment of a procedure for increasing the duration of a program voltage.
11B is a flow chart describing one embodiment of a procedure for increasing the duration of a program voltage.
11C is a flow chart describing one embodiment of a procedure for increasing the duration of a program voltage.
12 and 13 show exemplary waveforms.
14 is a table providing data for an exemplary programming signal.
15 and 16 show exemplary waveforms.

One example of a flash memory system uses a NAND structure, which includes arranging a plurality of transistors in series between two select gates. Transistors and select gates connected in series are referred to as a NAND string. 1 is a top view of one NAND string. 2 is an equivalent circuit thereof. The NAND string shown in FIGS. 1 and 2 includes four transistors 100, 102 connected in series between a first (or drain side) select gate 120 and a second (or source side) select gate 122. , 104 and 106). The select gate 120 connects the NAND string to the bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. The select gate 122 is controlled by applying an appropriate voltage to the select line SGD. The select gate 122 is controlled by applying an appropriate voltage to the select line SGS. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. For example, transistor 100 has a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes control gate 106CG and floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG ) Is connected to the word line WL0.

Note that while FIGS. 1 and 2 show four memory cells within a NAND string, the use of four memory cells is provided only as an example. The NAND string may have fewer than four memory cells, or may have more than four memory cells. For example, some NAND strings may include 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, and the like. The description herein is not limited to any particular number of memory cells in the NAND string.

A typical architecture for a flash memory system that uses a NAND structure includes several NAND strings. Each NAND string is connected to a source line by a source select gate controlled by a select line SGS and to an associated bit line by a drain select gate controlled by a select line SGS. Each bit line and the respective NAND string (s) connected to the bit line via bit line contacts constitute columns of an array of memory cells. Bit lines are shared with a plurality of NAND strings. In general, the bit lines are arranged in a direction perpendicular to the word lines on top of the NAND strings and are connected to one or more sense amplifiers.

Related examples of NAND type flash memories and their operation are provided in the following US patent / patent application, all of which are incorporated herein by reference. US Patent No. 5,570,315, US Patent No. 5,774,397, US Patent No. 6,046,935, US Patent No. 6,456,528, and US Patent Publication No. US2003 / 0002348. The description herein may also apply to other types of flash memory and other types of nonvolatile memory in addition to NAND.

In addition to NAND flash memory, other types of nonvolatile storage devices may also be used. For example, a so-called TANOS structure (TaN-Al ₂ O ₃ -SiN-SiO ₂ on a silicon substrate), which is basically a memory cell that uses trapping of charge in a nitride layer (instead of a floating gate) Consisting of laminated layers) can also be used with the present invention. Another memory cell is published in the paper (Chan et al., Titled "A True Single- Transistor Oxide-Nitride-Oxide EEPROM Device", IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93- 95). A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between the conductive control gate and the semiconductive substrate over the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a confined region. This stored charge changes the threshold voltage of a portion of the channel of the cell in a detectable manner. The cell is erased by injecting hot holes into nitride. In addition, the article (author: Nozaki et al., Title: "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application", IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497 -501, which describes a similar cell in a split-gate configuration, wherein the doped polysilicon gate extends over a portion of the memory cell channel to separate select transistors. select transistor). The above two articles are hereby incorporated by reference in their entirety. The programming techniques described in the paragraph (title: section 1.2 of "Nonvolatile Semiconductor Memory Technology", author: William D. Brown and Joe E. Brewer, IEEE Press, 1998) (which are also incorporated herein by reference) are also genetic It is described as applicable to the charge-trapping devices of. Other types of memory devices may also be used.

3 shows a memory device 210 having read / write circuits for reading and programming a page of memory cells (eg, NAND multi-state flash memory) in parallel. Memory device 210 may include one or more memory die or chips 212. Memory die 212 includes an array of memory cells 200 (two-dimensional or three-dimensional), control circuit 220, and read / write circuits 230A and 230B. In one embodiment, access to the memory array 200 by various peripheral circuits is implemented symmetrically on opposite sides of the array, reducing the density of each of the opposite access lines and circuits in half. Read / write circuits 230A and 230B include a plurality of sense blocks 300 that allow a page of memory cells to be read or programmed in parallel. The memory array 200 is addressable by word lines via row decoders 240A and 240B, and by bit lines through column decoders 242A and 242B. )Do. In a typical embodiment, the controller 244 is included as one or more memory die 212 in the same memory device 210 (eg, removable storage card or package). Commands and data are transmitted between the host and the controller 244 via lines 232, and between the controller and one or more memory die 212 via lines 234.

The control circuit 220 operates in cooperation with the read / write circuits 230A and 230B to perform a memory operation on the memory array 200. The control circuit 220 includes a state machine 222, an on-chip address decoder 224, and a power control module 226. State machine 222 provides chip-level control of memory operations. On-chip address decoder 224 provides an address interface between addresses used by the host or memory controller for hardware addresses used by decoders 240A, 240B, 242A, and 242B. The power control module 226 controls the power and voltage provided to the word line and the bit line during memory operation. In one embodiment, the power control module 226 includes one or more charge pumps capable of generating a voltage greater than the supply voltage.

In one embodiment, control circuit 220, power control circuit 226, decoder circuit 224, state machine circuit 222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A, decoder One or any combination of circuitry 240B, read / write circuits 230A, read / write circuits 230B and / or controller 244 may be referred to as one or more managing circuits. . One or more management circuits perform the procedures described herein.

4 illustrates an exemplary structure of the memory cell array 200. In one embodiment, the array of memory cells is divided into a large number of blocks of memory cells (eg, blocks 0-1023, or other amount). As is common in flash EEPROM systems, a block is a unit of erase. That is, each block contains the minimum number of memory cells that are erased together.

The block includes a set of NAND strings accessed through bit lines (eg, bit lines BL0-BL69623) and word lines WL0, WL1, WL2 and WL3. 4 shows four memory cells connected in series to form a NAND string. Although four cells are shown as contained within each NAND string, more or less than four may be used (e.g., 16, 32, 64, 128 or other numbers of memory cells on the NAND string). May be present). One terminal of the NAND string is connected to the corresponding bit line through the drain select gate (connected to the select gate drain line (SGD)), and the other terminal is connected through the source select gate (connected to the select gate source line (SGS)). Is connected to the source line.

In yet another embodiment, the bit lines are divided into odd bit lines and even bit lines. In odd / even bit line architectures, memory cells along a common word line and connected to odd bit lines are programmed at any time, while along a common word line and at even bit lines. The connected memory cells are programmed at another time.

Each block is usually divided into several pages. In one embodiment, a page is a unit of programming. One or more pages of data are generally stored within one row of memory cells. For example, one or more pages of data may be stored in memory cells connected to a common word line. A page can store one or more sectors. A sector includes user data and overhead data (which is also called system data). In general, the overhead data includes an error correction code (ECC) and header information calculated from user data of a sector. The controller (or other component) calculates the ECC when data is being programmed into the array and checks the ECC when the data is being read from the array. Alternatively, ECCs and / or other overhead data are stored in pages, or other blocks, different from the user data to which they belong. The sector of user data is typically 512 bytes, which corresponds to the size of the sector in the magnetic disk drive. Multiple pages (from approximately eight pages, for example up to 32, 64, 128, or more pages) form a block. Different sized blocks, pages and sectors may also be used.

5 is a block diagram of individual sensing blocks 300 partitioned into a core portion and a common portion 490, referred to as sensing module 480. In one embodiment, there may be a separate sense module 480 for each bit line, and one common portion 490 for a set of multiple sense modules 480. In one example, the sense block can include one common portion 490 and eight sense modules 480. Each of the sense modules in the group may communicate with an associated common portion via a data bus 472. For further details, see US Patent Application Publication No. 2006/0140007, which is also incorporated herein by reference in its entirety.

The sense module 480 includes a sense circuit 470, which determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. In some embodiments, sense module 480 includes circuitry commonly referred to as sense amplifiers. The sense module 480 also includes a bit line latch 482 that is used to set the voltage state on the connected bit line. For example, a predetermined state latched in bit line latch 482 may cause the connected bit line to indicate a program inhibit (eg, Vdd).

Common portion 490 includes a processor 492, a set of data latches 494, and an I / O interface 496 coupled between the set of data latches 494 and the data bus 420. Processor 492 performs computing operations. For example, one of its functions is to determine the data stored in the sensed memory cell, and to store the determined data in a set of data latches. The set of data latches 494 is used to store data bits determined by the processor 492 during a read operation. This is also used to store data bits that are obtained from the data bus 420 during program operation. The obtained data bits represent write data to be programmed into the memory. I / O interface 496 provides an interface between data latches 494 and data bus 420.

During reading or sensing, the operation of the system is under the control of the state machine 222, which is configured to supply different control gate voltages to the addressed memory cell (s) (power control 226). Control). As it proceeds through various predefined control gate voltages corresponding to the various memory states supported by the memory, the sensing module 480 may trip at one of these voltages and the output may be sensed. From module 480 is provided to processor 492 via bus 472. The processor 492 then determines the final memory state, taking into account tripping events of the sense module and information regarding the applied control gate voltage from the state machine through the input lines 493. do. The binary encoding for the memory state is then calculated and the last data bit stored in data latches 494. In another embodiment of the core portion, bit line latch 482 can perform two tasks, one as a latch to latch the output of sense module 480 and the other as described above. It is a mission as a line latch.

As expected, some embodiments may include a plurality of processors 492. In one embodiment, each processor 492 will include the output line such that each of the output lines (not shown in FIG. 5) are wired-OR to each other. In some embodiments, the output lines are inverted prior to being connected to the wired-OR line. This configuration allows for a quick decision during the program verification procedure when the programming procedure is completed, because the state machine accepting the wired-OR line can determine when all the bits being programmed have reached the required level. Because. For example, when each bit reaches its required level, logic 0 for that bit is sent to the wired-OR line (or data 1 is inverted). If all bits output data 0 (or data 1 is inverted), the state machine knows the end of the programming procedure. In an embodiment where each processor communicates with eight sense modules, the state machine may need to read the wired-OR line eight times (in some embodiments), or logic may accumulate the results of the bit lines. In addition to the processor 492, the state machine may only need to read the wired-OR line once.

The data latch stack 494 includes a stack of data latches corresponding to the sense module. In one embodiment, there are three (or four, or other) data latches per sense module 480. In one embodiment, the latches are each one bit.

During program or verification, the data to be programmed is stored in the set of data latches 494 from the data bus 420. During the verification procedure, the processor 492 monitors the verified memory state in comparison with the requested memory state. If both match, processor 492 sets bit line latch 482 such that the bit line indicates a program prohibition. This prevents further programming of the cell connected to the bit line even if the cell connected to the bit line is subjected to a programming pulse on the control gate. In another embodiment, the processor initially loads bit line latch 482, which sense circuit sets to an inhibit value during the verification procedure.

In some embodiments (but not necessarily), the data latches are implemented as a shift register such that parallel data stored therein is converted to serial data for the data bus 420 and vice versa. It is possible. In one preferred embodiment, all data latches corresponding to the read / write block of memory cells are linked together to form a block shift register such that a block of data can be input or output by serial transfer. Can be In particular, the bank of read / write modules is configured such that each set of data latches sequentially shifts data to or from the data bus as if they were one minute of the shift register for the entire read / write block.

For further information on sensing operations and sense amplifiers, see (1) US Patent Application Publication No. 2004/0057287, entitled "Non-Volatile Memory And Method With Reduced Source Line Bias Errors", March 25, 2004. Published), (2) US Patent Application Publication No. 2004/0109357, entitled "Non-Volatile Memory And Method with Improved Sensing," published 10 June 2004, (3) US Patent Application Publication No. 2005/0169082, (4) US Patent Publication No. 2006/0221692, entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory", inventor: Jian Chen, filed Apr. 2005, 2005, and (5) US patent application Ser. No. 11 / 321,953, entitled "Reference Sense Amplifier For Non-Volatile Memory", inventors: Siu Lung Chan and Raul-Adrian Cernea, filed Dec. 28, 2005. The five patent documents listed above are hereby incorporated by reference in their entirety.

At the end of a successful programming procedure (with verification), where appropriate, the threshold voltages of the memory cells must be within one or more distributions of threshold voltages for programmed memory cells or within the distribution of threshold voltages for erased memory cells. . 6 shows an example threshold voltage distribution (or data state) for a memory cell array when each memory cell stores three bits of data. However, other embodiments may use more or less than 3 bits of data per memory cell (eg, 4 bits of data or more than 4 bits of data per memory cell).

In the example of FIG. 6, each of the memory cells stores three bits of data, and thus there are eight valid data states S0-S7. In one embodiment, data state S0 is below zero volts and data states S1-S7 are above zero volts. In another embodiment, all eight data states are above zero volts, or other arrangements may be configured. In one embodiment, the threshold voltage distribution SO is wider than the distribution S1-S7 distribution.

Each data state corresponds to an eigenvalue for three bits stored in a memory cell. In one embodiment, S0 = 111, S1 = 110, S2 = 101, S3 = 100, S4 = 011, S5 = 010, S6 = 001 and S7 = 000. Other mappings of data to states S0-S7 can also be used. In one embodiment, the bits of all data stored in the memory cell are stored in the same logic page. In another embodiment, each bit of data stored in a memory cell corresponds to a different page. Thus, memory cells that store three bits of data will contain data in the first page, second page, and third page. In some embodiments, all of the memory cells connected to the same word line may store data in the same three data pages. In some embodiments, memory cells connected to a word line may be grouped in different sets of pages (eg, by odd and even bit lines).

In some conventional devices, memory cells may be erased in state SO. From state SO, the memory cells can be programmed to any of states S1-S7. In one embodiment, known as full sequence programming, memory cells may be programmed directly from the erase state SO to any of the programming states S1-S7. For example, a group of memory cells to be programmed may be erased first, so that all memory cells in that group are in an erased state SO. Some memory cells are programmed from state S0 to state S1, while other memory cells from state S0 to state S2, from state S0 to state S3, and state S0 to state S0. From S4, from state S0 to state S5, from state S0 to state S6, and from state S0 to state S7. Full sequence programming is schematically illustrated with the seven bent arrows of FIG. 6.

7A-7I disclose another procedure for programming a non-volatile memory, which, for any particular memory cell, writes adjacent memory cells for previous pages after that write for that particular page. By writing to a particular memory cell, the effect of floating gate to floating gate coupling is reduced. 7A-7I is a three step programming procedure. Prior to the first step, the memory cells are erased and are in the erase threshold distribution of state SO.

In the procedures of Figures 7A-7I, each memory cell stores three bits of data, and each bit is assumed to be in a different page. The first bit of data (the leftmost bit) is associated with the first page. The middle bit is associated with the second page. The rightmost bit is associated with the third page. The correlation between data and data states is S0 = 111, S1 = 110, S2 = 101, S3 = 100, S4 = 011, S5 = 010, S6 = 001 and S7 = 000. However, other embodiments may use other data encoding schemes.

When programming the first page (as described in FIG. 7A), if the bit should be data “1”, the memory cell remains in state SO (threshold voltage distribution 502). If the bit should be data "0", then the memory cell is programmed to state S4 (threshold voltage distribution 504). After adjacent memory cells are programmed, capacitive coupling between adjacent floating gates can cause the width of state S4 to be widened, as shown in FIG. 7B. The width of the state SO can also be widened, but there is enough margin between S0 and S1 to ignore the effect. More information regarding capacitive coupling between adjacent floating gates can be found in US Pat. No. 5,867,429 and US Pat. No. 6,657,891, all of which are incorporated herein by reference in their entirety.

When programming the second page (see FIG. 7C), if the memory cell is in state S0 and the second page bit is data "1", the memory cell remains in state S0. In some embodiments, the programming procedure for the second page tightens the threshold voltage distribution 501 to a new S0. If the memory cell was in state S0 and the data to be written to the second page is "0", the memory cell is moved to state S2 (threshold voltage distribution 506). State S2 has a verify point (lowest voltage) of C ^* . If the memory cell is in state S4 and the data to be written to the memory cell is "1", the memory cell is in S4. However, as shown in FIG. 7C, state S4 is tightened by moving memory cells from threshold voltage distribution 504 to threshold voltage distribution 508 for state S4. Threshold voltage distribution 508 has a verification point of E ^* (as compared to E ^** of threshold voltage distribution 504). If the memory cell is in state S4 and the data to be written to the second page is "0", the memory cell is moved to state S6 (threshold voltage distribution 510) with a verification point of G ^* . Has a threshold voltage.

After adjacent memory cells have been programmed, states S2, S4, and S6 become wider due to floating gate to floating gate coupling, as shown by threshold voltage distributions 506, 508, and 510 of FIG. 7D. . In some cases, the width of state SO can also be widened.

7E, 7F, 7G and 7H illustrate the programming of the third page. Although one graph can be used to illustrate the programming, it is described as four graphs to facilitate visual readout. After the second page is programmed, the memory cells are in either of states SO, S2, S4 or S6. 7E shows that the memory cell in state SO is programmed for the third page. 7F shows that the memory cell in state S2 is programmed for the third page. 7G shows that the memory cell in state S4 is programmed for the third page. 7H shows that the memory cell in state S6 is programmed for the third page. FIG. 7I shows the threshold voltage distributions after the procedure of FIGS. 7E, 7F, 7G and 7H have been performed (simultaneously or sequentially) on a group of memory cells.

If the memory cell is in state S0 and the third page data is "1", the memory cell remains in state S0. If the data for the third page is "0", the threshold voltage for the memory cell is raised to be in state S1, in which case the verification point is B (see Figure 7E).

If the memory cell is in state S2 and the data to be written to the third page is "1", the memory cell will remain in state S2 (see Fig. 7F). However, some programming may be performed to tighten the threshold distribution 506 to a new state S2 with a verification point of C volts. If the data to be written to the third page is "0", the memory cell is programmed to state S3, in which case the verify point is D volts.

If the memory cell is in state S4 and the data to be written to the third page is "1", the memory cell will remain in state S4 (see Fig. 7G). However, some programming may be performed to tighten the threshold voltage distribution 508 to a new state S4 with verification point E. If the memory cell is in state S4 and the data to be written to the third page is "0", the memory cell will have a raised threshold voltage to be in state S5, in which case the verification point is F.

If the memory cell is in state S6 and the data to be written to the third page is "1", the memory cell will remain in state S6 (see Fig. 7H). However, there may be some programming that causes the threshold voltage distribution 510 to tighten to a new state S6 with verification point G. If the third page data is "0", the memory cell will have its threshold voltage programmed to state S7, in which case the verification point is H. At the end of programming the third page, the memory cell will be in one of the eight states shown in FIG. 7I.

8 shows an example of a sequence for programming any set or page of memory cells. This table provides the order of programming for the four word lines WL0, WL1, WL2 and WL3 in FIG. 4. However, this table can be configured to accommodate more or less than four word lines. The first page of memory cells coupled to WL0 is programmed, the first page of memory cells coupled to WL1 is programmed, the second page of memory cells coupled to WL0 is programmed, and then the first page of memory cells coupled to WL2 The page is programmed, then the second page of memory cells connected to WL1 is programmed, and so on.

9 is a flowchart illustrating a programming procedure for programming memory cells connected to a selected word line. In one embodiment, the procedure of FIG. 9 is used to program a block of memory cells. In one embodiment of the procedure of FIG. 9, the memory cells are preprogrammed (step 550) to maintain uniform wear on the memory cells. In one embodiment, the memory cells are preprogrammed in state 7, any pattern, or any other pattern. In some embodiments, pre-programming does not need to be performed.

In step 552, memory cells are erased (in blocks or other units) prior to programming. In one embodiment, memory cells are erased by raising the p-well to an erase voltage (e.g., 20 volts) for a sufficient time and grounding the word lines of the selected block, in which case the source and bit lines Are in a floating state. Due to capacitive coupling, unselected word lines, bit lines, select lines and common source lines are also raised by a significant portion of the erase voltage. Thus, a strong electric field is applied to the tunnel oxide layers of the selected memory cells, so that the selected memory cells are erased because the electrons of the floating gates are generally Fowler-Nodeheim tunneling mechanisms. Due to the Nordheim tunneling mechanism). As electrons are transferred from the floating gate to the p-well region, the threshold voltage of the selected cell is lowered. Erase may be performed on the entire memory array, on individual blocks, or in another unit of cells. In one embodiment, after erasing the memory cells, all of the erased memory cells may be in state SO (see FIG. 6).

In step 554, a soft program is performed to narrow the distribution of erased threshold voltages for erased memory cells. As a result of the erase procedure, some memory cells may be in a deeper erased state than necessary. Soft programming may apply programming pulses to move the threshold voltage of the erased memory cells closer to the erase verify level. For example, referring to FIG. 6, step 554 may include tightening the threshold voltage distribution associated with state SO. In step 556, the memory cells of the block are programmed as described herein. The procedure of FIG. 9 can be performed by an indication of a state machine using the various circuits described above. In another embodiment, the procedure of FIG. 9 may be performed at the instruction of a controller using the various circuits described above. After the procedure of FIG. 9 is performed, the memory cells of the block can be read.

10 is a flowchart of a procedure for performing programming on memory cells connected to a common word line. The procedure of FIG. 10 may be performed once or several times during step 556 of FIG. 9. For example, the procedure of FIG. 10 can be used to perform the full sequence programming of FIG. 6, in which case the procedure of FIG. 10 will be performed once for each word line. In one embodiment, the programming procedure is performed in order of operation toward the bit line, starting with the word line closest to the source line. Also, the procedure of FIG. 10 can be used to perform programming of a page of data for a word line, in conjunction with the programming procedure of FIGS. 7A-7I, in which case the procedure of FIG. Can be performed times. Other ways can also be used.

In general, the program voltage applied to the control gate during a program operation is applied in a series of program pulses. There is a set of verify pulses between the programming pulses to enable verify. In many embodiments, the magnitude of the program pulses is increased by a predetermined step size in the form of each successive pulse. In step 608, the programming voltage Vpgm is initialized to a starting magnitude (e.g., ~ 12V or other appropriate level) and the program counter (PC) managed by the state machine 222 is set to one. It is initialized. In step 610, a program pulse of the program signal Vpgm is applied to the selected word line (selected word line for programming). Unselected word lines receive one or more boosting voltages (eg, ˜8 volts) to perform the boosting scheme known in the art. If the memory cell must be programmed, the corresponding bit line is grounded. On the other hand, if the memory cell must remain in its current data state, the corresponding bit line is connected to V _DD to inhibit programming. More information about boosting schemes can be found in US Pat. No. 6,859,397 and US Patent Application No. 11 / 555,850, all of which are incorporated herein by reference.

In step 612, the state of the selected memory cells is verified using an appropriate set of target levels. If it is detected that the threshold voltage of the selected memory cell has reached the appropriate target level, the memory cell is locked out of further programming, for example by raising the bit line voltage during subsequent programming pulses. In step 614, it is checked whether all memory cells have reached their target threshold voltages. If so, the programming procedure is complete and successful, because all selected memory cells have been programmed and verified with their target states. In step 616, the status of "PASS" is reported. Note that in some embodiments, at step 614 it should be checked whether at least a predetermined number of memory cells are properly programmed. This predetermined number may be less than the number of all memory cells, such that the programming procedure may stop before all the memory cells reach their appropriate verify levels. Memory cells that are not successfully programmed may be corrected using error correction during the read procedure.

If, at step 614, it is determined that not all of the memory cells have reached their target threshold voltage, the programming procedure continues. In step 618, the program counter PC is checked against the program limit value PL. One example of a program limit value is 20, although other values may be used in various embodiments. If the program counter PC is not less than the program limit value, it is determined in step 630 whether the number of unsuccessfully programmed memory cells is less than or equal to a predetermined number. If the number of unsuccessfully programmed memory cells is less than or equal to a predetermined number, the programming procedure is flagged as passed and the status of the pass PASS is reported in step 632. In many cases, unsuccessfully programmed memory cells may be corrected using error correction during a read procedure. However, if the number of unsuccessfully programmed memory cells is greater than the predetermined number, then the program procedure is flagged as failed and the status of FAIL is reported in step 634.

If at step 618 it is determined that the program counter PC is less than the program limit value PL, then at step 620 the system determines whether the program voltage has reached the maximum level (called the maximum program voltage). do. For example, in some memory systems, a charge pump is used to generate programming voltages from a supply voltage. This charge pump may have a maximum voltage or may apply a maximum voltage that the system can apply to word lines. If the programming voltage being applied to the selected word line is not yet at the maximum program voltage, then the magnitude of the voltage pulse of the next program signal Vpgm is increased by a step size (e.g., a step size of 0.2-0.4 volts). The program counter PC is incremented at step 622. In one embodiment, the width of the pulse does not change at step 622. After step 622, the procedure then returns to step 610 to apply a Vpgm voltage pulse.

If, at step 620, it is determined that the magnitude of the programming voltage has reached (or exceeded) the maximum program voltage, one or more programming pulses may be used to determine the duration of the programming signal Vpgm between verify operations (step 624). Is authorized to change. For example, the amount of programming voltage applied to selected memory cells between verify operations (eg, between repetitions of step 612) may be achieved by using a wider programming pulse or by using a plurality of programming pulses. Is increased. When using a plurality of programming pulses to increase the amount of programming voltage applied to selected memory cells, the system will not perform a verify operation between the plurality of pulses of the group of pulses. Rather, one or more verify operations will be performed before the group of pulses (the last iteration of step 612), and one or more verify operations will be performed after the group of the plurality of pulses (the next iteration of step 612). will be. Whether using wider pulses or multiple pulses, the magnitude of the program pulse is at or below the maximum program voltage.

One purpose of procedure 624 is to intelligently control the increase in the threshold voltage of the memory cells being programmed. In some embodiments that use a programming signal, which is a series of pulses of increasing magnitude to a predetermined step size in the form of each successive pulse, on average, the memory cells being programmed have a step size in response to each pulse. Will have an increased threshold voltage. Once the magnitude of the program pulses reaches the maximum program voltage, the pulse width of the pulses can be widened (rather than increasing the magnitude of the pulses) to maintain the same rate of increase of the threshold voltage of the memory cells being programmed. have. Alternatively, a plurality of program pulses may be applied to achieve the same effect as widening the pulse width. Either way, the duration of the programming voltage applied to the selected memory cells between the verify operations is increased. In some embodiments, step 624 may be used to maintain a rate equal to the rate of increase of the threshold voltage obtained before reaching the maximum program voltage, while other embodiments may use other methods to increase the rate of increase of the threshold voltage. Can be controlled.

Step 624 also includes incrementing the program counter. After step 624, the procedure of FIG. 10 continues with one or more verify operations at step 612.

Step 612 of FIG. 10 includes performing one or more verify operations. In general, during a verify operation and a read operation, the selected word line is connected to any voltage, and its level is determined by each read and verify operation to determine whether the threshold voltage of the corresponding memory cell has reached such a level. For example, see B, C, D, E, F, G, and H of FIG. 7I). After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell is turned on in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, the memory cell is turned on and the voltage applied to the word line is assumed to be greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, the memory cell is not turned on and it is assumed that the voltage applied to the word line is not greater than the threshold voltage of the memory cell.

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of the memory cell is measured at the rate of discharging or charging the dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell may cause the NAND string comprising the memory cell to discharge (or not be able to discharge) the corresponding bit line. The voltage on the bit line is measured after a certain time to see if the bit line is discharged or not.

11A-11C are flowcharts illustrating various embodiments in which the duration of a program signal is increased. That is, each of the flowcharts of FIGS. 11A-11C provides an example of a procedure performed as part of step 624 of FIG. 10.

The embodiment of FIG. 11A includes using wider pulses after reaching the maximum program voltage. In step 702 of the procedure of FIG. 11A, the pulse width of the next programming pulse is increased based on a constant. The constant may be an absolute value or a percentage of the previous pulse width. For example, the pulse width may increase by X time units or may increase by Y% of the previous pulse width. Step 702 includes applying a program pulse of a wider new pulse width. In one embodiment, the program pulse is applied at the magnitude of the maximum program voltage (or close to the maximum program voltage). In other embodiments, other sizes may be used. The procedure of FIG. 11A may be performed during step 624 for each iteration of the procedure loop of FIG. 10 after Vpgm has reached the maximum program voltage. In one embodiment, step 702 includes configuring a charge pump.

12 schematically illustrates an example of a programming signal according to the embodiment of FIG. 11A. Programming pulses 802, 804, 806, 808, 810, 812, 814, 816, 818, and 820 represent pulses that have a fixed pulse width and that increase in magnitude with a fixed step size. The magnitude of pulse 820 is at the maximum program voltage. Referring back to FIG. 10, prior to applying pulse 820, step 620 always proceeds to step 622 to increase the size by the step size (and keep the pulse width constant). After applying pulse 820 and performing verification, step 620 performs step 624, where the pulse width is increased (step 702) and the magnitude of the pulse is the maximum for each pulse. It remains constant at the program voltage, as shown in Figure 12, the width of pulse 822 has a wider pulse width than the width of pulse 820, and the width of pulse 824 is the width of pulse 822. With a wider pulse width, the width of pulse 826 has a wider pulse width than the width of pulse 824, and the width of pulse 828 has a wider pulse width than the width of pulse 826. The magnitudes of the pulses 822, 824, 826, and 828 all have the magnitude of the maximum program voltage In one embodiment, not all pulses need to include a larger pulse width after reaching the maximum program voltage. .

As described above, there are one or more verify pulses between programming pulses. For example, seven verify pulses can be used at the magnitudes of B, C, D, E, F, G and H volts (see FIG. 7I). These verify pulses are not shown in FIG. 12 to facilitate drawing reading. However, in FIG. 13, three of the programming pulses 810, 812, and 814 are seven verify pulses () between pulses 810 and 812 and between pulses 812 and 814. Also, it is shown as having seven verify operations).

14 is a table providing another example of a programming signal according to the embodiment of FIG. 11A. This table provides example magnitudes and pulse widths for the programming signals. The table of FIG. 14 also provides an average threshold voltage Vth for a group of memory cells that are programmed from an erased state. As can be seen in Figure 14, prior to reaching a maximum program voltage of 23.25 volts, the program pulses are increasing in size by a fixed step size of 0.25 volts, while maintaining a constant pulse width of 10.00 Hz The average threshold voltage is increased by 0.25 volts. After reaching the maximum program voltage of 23.25 volts, the magnitude of the program pulse remains 23.25 volts, but the pulse width of the program pulse is increasing, so the average threshold voltage continues to increase by 0.25 volts.

In one embodiment, it should be noted that pulse # 1 of FIG. 14 is not the first pulse applied. There may be previously applied pulses such that programming reaches a steady state by a pulse of 17.00 volts.

11B provides another embodiment of performing step 624 of FIG. 10. In step 710, one or more customizable parameters are stored. These parameters indicate the pulse width magnitudes to use for the pulses after reaching the maximum program voltage. For example, the one or more customizable parameters may include one parameter indicating a step size for increase in pulse width or one parameter indicating a percentage increase in pulse width. In another embodiment, a parameter is stored for each pulse applied after reaching the maximum program voltage. Each parameter represents a pulse width for each pulse. Step 710 of FIG. 11B is shown in dashed lines to indicate that it may be performed at another time following the other steps of FIG. 11B. In one example, the customizable parameters are set during manufacturing or at the testing stage. In another embodiment, the user can set parameters at any time via the host device.

In step 712, the system reads the parameters associated with the next programming pulse to be applied. In step 714, the next program pulse is applied with a pulse width set based on the parameter read in step 712. One embodiment includes configuring the charge pump circuit to adjust the pulse width. The procedure of FIG. 11B involves using the same magnitude for the pulses. For example, all of the pulses applied after reaching the maximum program voltage may have the same magnitude as the maximum program voltage.

FIG. 11C provides another embodiment of executing step 624 of FIG. 10, including applying a plurality of program pulses between verify operations to achieve an effect similar to widening the pulse width. In step 720, the system determines the number of iterations of the programming loop of FIG. 10 that has been performed since reaching the maximum program voltage. In step 722, one or more program pulses are applied based on the number of repetitions determined in step 720. For example, after the maximum program voltage, the system may apply a set of two programming pulses at the maximum program voltage, and then apply a set of three programming pulses at the maximum program voltage, then four at the maximum program voltage. May apply a set of two programming pulses. Step 772 adds additional programming pulses to achieve the goal of increasing the duration of the program voltage between verify operations. There is one or more sets of verify operations between each set of programming pulses. Within a set of programming pulses, programming pulses are applied without performing verify operations. In one embodiment, the determination of how many program pulses to apply is made by incrementing the number of pulses for each iteration of the programming loop of FIG. 10 after reaching the maximum program voltage. In another embodiment, customizable parameters (see FIG. 11B) can be used to identify how many program pulses to use.

15 schematically illustrates an example of a programming signal according to the embodiment of FIG. 11C. Programming pulses 850, 852, 854, 856, 858, 860, 862, 864, 866 and 868 represent pulses with a fixed pulse width and magnitude increasing by a fixed step size. The magnitude of pulse 868 is at the maximum program voltage. Referring back to FIG. 10, prior to applying pulse 868, step 620 always proceeds to step 622 to increase in size by the step size (also keep the pulse width constant). After applying pulse 868 and performing verification, step 620 causes step 624 to be performed, wherein the system is configured to apply two pulses 870 and 872. Both pulses 870 and 872 are at the maximum program voltage and also have the same pulse width as the previous pulses (although other pulse widths and magnitudes may be used). Next, step 624 is performed and the system is configured to apply three pulses 874, 876 and 878. Next, step 624 is performed and the system is configured to apply four pulses 880, 882, 884, 886. And it can continue in this way.

Verify operations are performed between sets of program pulses (eg 870/872 is one set and 874/875/878 is an example of sets), and no verify operation is performed within the sets of program pulses. . Thus, this embodiment makes the duration of the valid program signal longer by using a plurality of program pulses between verify operations. For example, between program pulse 868 and program pulse 870, one or more verify operations are performed. For example, FIG. 16 shows seven verify operations (corresponding to seven verify pulses) performed between program pulse 868 and program pulse 870. Between the program pulse 870 and the program pulse 872, no verify operation is performed. Between program pulse 872 and program pulse 874, one or more verify operations are performed. For example, FIG. 16 shows seven verify operations (corresponding to seven verify pulses) performed between program pulse 872 and program pulse 874. Between program pulses 874, 876 and 878, no verify operation is performed. In addition, a verify operation is also performed between each of the program pulses 850, 852, 854, 856, 858, 860, 862, 864, 866 and 868.

In an alternative embodiment to the pulse signal of FIGS. 11C and 15, each set of pulses (eg, 870/872 is one set and 874/875/878 is an example of sets) each has its own set of magnitudes. In combination with its magnitude, the combined duration of the pulses in the set provides the desired programming amount. In one embodiment, the magnitude of the number of pulses in the set and the number of pulses in the set may be determined from user configurable parameters (see FIG. 11B) and / or achieve a constant programming amount within each set. (And, optionally, this is also the same programming amount as each pulse 850-868).

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to these embodiments. Many modifications and variations are possible in light of the above teaching. The above-described embodiments are chosen to best explain the principles of the present invention and their practical applications, whereby those skilled in the art will be suitable for the particular use desired, and in various embodiments, also in various modifications. Together with them, they are chosen to enable the best possible use. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

A method of programming nonvolatile storage,
And applying a programming signal to the non-volatile storage device, wherein applying the programming signal comprises: programming pulses having a constant pulse width before the one or more pulses reach a maximum magnitude; Applying to and applying one or more programming pulses to the non-volatile storage device providing a change in duration of the programming signal between verify operations after one or more pulses have reached their maximum magnitude. How to program a non-volatile storage characterized by.

The method of claim 1,
Programming pulses having a constant pulse width are applied in increasing magnitude.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in duration of the programming signal comprises applying one or more programming pulses with varying pulse widths. How to.

The method of claim 1,
Applying one or more programming pulses to the nonvolatile storage element providing a change in duration of the programming signal comprises applying one or more programming pulses with increasing pulse widths. How to program.

The method of claim 1,
Applying one or more programming pulses to the nonvolatile storage device providing a change in the duration of the programming signal comprises applying one or more programming pulses having pulse widths that change to a constant value. How to program nonvolatile storage.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in duration of the programming signal comprises applying one or more programming pulses having pulse widths that vary with a variable value. How to program a non-volatile storage characterized by.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in duration of the programming signal comprises applying one or more programming pulses with pulse widths that increase to a constant value. How to program volatile storage.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in duration of the programming signal comprises applying one or more programming pulses with increasing pulse widths to varying values. How to program nonvolatile storage.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in duration of the programming signal comprises applying one or more programming pulses with increasing pulse widths and the maximum magnitude. How to program nonvolatile storage.

The method of claim 1,
Storing a set of customizable pulse width parameters,
Applying one or more programming pulses to the non-volatile storage element providing a change in the duration of the programming signal may include one or more programming pulses having increasing pulse widths based on the stored customizable pulse width parameter set. A method for programming non-volatile storage, comprising applying.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in the duration of the programming signal comprises applying a plurality of pulses between verify operations. Way.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in the duration of the programming signal comprises applying a plurality of pulses at the maximum magnitude between verify operations. How to program volatile storage.

The method of claim 1,
Applying one or more programming pulses to the nonvolatile storage element providing a change in duration of the programming signal includes applying one or more groups of different numbers of programming pulses to the nonvolatile storage element, each Wherein a group of s is applied between the verify operations.

The method of claim 1,
Applying one or more programming pulses to the non-volatile storage element providing a change in duration of the programming signal,
Determining how many program verify cycles were performed within the current time period, and
Applying any number of programming pulses to the nonvolatile storage device based on the determination.

The method of claim 1,
Applying the programming signal,
(a) applying a pulse to the control gate of the nonvolatile storage element,
(b) performing one or more verify operations on the non-volatile storage element;
(c) determining whether a maximum voltage has been used for the programming signal;
(d) if the maximum voltage has not yet been used for the programming signal, repeating steps (a) to (c) with a higher magnitude pulse, and
(e) if said maximum voltage has been used for said programming signal, comprising repeating steps (a) through (c) with one or more pulses of longer duration; How to program it.

Non-volatile storage system,
A nonvolatile storage element; And
One or more management circuits in communication with the non-volatile storage element,
The one or more management circuits may program the nonvolatile storage element by applying a programming signal to the nonvolatile storage element, and applying the programming signal has a constant width before one or more pulses reach a maximum magnitude. Applying one or more programming pulses to the nonvolatile storage device and providing a change in the duration of the programming signal between verify operations after one or more pulses have reached their maximum magnitude. Non-volatile storage system comprising applying to the storage element.

The method of claim 16,
And said programming pulses having said constant width are applied by said one or more management circuits in increasing magnitude.

The method of claim 16,
Applying one or more programming pulses to the nonvolatile storage element providing a change in the duration of the programming signal comprises the one or more management circuits applying one or more programming pulses with varying pulse widths. Non-volatile storage system.

The method of claim 16,
Applying one or more programming pulses to the nonvolatile storage element providing a change in duration of the programming signal includes the one or more management circuits applying one or more programming pulses with increasing pulse widths. Non-volatile storage system.

The method of claim 16,
Applying one or more programming pulses to the nonvolatile storage element providing a change in the duration of the programming signal is such that the one or more management circuits apply one or more programming pulses having pulse widths that increase to a variable value. Non-volatile storage system comprising a.

The method of claim 16,
Applying one or more programming pulses to the non-volatile storage element providing a change in duration of the programming signal means that the one or more management circuits apply one or more programming pulses with pulse widths that increase to a constant value. Non-volatile storage system comprising a.

The method of claim 16,
Applying one or more programming pulses to the nonvolatile storage element providing a change in the duration of the programming signal is such that the one or more management circuits apply one or more programming pulses with increasing pulse widths and the maximum magnitude. Non-volatile storage system comprising a.

The method of claim 16,
Applying one or more programming pulses to the nonvolatile storage element providing a change in duration of the programming signal comprises the one or more management circuits applying a plurality of pulses between verify operations. Non-volatile storage system.

The method of claim 16,
Applying one or more programming pulses to the nonvolatile storage element providing a change in duration of the programming signal indicates that the one or more management circuits apply a plurality of pulses at the maximum magnitude between verify operations. Non-volatile storage system comprising a.

The method of claim 16,
And the nonvolatile storage element is a flash memory device.