KR20100044996A - Image sensor and method for manufacturing thereof - Google Patents

Image sensor and method for manufacturing thereof Download PDF

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Publication number
KR20100044996A
KR20100044996A KR1020080104006A KR20080104006A KR20100044996A KR 20100044996 A KR20100044996 A KR 20100044996A KR 1020080104006 A KR1020080104006 A KR 1020080104006A KR 20080104006 A KR20080104006 A KR 20080104006A KR 20100044996 A KR20100044996 A KR 20100044996A
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South Korea
Prior art keywords
semiconductor substrate
doped layer
trench
depth
region
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KR1020080104006A
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Korean (ko)
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황상일
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주식회사 동부하이텍
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Priority to KR1020080104006A priority Critical patent/KR20100044996A/en
Publication of KR20100044996A publication Critical patent/KR20100044996A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

An image sensor according to an embodiment includes a gate formed on a semiconductor substrate; A plurality of trenches formed in the semiconductor substrate such that a surface of the semiconductor substrate corresponding to one side of the gate has a step; A first doped layer formed in a deep region of the semiconductor substrate along a step of the semiconductor substrate; A second doped layer formed in a shallow region of the semiconductor substrate along a step of the semiconductor substrate to be in contact with the first doped layer; And a floating diffusion region formed in the semiconductor substrate corresponding to the other side of the gate, wherein the first doped layer and the second doped layer formed between the adjacent trenches are formed to have a first depth and correspond to the trench. The first doped layer and the second doped layer may be formed to have a second depth deeper than the first depth.

Description

Image Sensor and Method For Manufacturing Thereof}

Embodiments relate to an image sensor and a method of manufacturing the same.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor includes a light sensing area for detecting light and a logic circuit portion for processing the detected light into an electrical signal to make data.

Complementary Metal Oxide Semiconductor (CMOS) image sensors employ a switching scheme that creates MOS transistors as many as the number of pixels and uses them to sequentially detect the output.

As the CMOS image sensor is highly integrated, the size of the unit pixel is proportionally reduced and the photodiode, which is a photo response region, is also relatively reduced, thereby reducing the light receiving region.

In particular, the visible light applied to the photodiode generates an electron-hole pair at different depths depending on the intensity of the wavelengths of red, green and blue. Each of these depths is determined by the surface depth of the wavelength, with the shallowest wavelength being blue and the deepest being red.

If the photodiode area is reduced, there is a problem in that the quality of the image sensor is degraded due to a difference in short wavelength and long wavelength.

The embodiment provides an image sensor and a manufacturing method which can improve light sensitivity by expanding a light receiving area of a photodiode.

An image sensor according to an embodiment includes a gate formed on a semiconductor substrate; A plurality of trenches formed in the semiconductor substrate such that a surface of the semiconductor substrate corresponding to one side of the gate has a step; A first doped layer formed in a deep region of the semiconductor substrate along a step of the semiconductor substrate; A second doped layer formed in a shallow region of the semiconductor substrate along a step of the semiconductor substrate to be in contact with the first doped layer; And a floating diffusion region formed in the semiconductor substrate corresponding to the other side of the gate, wherein the first doped layer and the second doped layer formed between the adjacent trenches are formed to have a first depth and correspond to the trench. The first doped layer and the second doped layer include those formed to have a second depth deeper than the first depth.

In another embodiment, a method of manufacturing an image sensor includes: forming at least one trench in a semiconductor substrate such that a surface of a semiconductor substrate in which a photodiode predetermined region is defined has a step; Forming a gate on the semiconductor substrate; Forming a first doped layer in a deep region of the semiconductor substrate along the step of the semiconductor substrate; Forming a second doped layer in a shallow region of the semiconductor substrate along a step of the semiconductor substrate to be in contact with the first doped layer; And forming a floating diffusion region in the semiconductor substrate corresponding to the other side of the gate, wherein the first doped layer and the second doped layer formed between the adjacent trenches are formed to have a first depth and are formed in the trench. The first doped layer and the second doped layer corresponding to the formed to have a second depth deeper than the first depth.

According to the image sensor and the manufacturing method according to the embodiment, the trench of the grid structure is formed in the photodiode region and the photodiode formed in the photodiode region has a grid structure so that the light receiving area of the photodiode is extended to improve the light sensitivity Can be.

In addition, the photodiodes may be formed to have different depths by the trenches, thereby improving image characteristics by maintaining uniform light sensitivity for short wavelengths and long wavelengths.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

6 is a cross-sectional view of an image sensor according to an embodiment.

An image sensor according to an embodiment includes a gate 30 formed on a semiconductor substrate 10; A plurality of trenches 40 formed in the semiconductor substrate 10 so that the surface of the semiconductor substrate 10 corresponding to one side of the gate 30 has a step; A first doped layer 50 formed in a deep region of the semiconductor substrate 10 along a step of the semiconductor substrate 10; A second doped layer 60 formed in a shallow region of the semiconductor substrate 10 along a step of the semiconductor substrate 10 to be in contact with the first doped layer 50; And a floating diffusion region 70 formed in the semiconductor substrate 10 corresponding to the other side of the gate 30, wherein the first doped layer 50 and the second doped layer formed between the trenches 40 are formed. 60 is formed to have a first depth D1 and the first doped layer 50 and the second doped layer 60 corresponding to the trench 40 have a second depth deeper than the first depth D1. It includes what was formed to have (D2).

The semiconductor substrate 10 may be a single crystal silicon substrate, and may be a substrate doped with P-type impurities or N-type impurities. In an embodiment, the semiconductor substrate 10 is a high concentration p-type semiconductor substrate, and the semiconductor substrate 10 includes a low concentration p-type epi layer (p-epi).

The first doped layer 50 is formed of an n-type impurity and the second doped layer 60 is formed of a p-type impurity such that the first doped layer 50 and the second doped layer 60 are formed of pn junction. It acts as a photodiode to produce photoelectrons.

Since the first and second doped layers 50 and 60 are formed by ion implantation into the semiconductor substrate 10 having a step by the trench 40, the first and second doped layers 50 and 60 are also formed. Have a step For example, the first and second doped layers 50 and 60 formed in the semiconductor substrate 10 between the trenches 40 are formed to have a first depth D1, and the trenches 40 may be formed in the trench 40. The first and second doped layers 50 and 60 formed on the semiconductor substrate 10 corresponding to the lower portion may be formed to have a second depth D2 deeper than the first depth.

As described above, a step having a different depth between the first doped layer 50 and the second doped layer 60 formed in the semiconductor substrate 10 may be formed to uniformly maintain the light sensitivity.

That is, the first doped layer 50 and the second doped layer 60 formed in the semiconductor substrate 10 corresponding to the trenches 40 are formed to have a first depth D1 to have a short wavelength band. The first doped layer 50 and the second doped layer 60 corresponding to the lower portion of the trench 40 may be formed to have a second depth D2 to absorb light in a long wavelength band. It is advantageous to be able to maintain a uniform light sensitivity.

A manufacturing method of an image sensor according to an embodiment will be described with reference to FIGS. 1 to 6.

Referring to FIG. 1, a first photoresist pattern 210 is formed on the semiconductor substrate 10 so that the photodiode predetermined region A is selectively exposed.

The semiconductor substrate 10 may be a single crystal silicon substrate, and may be a substrate doped with P-type impurities or N-type impurities. In the embodiment, the semiconductor substrate 10 is a high concentration p-type semiconductor substrate 10. In addition, the semiconductor substrate 10 includes an epitaxial process to form a low concentration p-type epi layer (p-Epi).

A plurality of device isolation layers 20 defining an active region and a field region are formed in the semiconductor substrate 10. A unit pixel including a photodiode and a transistor may be formed in the active region of the semiconductor substrate 10.

The first photoresist pattern 210 is formed to selectively expose the photodiode predetermined region A of the semiconductor substrate 10. That is, the first photoresist pattern 210 is formed to cover all of the remaining regions except for the photodiode predetermined region A. FIG. In addition, a plurality of openings 215 may be formed in the first photoresist pattern 210 so that the photodiode predetermined region A is partially exposed. In particular, the width of the opening 215 of the first photoresist pattern 210 may be shorter to the extent that photolithography technology permits. For example, the width of the opening 215 may be formed to 40 ~ 50nm.

The opening 215 may be formed in the shape of a rectangle, a circle, and a polygon. In addition, the first photoresist pattern 210 formed in the photodiode predetermined region A may be formed to have a lattice pattern when viewed in plan view.

The first photoresist pattern 210 may apply a photoresist on the semiconductor substrate 10 through a spin process, and may partially expose the photodiode predetermined region A by performing an exposure and development process using a mask. Can be.

Referring to FIG. 2, a trench 40 is formed in the photodiode predetermined region A of the semiconductor substrate 10. The trench 40 may be formed to have a predetermined depth in the semiconductor substrate 10 so that a step may be formed on the surface of the semiconductor substrate 10. For example, the surface of the semiconductor substrate 10 is referred to as the reference plane C1, and the surface of the semiconductor substrate 10 exposed by the trench 40 is referred to as the bottom surface C2. Accordingly, a step difference between the reference plane C1 and the bottom surface C2 by the height H of the sidewalls of the trench 40 is generated.

The trench 40 may be formed by etching the semiconductor substrate 10 using the first photoresist pattern 210 as an etching mask. That is, the opening 215 of the first photoresist pattern 210 may be formed. The semiconductor substrate 10 may be selectively removed to form a plurality of trenches 40. For example, the trench 40 may be formed by wet etching, dry etching, or dry isotropic etching. The trench 40 may have a height H of a sidewall of about 200 nm to about 400 nm.

The plurality of trenches 40 formed in the semiconductor substrate 10 corresponding to the photodiode predetermined region A may have a lattice structure when viewed in plan view. In addition, each of the trenches 40 may be formed in the shape of a rectangle, a circle, or a polygon.

Referring to FIG. 3, a gate 30 is formed on the semiconductor substrate 10. The gate 30 may be a gate 30 of a transfer transistor. The gate 30 may be formed by depositing and patterning a gate insulating film and a gate conductive film. For example, the gate insulating film may be an oxide film, and the gate conductive film may be formed of a single layer or a plurality of layers of a metal such as polysilicon and tungsten and a metal silicide.

Referring to FIG. 4, a second photoresist pattern 220 is formed on the semiconductor substrate 10. The second photoresist pattern 220 may be formed to cover the semiconductor substrate 10 including the gate 30. Therefore, the trench 40 and the semiconductor substrate 10 corresponding to the photodiode predetermined region A may be exposed by the second photoresist pattern 220.

Next, a photodiode having a step is formed on the semiconductor substrate 10 corresponding to the photodiode predetermined region A. FIG. The photodiode may have a structure in which the first doped layer 50 and the second doped layer 60 are stacked. For example, the first doped layer 50 may be formed of n-type impurity (n−), and the second doped layer 60 may be formed of p-type impurity (p0).

Specifically, the first doped layer 50 is formed by ion implanting n-type impurities into the deep region of the semiconductor substrate 10 by an ion implantation process using the second photoresist pattern 220 as an ion implantation mask. Can be. In this case, the semiconductor substrate 10 may be formed in a structure having a step by the trench 40 so that the first doped layer 50 may also be formed in a structure having a step. That is, the first doped layer 50 injected through the bottom surface C2 of the trench 40 due to the height difference of the trench 40 is injected through the reference surface C1 of the semiconductor substrate 10. It may have a deeper depth than the first doped layer 50.

Next, a p-type impurity is ion-implanted into a shallow region of the semiconductor substrate 10 by an ion implantation process using the second photoresist pattern 220 as an ion implantation mask to form the first doped layer 50 and the first doped layer 50. The second doped layer 60 is formed to be in contact. The second doped layer 60 is formed along the surface of the semiconductor substrate 10 on which the trench 40 is formed to have a step.

Impurities of the first and second doped layers 50 and 60 may be diffused by performing a heat treatment process after forming the first and second doped layers 50 and 60.

The first doped layer 50 and the second doped layer 60 are ion-implanted into the semiconductor substrate 10 on which the trench 40 is formed to have a stepped structure. For example, the first and second doped layers 50 and 60 formed in the lower region of the reference plane C1 of the semiconductor substrate 100 are formed to have a first depth D1 and the bottom surface of the trench 40. The first and second doped layers 50 and 60 formed in the lower region of C2 may be formed to have a second depth D2 deeper than the first depth D1.

As described above, the stacked structure of the first and second doped layers 50 and 60 may be formed to have a step height, thereby extending the light receiving area of the photodiode. That is, the photodiode has a stepped structure in a limited unit pixel size, thereby increasing the generation rate of photoelectrons by expanding the light receiving region.

In addition, the photodiode may be formed to have a first depth D1 and a second depth D2, thereby improving light sensitivity of the photodiode. Specifically, the visible light applied to the photodiode generates an electron-hole pair at different depths according to the intensity of the wavelengths of red, green, and blue. This depth is determined by the surface depth for each wavelength, with the shallowest wavelength being blue and the deepest being red. For example, the blue may be detected in an area of 400 mW from the surface of the photodiode, the green may be detected in an area of 400 mW to 700 mW, and the red may be detected at a depth of 700 mW or less. Therefore, when the photodiode is extended in the same height direction, the sensitivity of the long wavelength red may be higher than that of blue or green, and the light sensitivity may be lowered.

In an embodiment, a trench 40 is formed in the semiconductor substrate 10, a photodiode having a second depth D2 is formed in a lower region of the trench 10, and a photodiode having a first depth D1 in the remaining region. A photodiode is formed to maintain the light sensitivity uniformly. That is, the photodiode formed under the trench 40 and having a second depth D2 senses light having a long wavelength, and the photodiode having a relatively shallow first depth D1 senses light having a short wavelength. Therefore, since photoelectrons can be generated at a uniform ratio in the entire visible light band, the light sensitivity can be improved.

Referring to FIG. 5, spacers are formed on both side walls of the gate 30. A floating diffusion region 70 is formed in the semiconductor substrate 10 corresponding to the other side of the gate 30. The floating diffusion region 70 may be formed by ion implanting a high concentration of n + impurities on the other side of the gate 30.

Referring to FIG. 6, a lower insulating layer 80 including a contact plug 81 is formed on a semiconductor substrate 10 including the gate 30 and a photodiode. The lower insulating layer 80 may be formed of an oxide film or a nitride film to gap fill the trench 40. The contact plug 81 may be connected to the gate 30 and the floating diffusion region 70 to apply an electrical signal.

Next, a metal wiring layer is formed on the lower insulating layer 80. The metal wiring layer includes an upper insulating layer 85 and metal wirings M1, M2, and M3 connected to the contact plug 81 through the upper insulating layer 85. Thereafter, the color filter 90 and the micro lens 100 are formed on the metal wiring layer.

According to the manufacturing method of the image sensor according to the embodiment, the light receiving area of the photodiode can be extended within a limited area to improve the light sensitivity of the photodiode.

In addition, since the photodiode is formed in a lattice structure having a deep region and a shallow region, photoelectrons with respect to green, blue, and red wavelengths may be generated in a balanced manner, thereby improving light sensitivity.

The embodiments described above are not limited to the above-described embodiments and drawings, and it is to be understood that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be obvious to those who have it.

1 to 6 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (10)

A gate formed on the semiconductor substrate; A plurality of trenches formed in the semiconductor substrate such that a surface of the semiconductor substrate corresponding to one side of the gate has a step; A first doped layer formed in a deep region of the semiconductor substrate along a step of the semiconductor substrate; A second doped layer formed in a shallow region of the semiconductor substrate along a step of the semiconductor substrate to be in contact with the first doped layer; And A floating diffusion region formed in the semiconductor substrate corresponding to the other side of the gate; The first doped layer and the second doped layer formed between the adjacent trenches are formed to have a first depth, and the first doped layer and the second doped layer corresponding to the trench are deeper than a first depth. Image sensor, characterized in that formed to have a depth. The method of claim 1, The depth of the trench is an image sensor, characterized in that formed in 200 ~ 400nm. The method of claim 1, And the first and second doped layers are formed to have a pn junction. The method of claim 1, And the trench is formed in the semiconductor substrate to have a lattice structure. The method of claim 1, The trench is an image sensor, characterized in that formed in a rectangular, circular or closed shape. Forming at least one trench in the semiconductor substrate such that a surface of the semiconductor substrate in which the photodiode predetermined region is defined has a step; Forming a gate on the semiconductor substrate; Forming a first doped layer in a deep region of the semiconductor substrate along the step of the semiconductor substrate; Forming a second doped layer in a shallow region of the semiconductor substrate along a step of the semiconductor substrate to be in contact with the first doped layer; And Forming a floating diffusion region in a semiconductor substrate corresponding to the other side of the gate; The first doped layer and the second doped layer formed between the adjacent trenches are formed to have a first depth, and the first doped layer and the second doped layer corresponding to the trench are deeper than a first depth. Method of manufacturing an image sensor, characterized in that formed to have a depth. The method of claim 6, Forming the trench, Forming a first photoresist pattern on the semiconductor substrate to selectively expose the photodiode predetermined region and cover the remaining region; And Selectively etching the semiconductor substrate using the photoresist pattern as an etching mask. The method of claim 6, The depth of the trench is a manufacturing method of the image sensor, characterized in that formed in 200 ~ 400nm. The method of claim 6, Forming the first doped layer and the second doped layer, Forming a photoresist pattern exposing the photodiode region; Implanting a first impurity into a deep region of the semiconductor substrate on which the trench is formed using the photoresist pattern as an ion implantation mask; And And implanting a second impurity into a shallow region of the semiconductor substrate on which the trench is formed by using the photoresist pattern as an ion implantation mask. The method of claim 6, And forming a PMD layer on the semiconductor substrate on which the first and second doped layers are formed to gap fill the trench.
KR1020080104006A 2008-10-23 2008-10-23 Image sensor and method for manufacturing thereof KR20100044996A (en)

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