KR20100038927A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20100038927A
KR20100038927A KR1020080098089A KR20080098089A KR20100038927A KR 20100038927 A KR20100038927 A KR 20100038927A KR 1020080098089 A KR1020080098089 A KR 1020080098089A KR 20080098089 A KR20080098089 A KR 20080098089A KR 20100038927 A KR20100038927 A KR 20100038927A
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KR
South Korea
Prior art keywords
hard mask
semiconductor device
material layer
trench
semiconductor substrate
Prior art date
Application number
KR1020080098089A
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Korean (ko)
Inventor
이민곤
Original Assignee
주식회사 동부하이텍
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Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080098089A priority Critical patent/KR20100038927A/en
Publication of KR20100038927A publication Critical patent/KR20100038927A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for forming a semiconductor device is provided to reduce a process time and costs by forming a hard mask through one deposition process. CONSTITUTION: A hard mask material layer is formed on the upper side of a semiconductor substrate(100). A hard mask(112A) exposes a trench region(120) of the semiconductor substrate by patterning a hard mask material layer. An ion(130) is inserted into the front side of the hard mask, including the exposed trench region. A trench is formed by etching the semiconductor substrate using the hard mask as an etching mask. The hard mask is removed.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for forming a trench.

In general, a method of electrically isolating semiconductor devices from each other is to recess the silicon substrate and grow an insulating layer to perform local oxidation of silicon (LOCOS), or to insulate the silicon substrate in a vertical direction. Shallow Trench Isolation (STI) technology is well known.

1A to 1D show cross-sectional views of a process by a method of manufacturing a general semiconductor device.

A hard mask pattern 20 is formed on the upper front surface of the semiconductor substrate 10 shown in FIG. 1A to expose a region 30 to form a trench, as shown in FIG. 1B. Here, the hard mask pattern 20 has an oxide film 22-nitride film 24-oxide film 26 (ONO: Oxide-Nitride-Oxide) structure. In order to form the hard mask pattern 20 having the ONO structure, an oxide film 22 is first deposited on the semiconductor substrate 10 to be formed, and then a nitride film (CVD) is formed by chemical vapor deposition (CVD). 24 is formed on the oxide film 22 and an oxide film 26 is formed on the nitride film 24. Here, the oxide film 22 has a thickness of approximately 30 kPa to 60 kPa, the nitride film 24 has a thickness of 1000 kPa to 1200 kPa, and the oxide film 26 has a thickness of 1000 kPa to 1200 kPa. Thereafter, the ONO structure 20 is patterned by a photolithography and an etching process using a photoresist (not shown) to complete the hard mask pattern 20 as shown in FIG. 1B.

1C, the trench 40 is formed by etching the semiconductor substrate 10 using the hard mask pattern 20 as an etching mask. Thereafter, as illustrated in FIG. 1D, the hard mask pattern 20 is removed.

As described above, the ONO structure of the hard mask pattern 20 that is generally used to form the trench 40 is formed by three deposition processes. Therefore, there is a very inefficient problem in terms of time and cost of forming the hard mask pattern 20.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the hard mask pattern used to form the trench.

In accordance with an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming a hard mask material layer on an upper surface of a semiconductor substrate, and patterning the hard mask material layer to expose a trench region of the semiconductor substrate. Forming a trench, implanting ions into an entire surface of the hard mask including the exposed trench region, etching the semiconductor substrate using the hard mask as an etching mask, and forming a trench; It is preferred to consist of removing the hard mask.

In the method of fabricating a semiconductor device according to the present invention, since the implantation of the silicon lattice can be weakened by performing ion implantation on the semiconductor substrate to form the trench, the trench can be smoothly formed even using a single layer hard mask pattern. Instead of the general hard mask pattern formed by three deposition processes, the hard mask may be formed by one deposition process, thereby simplifying the process and reducing the process time and cost.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2J are cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.

A hard mask material layer 112 is formed on the semiconductor substrate 100 shown in FIG. 2A as shown in FIG. 2B. Here, the semiconductor substrate 100 may mean a silicon wafer. According to the present invention, the hard mask material layer 112 may be a silicon nitride film (SiN). For example, the thickness of the silicon nitride film 112 may be 1000 kPa to 1200 kPa.

In this case, according to the present invention, the pad oxide film 110 is formed thin on the semiconductor substrate 100 by a CVD process or a thermal oxidation process, and then the hard mask material layer 112 is formed on the pad oxide film 110. Can be formed. As such, the pad oxide layer 110 may be selectively formed. For example, the thickness of the pad oxide film 110 may be 30 kPa to 60 kPa. When the pad oxide layer 110 forms a polysilicon gate (not shown) on the semiconductor substrate 110A, the pad oxide layer 110 serves as a buffer between the polysilicon gate and the semiconductor substrate 110A.

As shown in FIGS. 2B to 2D, the hard mask material layer 112 is patterned to form a hard mask 112A exposing the trench regions 120 of the semiconductor substrate 100. In this case, the pad oxide layer 110 is patterned together with the hard mask material layer 112.

In other words, a photoresist (not shown) is applied on the hard mask material layer 112. The photoresist is then patterned by exposure and development processes to form a photoresist mask 114 that exposes the hard mask material layer 112 corresponding to the trench region 120 as shown in FIG. 2B. Thereafter, using the photoresist mask 114 as an etching mask, the hard mask material layer 112 is dry etched to form the hard mask 112A as shown in FIG. 2C. Thereafter, the pad oxide layer 110 is etched using the hard mask 112A as an etch mask, as shown in FIG. 2D. Thereafter, the hard mask material layer 112 is patterned to form the hard mask 112A, and then the photoresist mask 114 is removed by ashing and cleaning processes.

2C and 2D, the hard mask 112A is first formed, and then the pad oxide film 110 is patterned using the hard mask 112A. However, the pad oxide layer 110 and the hard mask material layer 112 may be etched using the photoresist mask 114 illustrated in FIG. 2B to be patterned as shown in FIG. 2D.

Thereafter, as shown in FIG. 2E, the ion 130 is implanted into the entire surface of the hard mask 112A including the exposed trench region 120. According to the present invention, the dose of ion implantation may be larger than E15ion / cm 2. That is, ions are implanted with an implantation amount of at least E15 ion / cm 2 or more. In addition, the implanted ions 130 may be N-type ions.

As such, when the ion implantation 130 is performed on the exposed semiconductor substrate 100 on which the trench 140 is to be formed, the bonding force between the silicon lattice of the semiconductor substrate 100 is weakened. Thus, even when the single hard mask pattern 112A is used, the trench 140 can be formed smoothly.

As illustrated in FIG. 2F, the trench 140 may be formed by dry etching the semiconductor substrate 110 using reactive ion etching using the hard mask 112A as an etching mask.

Thereafter, as shown in FIG. 2G, the hard mask 112A and the pad oxide layer 110A are removed.

Subsequently, according to one embodiment of the present invention, as shown in FIGS. 2H and 2I, an insulating material 150 is embedded in the trench 140 to form the device isolation layer 150A. That is, the trench 140 is filled with the insulator 150 by a high density plasma (HDP) method as shown in FIG. 2H. Subsequently, the insulation layer 150 is polished until the semiconductor substrate 100A is exposed by a chemical mechanical polarization (CMP) process to form the device isolation layer 150A.

In addition, according to another exemplary embodiment of the present invention, the gate insulating layer 160 is formed on the entire surface of the semiconductor substrate 110A including the trench 140 shown in FIG. 2G, as shown in FIG. 2J. Here, the gate insulating layer 160 may be a gate oxide layer. Thereafter, as illustrated in FIG. 2J, a gate is formed by filling polysilicon 162 to fill the trench 140 on the gate insulating layer 160. The semiconductor device illustrated in FIG. 2J may be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1A to 1D show cross-sectional views of a process by a method of manufacturing a general semiconductor device.

2A to 2J are cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

100 semiconductor substrate 110 pad oxide film

112A: hard mask 150A: device isolation film

160: gate insulating film 162: polysilicon

Claims (10)

Forming a hard mask material layer on top of the semiconductor substrate; Patterning the hard mask material layer to form a hard mask that exposes a trench region of the semiconductor substrate; Implanting ions into the entire surface of the hard mask including the exposed trench regions; Etching the semiconductor substrate to form a trench using the hard mask as an etching mask; And Removing the hard mask; and manufacturing the semiconductor device. The method of claim 1, wherein the semiconductor device is manufactured. And embedding an insulator in the trench to form a device isolation layer. The method of claim 1, wherein the hard mask material layer is a silicon nitride film. The method of claim 1, wherein the semiconductor device is manufactured. Forming a pad oxide film on the semiconductor substrate; And the hard mask material layer is formed over the pad oxide film, and the pad oxide film is patterned together with the hard mask material layer to expose the trench region. The method of manufacturing a semiconductor device according to claim 3, wherein the silicon nitride film has a thickness of 1000 GPa to 1200 GPa. The method of manufacturing a semiconductor device according to claim 4, wherein the pad oxide film has a thickness of 30 kPa to 60 kPa. The method of manufacturing a semiconductor device according to claim 1, wherein the amount of dust in the ion implantation is larger than E15. The method of claim 1, wherein forming the hard mask comprises: Applying a photoresist on top of the hard mask material layer; Patterning the photoresist by a photo and etching process to form a photoresist mask exposing the hard mask material layer corresponding to the trench region; And And etching the hard mask material layer to form the hard mask by using the photoresist mask as an etch mask. The method of manufacturing a semiconductor device according to claim 1, wherein the ions are N-type ions. The method of claim 1, wherein the semiconductor device is manufactured. And embedding polysilicon in the trench to form a gate.
KR1020080098089A 2008-10-07 2008-10-07 Method for manufacturing semiconductor device KR20100038927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080098089A KR20100038927A (en) 2008-10-07 2008-10-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080098089A KR20100038927A (en) 2008-10-07 2008-10-07 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20100038927A true KR20100038927A (en) 2010-04-15

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