KR20100038927A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20100038927A KR20100038927A KR1020080098089A KR20080098089A KR20100038927A KR 20100038927 A KR20100038927 A KR 20100038927A KR 1020080098089 A KR1020080098089 A KR 1020080098089A KR 20080098089 A KR20080098089 A KR 20080098089A KR 20100038927 A KR20100038927 A KR 20100038927A
- Authority
- KR
- South Korea
- Prior art keywords
- hard mask
- semiconductor device
- material layer
- trench
- semiconductor substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 239000000428 dust Substances 0.000 claims 1
- 238000005137 deposition process Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for forming a trench.
In general, a method of electrically isolating semiconductor devices from each other is to recess the silicon substrate and grow an insulating layer to perform local oxidation of silicon (LOCOS), or to insulate the silicon substrate in a vertical direction. Shallow Trench Isolation (STI) technology is well known.
1A to 1D show cross-sectional views of a process by a method of manufacturing a general semiconductor device.
A
1C, the
As described above, the ONO structure of the
An object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the hard mask pattern used to form the trench.
In accordance with an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming a hard mask material layer on an upper surface of a semiconductor substrate, and patterning the hard mask material layer to expose a trench region of the semiconductor substrate. Forming a trench, implanting ions into an entire surface of the hard mask including the exposed trench region, etching the semiconductor substrate using the hard mask as an etching mask, and forming a trench; It is preferred to consist of removing the hard mask.
In the method of fabricating a semiconductor device according to the present invention, since the implantation of the silicon lattice can be weakened by performing ion implantation on the semiconductor substrate to form the trench, the trench can be smoothly formed even using a single layer hard mask pattern. Instead of the general hard mask pattern formed by three deposition processes, the hard mask may be formed by one deposition process, thereby simplifying the process and reducing the process time and cost.
Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.
2A to 2J are cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.
A hard
In this case, according to the present invention, the
As shown in FIGS. 2B to 2D, the hard
In other words, a photoresist (not shown) is applied on the hard
2C and 2D, the
Thereafter, as shown in FIG. 2E, the
As such, when the
As illustrated in FIG. 2F, the
Thereafter, as shown in FIG. 2G, the
Subsequently, according to one embodiment of the present invention, as shown in FIGS. 2H and 2I, an insulating
In addition, according to another exemplary embodiment of the present invention, the
The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
1A to 1D show cross-sectional views of a process by a method of manufacturing a general semiconductor device.
2A to 2J are cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.
DESCRIPTION OF THE REFERENCE NUMERALS
100
112A:
160: gate insulating film 162: polysilicon
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080098089A KR20100038927A (en) | 2008-10-07 | 2008-10-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080098089A KR20100038927A (en) | 2008-10-07 | 2008-10-07 | Method for manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20100038927A true KR20100038927A (en) | 2010-04-15 |
Family
ID=42215573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020080098089A KR20100038927A (en) | 2008-10-07 | 2008-10-07 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20100038927A (en) |
-
2008
- 2008-10-07 KR KR1020080098089A patent/KR20100038927A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |