KR20100028406A - Method for manufacuring semiconductor device - Google Patents

Method for manufacuring semiconductor device Download PDF

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Publication number
KR20100028406A
KR20100028406A KR1020080087428A KR20080087428A KR20100028406A KR 20100028406 A KR20100028406 A KR 20100028406A KR 1020080087428 A KR1020080087428 A KR 1020080087428A KR 20080087428 A KR20080087428 A KR 20080087428A KR 20100028406 A KR20100028406 A KR 20100028406A
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KR
South Korea
Prior art keywords
pattern
layer
photoresist
forming
etching
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KR1020080087428A
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Korean (ko)
Inventor
김영식
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080087428A priority Critical patent/KR20100028406A/en
Publication of KR20100028406A publication Critical patent/KR20100028406A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/265—Selective reaction with inorganic or organometallic reagents after image-wise exposure, e.g. silylation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The present invention provides a method that can overcome the limitations of the pattern implementation due to the collapse of the pattern and the resolution limit as the aspect ratio of the pattern increases. In the method of manufacturing a semiconductor device according to the present invention, forming a protective film on the photoresist layer through a silicide process, forming a photoresist pattern by etching the exposed photoresist between the protective films, and forming a spacer on the photoresist pattern sidewalls. And etching the etched layer using the photoresist pattern and the spacer as a mask to form a fine pattern.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacuring Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a process for forming a highly integrated pattern in a semiconductor cell structure.

As the recent development of semiconductor device manufacturing technology and the application field of memory devices have been expanded, there is an urgent need to develop a technology for manufacturing a large-capacity memory device in which integration degree is improved and electrical characteristics are not degraded. Accordingly, various studies have been conducted to improve photo-lithography processes or to obtain stable process conditions by overcoming limitations such as cell structures, wiring forming materials, and insulating film forming materials. Among these, the photolithography process is an essential technology applied to the contact forming process or the pattern forming process for connecting the various layers constituting the device to each other, and the improvement of the photolithography process technology determines the success or failure of the highly integrated semiconductor device. Becomes

The photolithography process uses a principle of changing a property by causing a chemical reaction when a specific chemical (photo resist) receives light.However, by using a mask of a desired pattern, a photoresist is selectively injected to the light to mask the pattern of the mask. It is a process of forming in the same pattern as. The photolithography process is a coating process for applying a photoresist corresponding to a film of a general photograph, an exposure process for selectively scanning light using a mask, and a photoresist for removing a portion of the lighted portion using a developer to form a pattern. It consists of a developing process.

The photolithography process currently commercialized uses exposure equipment using short wavelength light sources such as KrF and ArF, and the resolution of the pattern obtained from such short wavelength light sources is limited to about 0.1 μm. Thus, it is very difficult to fabricate highly integrated semiconductor devices of smaller sized patterns.

In particular, a resist flow process using heat has been performed to reduce the size of a contact hole pattern, which is one of fine patterns included in a semiconductor device, using a conventional technology. However, in the resist flow process, even if the same energy is delivered to the front surface of the photoresist at a temperature higher than the glass transition temperature, the upper part of the pattern spreads more than the lower part because the photoresist flows relatively higher than the upper and middle parts of the photoresist. There is a problem that overflow occurs.

In addition, although a RELACS (Resist Enhancement Lithography Assisted by Chemical Shrink) process is used to form a fine pattern, the cost of the process material is high, and the water-soluble polymer used during the process is not completely removed and remains as a development residue on the pattern. This has the disadvantage of affecting subsequent etching processes. As a result, the RELACS process increases the probability of defects in the final device, leading to a decrease in yield and reliability of the semiconductor device.

As described above, the technology for reducing the size of the contact hole pattern is not yet complete. In addition, the development of the technology of the exposure equipment has also reached a limit point, the situation of technology development is delayed. In the case where fine patterns of non-uniform size are formed on the semiconductor substrate, the measurement accuracy of the critical dimension (CD) is reduced, thereby not only obtaining sufficient etching margin for performing a stable subsequent etching process, but also yielding final semiconductor device yield. This decreasing phenomenon occurs.

1A and 1B are photographic views illustrating problems of a method of manufacturing a semiconductor device according to the prior art.

Although FIG. 1A illustrates a pattern in which a pattern is normally patterned, FIG. 1B may show a phenomenon in which a pattern collapses due to an increase in aspect ratio of the pattern after the pattern is patterned.

In general, when forming a fine pattern in a semiconductor manufacturing process, a photoresist is applied to the upper portion of the layer to be etched through a photolithography process, followed by exposure and development to form a photoresist pattern, followed by an etching process using the photoresist pattern as an etching mask. Etching the exposed portion of the layer to be etched.

In performing the photolithography process, the developer used in the developing process in a situation in which it is difficult to maintain the pattern stably as the aspect ratio increases due to the decrease in the dimension of the pattern formed on the etched layer. developer) or rinse solution by rotation to cause the collapse of the pattern due to the surface tension of the liquid.

The conventional method of manufacturing a semiconductor device has a disadvantage in that a collapse of the pattern occurs as the aspect ratio increases, and a pattern having an appropriate size cannot be realized due to the limitation of resolution.

In order to solve the above-mentioned problems, the present invention forms a photoresist pattern including a silicide layer on an etched layer on a semiconductor substrate, and then forms a fine pattern by etching the etched layer using a spacer on the sidewall of the photoresist pattern. Provided is a method of manufacturing a semiconductor device that prevents the collapse of a pattern as the aspect ratio increases.

According to an embodiment of the present invention, a passivation layer is formed on the photoresist layer through a silicide process, etching the photoresist layer exposed between the passivation layers to form a photoresist pattern, forming a spacer on sidewalls of the photoresist pattern, and the photoresist pattern and the A method of manufacturing a semiconductor device includes forming a fine pattern by etching the etched layer using a spacer as a mask.

Preferably, forming the passivation layer on the photoresist layer through a silicide process includes etching a portion of the photoresist layer through an exposure and development process, and injecting a gas containing silicon into a region formed by etching a portion of the photoresist layer. And curing the silicon in the etched region by performing a heat treatment process.

Preferably, the etched layer includes at least one of an insulating film and a hard mask layer.

Preferably, the insulating film includes any one selected from an oxide film, a nitride film, and a combination thereof.

Preferably, the spacer is formed of a nitride film.

Preferably, the forming of the fine pattern may include removing the photoresist pattern and the spacer, forming a poly film on the entire surface including the etched layer, planarizing the poly film, and then etching the etched layer. And removing the first pillar pattern to form a second pillar pattern by etching the semiconductor substrate using the pillar pattern as a mask.

Preferably, the photoresist pattern and the spacer are removed using wet etching.

Preferably, the method may further include filling an oxide film between the second pillar patterns after forming the second pillar pattern.

The present invention forms a photoresist pattern including a silicide layer on an etched layer on a semiconductor substrate, and then forms a fine pattern by etching the etched layer using a spacer on the sidewall of the photoresist pattern so that the pattern collapses and the resolution is increased as the aspect ratio increases. By preventing the impossibility of pattern implementation due to limitations, semiconductor product development and process turn-around time (TAT) time is shortened.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and where it is mentioned that the layer is on another layer or substrate, it may be formed directly on another layer or substrate, or A third layer may be interposed between them.

Also, the same reference numerals throughout the specification represent the same components.

2 is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, in the semiconductor device, an oxide layer 395 is embedded between pillar-shaped pillar patterns 390, that is, active regions (not shown), to electrically isolate the pillar patterns 390. Has a structure. Hereinafter, a method of manufacturing a semiconductor device will be described in detail with reference to the cross-sectional views.

3A to 3I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention, and illustrate a cross-sectional view taken along line AA ′ of FIG. 2.

3A and 3B, after forming insulating layers 310 and 320 on the semiconductor substrate 300, a hard mask layer 330 is deposited on the insulating layers 310 and 320. Herein, the insulating films 310 and 320 preferably include any one selected from an oxide film, a nitride film, and a combination thereof.

Next, after forming the photosensitive film 340 containing silicon (Si) on the hard mask layer 330, using the mask defining the hole (Hole) to expose the photosensitive film 340 by an exposure process, and then heat treatment The process is performed to secure an area where the protective film 350 is to be formed. Subsequently, silicon is deposited on the area secured by scanning the gas containing silicon and the heat treatment process is performed again. Silicon is cured on the photoresist layer 340 through the Silation process to form a thin protective film 350 on the photoresist layer 340.

Referring to Figure 3c, O 2 on the entire surface including the protective film 350 The photoresist layer 340 is etched through the etching process using a plasma gas to form the photoresist pattern 345.

Referring to FIG. 3D, an insulating film for forming a spacer (not shown) is formed on the entire surface including the photosensitive film pattern 345 and an etchback process is performed on the sidewalls of the photosensitive film pattern 345. A spacer 360 is formed. At this time, the spacer 360 is preferably formed of a nitride film.

3E and 3F, after forming the spacer 360 on the sidewalls of the photoresist pattern 345, the hard mask layer 330 is etched to form the hard mask layer pattern 335. In this case, the passivation layer 350, the photoresist pattern 345, and the spacer 360 are used as an etch barrier for etching the hard mask layer 330.

Thereafter, the insulating layers 310 and 320 are etched using the hard mask layer pattern 335 as a mask to form holes 370 exposing the semiconductor substrate 300.

Referring to FIG. 3G, after the photoresist pattern 345, the spacer 360, and the hard mask layer pattern 335 are removed, the poly film 380 is formed on the entire surface including the insulating layers 320 and 310. In this case, the photoresist pattern 345, the spacer 360, and the hard mask layer pattern 335 are removed using a wet etching process. The protective film 350 formed on the photoresist pattern 345 may be a protective film. The photoresist pattern 345 and the hard mask layer pattern 335 are etched under the 350 and removed together.

Referring to FIG. 3H, after the poly film 380 is chemically mechanically polished, the insulating layers 320 and 310 are removed to form a first pillar pattern 385. In this case, the semiconductor substrate 300 is etched using the first pillar pattern 385 as a mask to form a trench, and a second pillar pattern 390 is formed between the trenches.

Thereafter, an oxide film 395 is buried between the second pillar patterns 390 to isolate the adjacent second pillar patterns 390 from each other.

As described above, the present invention forms a photoresist pattern including a passivation layer formed on the etching target layer on the semiconductor substrate by a silicide process, and then forms a fine pattern by etching the etched layer using a spacer on the sidewall of the photoresist pattern. Over time, semiconductor product development and turnaround time (TAT) time will be shortened by overcoming the pattern implementation due to the collapse of the pattern and the limitation of resolution as the aspect ratio increases.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A and 1B are photographic diagrams illustrating a method of manufacturing a semiconductor device according to the prior art.

2 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.

3A to 3I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Description of the symbols for the main parts of the drawings>

300: semiconductor substrate 310: oxide film

320: nitride film 330: hard mask layer

335: hard mask layer pattern 340: photosensitive film

345: photosensitive film pattern 350: protective film

360: spacer 370: hole

380: poly film 385: first pillar pattern

390: second pillar pattern 395: oxide film

Claims (8)

Forming a protective film on the photoresist film through a silicide process; Etching the exposed photoresist between the passivation layers to form a photoresist pattern; Forming a spacer on sidewalls of the photoresist pattern; And Etching a layer to be etched using the photoresist pattern and the spacer as a mask to form a fine pattern Method for manufacturing a semiconductor device comprising a. The method of claim 1, The forming of the passivation layer on the photoresist layer through the silicide process Performing an exposure process and a first heat treatment process on a region where the protective film is to be formed; Injecting a gas containing silicon into a region where the exposure process and the first heat treatment process are performed; And Hardening the silicon in the region by performing a second heat treatment process. The method of claim 1, The etched layer may include at least one of an insulating film and a hard mask layer. The method of claim 3, wherein And the insulating film includes any one selected from an oxide film, a nitride film, and a combination thereof. The method of claim 1, And the spacer is formed of a nitride film. The method of claim 1, Forming the fine pattern is Removing the photoresist pattern and the spacer; Forming a polysilicon film on the entire surface including the etched layer; Forming a first pillar pattern by removing the etching layer after planarization etching the polysilicon layer; And And etching the semiconductor substrate using the first pillar pattern as a mask to form a second pillar pattern. The method of claim 6, The photosensitive film pattern and the spacer is a method of manufacturing a semiconductor device, characterized in that by using a wet etching. The method of claim 6, And forming an oxide film between the second pillar patterns after forming the second pillar pattern.
KR1020080087428A 2008-09-04 2008-09-04 Method for manufacuring semiconductor device KR20100028406A (en)

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