KR20090116062A - Method for forming landing plug contact in semiconductor device - Google Patents

Method for forming landing plug contact in semiconductor device Download PDF

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KR20090116062A
KR20090116062A KR1020080041746A KR20080041746A KR20090116062A KR 20090116062 A KR20090116062 A KR 20090116062A KR 1020080041746 A KR1020080041746 A KR 1020080041746A KR 20080041746 A KR20080041746 A KR 20080041746A KR 20090116062 A KR20090116062 A KR 20090116062A
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landing plug
plug contact
conductive layer
forming
etching
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KR1020080041746A
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Korean (ko)
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이명신
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Abstract

PURPOSE: A method for forming a landing plug contact of a semiconductor device is provided to implement insulation between contact plugs by etching an upper side of a conductive layer using a wet etchant. CONSTITUTION: A plurality of gate patterns(110) are formed on a semiconductor substrate(100). An interlayer insulation layer(130) covering the gate pattern is formed. An opening to expose the semiconductor substrate is formed by etching the interlayer insulation layer of the region to form a landing plug contact(160a). A conductive layer is formed to fill the opening. The conductive layer is etched back to remain in the only opening. The landing plug contact is formed by wet etching the upper side of the conductive layer.

Description

반도체 소자의 랜딩 플러그 컨택 형성방법{Method for forming landing plug contact in semiconductor device}Method for forming landing plug contact in semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 랜딩 플러그 컨택을 신뢰성있게 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for reliably forming a landing plug contact of a semiconductor device.

반도체 메모리소자, 예컨대 디램(DRAM)의 집적도가 높아지고 제조기술의 수준 또한 높아지면서 여러 가지 공정조건들은 더욱 까다로워졌다. 예컨대, 비트라인 또는 스토리지 전극과 같은 상부 도전층과 반도체기판을 접속시키기 위한 랜딩 플러그 컨택(Landing Plug Contact, LPC)의 경우에도, 랜딩 플러그 컨택(LPC)이 오픈되지 않는 현상을 개선하기 위하여 과도한 식각조건이 적용되고 있는 상황이다. As the degree of integration of semiconductor memory devices, such as DRAM, and the level of manufacturing technology have increased, various process conditions have become more difficult. For example, even in the case of a landing plug contact (LPC) for connecting an upper conductive layer, such as a bit line or a storage electrode, to a semiconductor substrate, the excessive etching to improve the phenomenon that the landing plug contact (LPC) does not open. The condition is being applied.

랜딩 플러그 컨택(LPC)을 형성하기 위해서는 먼저, 반도체기판 상에 하드마스크를 포함하는 게이트 패턴들을 형성하고 이 게이트 패턴들 사이를 분리시키기 위한 층간절연막을 증착한 후, 하드마스크의 표면이 노출될 때까지 층간절연막에 대해 화학적기계적연마(CMP) 공정을 실시한다. 다음에, 층간절연막을 식각하여 컨 택홀을 형성하고, 이 컨택홀을 도전물질로 매립함으로써 랜딩 플러그 컨택을 형성하게 된다. 그런데, 상기 층간절연막에 대한 CMP 공정에서 랜딩 플러그 컨택(LPC)을 위한 컨택홀이 오픈되지 않는 현상을 개선하기 위하여 과도 식각조건으로 실시하게 된다. 그 결과, 게이트 하드마스크로 사용되는 질화막의 손실량이 증가하게 되고, 결국 랜딩 플러그 컨택 사이를 절연시키기 위하여 수행되는 CMP 공정의 마진 부족에 의해 스토리지 노드 컨택 불량, 랜딩 플러그 컨택 브리지 불량 등이 큰 문제로 대두되고 있다.In order to form a landing plug contact (LPC), first, gate patterns including a hard mask are formed on a semiconductor substrate, and an interlayer insulating layer is deposited to separate the gate patterns, and then the surface of the hard mask is exposed. The chemical mechanical polishing (CMP) process is performed on the interlayer insulating film. Next, a contact hole is formed by etching the interlayer insulating film, and the landing plug contact is formed by filling the contact hole with a conductive material. However, in order to improve the phenomenon that the contact hole for the landing plug contact (LPC) is not opened in the CMP process with respect to the interlayer insulating layer, the etching process is performed under a transient etching condition. As a result, the loss amount of the nitride film used as the gate hard mask is increased, and the storage node contact failure and the landing plug contact bridge defect are large problems due to the lack of margin of the CMP process performed to insulate the landing plug contacts. It is emerging.

본 발명이 이루고자 하는 기술적 과제는 컨택 불량 및 컨택 브리지와 같은 문제가 발생하지 않도록 하는 반도체 소자의 랜딩 플러그 컨택 형성방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming a landing plug contact of a semiconductor device such that problems such as a defective contact and a contact bridge do not occur.

상기 기술적 과제를 달성하기 위하여 본 발명에 따른 반도체 소자의 랜딩 플러그 컨택 형성방법은, 반도체기판 상에 복수 개의 게이트 패턴을 형성하는 단계와, 게이트 패턴을 덮는 층간절연막을 형성하는 단계와, 랜딩 플러그 컨택이 형성될 영역의 층간절연막을 식각하여 반도체기판을 노출시키는 개구부를 형성하는 단계와, 개구부가 매립되도록 결과물 상에 도전층을 형성하는 단계와, 개구부 내에만 남도록 도전층을 에치백하는 단계, 및 도전층의 상부를 습식식각하여 랜딩 플러그 컨택을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a landing plug contact of a semiconductor device, the method comprising: forming a plurality of gate patterns on a semiconductor substrate, forming an interlayer insulating layer covering the gate pattern, and landing plug contacts; Etching the interlayer insulating film in the region to be formed to form an opening for exposing the semiconductor substrate, forming a conductive layer on the resultant so that the opening is embedded, etching back the conductive layer so as to remain only in the opening, and Wet etching the upper portion of the conductive layer to form a landing plug contact.

상기 층간절연막 상에, 하드마스크를 형성하는 단계를 더 포함할 수 있다.The method may further include forming a hard mask on the interlayer insulating layer.

상기 하드마스크는 아몰퍼스 카본막과 테오스(TEOS)막의 이중막으로 형성할 수 있다.The hard mask may be formed as a double film of an amorphous carbon film and a TEOS film.

상기 도전층을 에치백하는 단계 후에, 랜딩 플러그 컨택이 형성될 영역과 이외의 영역 사이의 평탄화를 위한 화학적기계적연마(CMP) 공정을 실시할 수 있다. 이때, 상기 화학적기계적연마(CMP) 공정은, 폴리실리콘막과 질화막에 대한 연마량 이 1:20인 슬러리를 사용하여 진행할 수 있다.After etching back the conductive layer, a chemical mechanical polishing (CMP) process may be performed to planarize the region between the region where the landing plug contact is to be formed and the region other than that. In this case, the chemical mechanical polishing (CMP) process may be performed using a slurry having a polishing amount of 1:20 for the polysilicon film and the nitride film.

상기 도전층의 상부를 습식식각하는 단계에서, 질산(HNO3)과 불산(HF)의 혼합용액을 사용할 수 있다. 상기 질산(HNO3)과 불산(HF)의 혼합비를 1:0 ∼ 1:1로 하는 것이 바람직하다.In the wet etching of the upper portion of the conductive layer, a mixed solution of nitric acid (HNO 3 ) and hydrofluoric acid (HF) may be used. The mixing ratio of nitric acid (HNO 3 ) and hydrofluoric acid (HF) is preferably 1: 0 to 1: 1.

상기 도전층의 상부를 습식식각하여 랜딩 플러그 컨택을 형성하는 단계 후에, 상기 도전층의 상부를 인산(H3PO4) 용액을 사용하여 세정하는 단계를 더 포함할 수 있다.After forming the landing plug contact by wet etching the upper portion of the conductive layer, the upper portion of the conductive layer may be further cleaned using a phosphoric acid (H 3 PO 4 ) solution.

본 발명에 의한 반도체 소자의 랜딩 플러그 컨택 형성방법에 따르면, 랜딩 플러그 컨택홀 내에 도전막을 증착한 다음 에치백과 CMP를 실시하고, 습식식각 용액을 이용하여 상기 도전막의 상부를 식각함으로써, 컨택 플러그들 사이의 절연을 용이하게 하고 게이트 하드마스크의 마진을 충분히 확보할 수 있다.According to the method for forming a landing plug contact of a semiconductor device according to the present invention, a conductive film is deposited in a landing plug contact hole, followed by etch back and CMP, and an upper portion of the conductive film is etched using a wet etching solution, thereby forming contact between the contact plugs. Can be easily insulated and a sufficient margin of the gate hard mask can be secured.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되는 것으로 해석되어서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 1 내지 도 5는 본 발명에 따른 반도체 소자의 랜딩 플러그 컨택 형성방법을 설명하기 위한 단면도들이다.1 to 5 are cross-sectional views illustrating a method for forming a landing plug contact of a semiconductor device according to the present invention.

도 1을 참조하면, 소자분리막(102)에 의해 활성영역이 정의된 반도체기판(100) 상에, 게이트 패턴(110)을 형성한다. 게이트 패턴(110)은, 예를 들어 산화막으로 이루어진 게이트절연막(112), 예를 들어 도핑된 폴리실리콘막으로 이루어진 도전층(114), 예를 들어 텅스텐실리사이드막으로 이루어진 저저항층(116) 및 예를 들어 질화막으로 이루어진 하드마스크(118)을 차례로 적층한 후 이방성식각을 수행하여 형성할 수 있다. 상기 게이트 패턴(110)의 측벽에 절연막 스페이서(120)를 형성한다. 결과물 상에, 상기 게이트 패턴(110)들을 덮도록 산화막을 증착하여 층간절연막(130)을 형성한다. 다음에, 상기 층간절연막(130)에 대해 CMP 공정을 실시한다. 이때, 상기 층간절연막(130)에 대한 CMP 공정은 게이트 패턴의 하드마스크(118)의 표면이 노출될 때까지 실시한다.Referring to FIG. 1, a gate pattern 110 is formed on a semiconductor substrate 100 in which an active region is defined by an isolation layer 102. The gate pattern 110 includes, for example, a gate insulating film 112 made of an oxide film, a conductive layer 114 made of a doped polysilicon film, for example, a low resistance layer 116 made of a tungsten silicide film, and For example, it may be formed by sequentially stacking the hard mask 118 made of a nitride film and then performing anisotropic etching. An insulating layer spacer 120 is formed on sidewalls of the gate pattern 110. On the resultant, an oxide film is deposited to cover the gate patterns 110 to form an interlayer insulating film 130. Next, a CMP process is performed on the interlayer insulating film 130. In this case, the CMP process on the interlayer insulating layer 130 is performed until the surface of the hard mask 118 of the gate pattern is exposed.

도 2를 참조하면, 랜딩 플러그 컨택 형성을 위한 사진 및 식각공정에서 양호한 랜딩 플러그 컨택 프로파일을 얻기 위하여, 층간절연막(130)이 평탄화된 결과물 상에 아몰퍼스 카본(amophous carbon)막(142)과 테오스(TEOS)막(144)을 차례로 증착하여 제2 하드마스크를(140)를 형성한다. 상기 제2 하드마스크(140) 상에, 랜딩 플러그 컨택이 형성될 영역을 한정하는 포토레지스트 패턴(150)을 형성한다. 포토레지스트 패턴(150)을 마스크로 하여 제2 하드마스크, 즉 TEOS막(144)과 아몰퍼스 카본막(142)을 차례로 식각하여 랜딩 플러그 컨택이 형성될 영역의 층간절연막(130)이 노출되도록 한다.Referring to FIG. 2, in order to obtain a good landing plug contact profile in the photolithography and etching process for forming the landing plug contact, the amorphous carbon film 142 and theos are formed on the resultant of the planarization of the interlayer insulating film 130. The second hard mask 140 is formed by sequentially depositing the (TEOS) film 144. A photoresist pattern 150 is formed on the second hard mask 140 to define a region in which the landing plug contact is to be formed. The second hard mask, that is, the TEOS film 144 and the amorphous carbon film 142 are sequentially etched using the photoresist pattern 150 as a mask to expose the interlayer insulating film 130 in the region where the landing plug contact is to be formed.

도 3을 참조하면, 노출된 영역의 층간절연막(130)을 식각하여 랜딩 플러그 컨택을 형성하기 위한 컨택홀을 형성한다. 이때, 컨택홀이 형성되는 영역의 게이트 하드마스크(118)의 일부가 식각된다. 다음에, 상기 컨택홀이 매립되도록 결과물 상에 도전층(160), 예를 들어 도핑된 폴리실리콘막을 일정 두께 형성한다. 다음에, 상기 도전층(160)에 대해 에치백을 실시하여 랜딩 플러그 컨택이 형성될 영역에만 상기 도전층(160)이 남도록 한다.Referring to FIG. 3, a contact hole for forming a landing plug contact is formed by etching the interlayer insulating layer 130 in the exposed region. At this time, a portion of the gate hard mask 118 in the region where the contact hole is formed is etched. Next, a conductive layer 160, for example, a doped polysilicon film, is formed on the resultant material to fill the contact hole. Next, the conductive layer 160 is etched back so that the conductive layer 160 remains only in the region where the landing plug contact is to be formed.

도 4를 참조하면, 랜딩 플러그 컨택이 형성될 영역의 도전층(160)과 그 외의 영역의 평탄화를 위하여, 결과물에 대해 CMP 공정을 실시한다. 이때, 폴리실리콘막과 질화막에 대한 선택비가 좋은 슬러리를 사용하여 CMP 공정을 진행한다. 바람직하게는, 폴리실리콘막과 질화막에 대한 연마량의 비가 1:20인 슬러리를 사용할 수 있다. 이때, 상기 폴리실리콘막은 50Å 이내로 연마되도록 한다.Referring to FIG. 4, the CMP process is performed on the resultant to planarize the conductive layer 160 and other regions of the region where the landing plug contact is to be formed. At this time, the CMP process is performed using a slurry having good selectivity for the polysilicon film and the nitride film. Preferably, a slurry in which the ratio of the polishing amount to the polysilicon film and the nitride film is 1:20 can be used. At this time, the polysilicon film is polished to within 50 kPa.

이 과정에서 랜딩 플러그 컨택이 형성되지 않는 영역의 층간절연막(130)과 제1 하드마스크(118)의 일부가 제거되어 평탄화가 이루어진다.In this process, a portion of the interlayer insulating layer 130 and the first hard mask 118 in a region where the landing plug contact is not formed are removed to planarize.

도 5를 참조하면, 랜딩 플러그 컨택 사이를 분리시키기 위하여 상기 도전층에 대한 식각을 실시한다. 이때, 식각제로는 상기 도전층을 구성하는 물질, 즉 폴리실리콘막과 제1 하드마스크(118)를 구성하는 질화막 사이에 식각 선택비가 좋은 물질을 사용한다. 이러한 물질로는 질산(HNO3)과 불산(HF)의 혼합용액을 사용할 수 있는데, 질산(HNO3)과 불산(HF)의 혼합비를 1:0 ∼ 1:1 정도로 하는 것이 바람직하다. 그리고, 불산(HF)은 탈이온수와 불산이 100:1로 희석된 것으로 사용하며, 식각공정의 온도는 25 ∼ 35℃ 정도가 적당하다.Referring to FIG. 5, the conductive layer is etched to separate landing plug contacts. In this case, as an etchant, a material constituting the conductive layer, that is, a material having a good etching selectivity between the polysilicon film and the nitride film constituting the first hard mask 118 is used. As such a substance, a mixed solution of nitric acid (HNO 3) and hydrofluoric acid (HF) may be used, and the mixing ratio of nitric acid (HNO 3) and hydrofluoric acid (HF) is preferably 1: 0 to 1: 1. In addition, hydrofluoric acid (HF) is used in which deionized water and hydrofluoric acid are diluted to 100: 1, and the temperature of the etching process is preferably about 25 to 35 ° C.

상기 혼합용액을 사용하여 도전층을 게이트 패턴의 높이보다 낮아지도록 식각함으로써 랜딩 플러그 컨택들(160a)이 서로 전기적으로 분리된다. 랜딩 플러그 컨택들(160a) 사이의 전기적 분리에 대한 신뢰성을 확보하기 위하여 인산(H3PO4) 용액을 사용한 세정을 추가로 실시할 수 있다. 이때, 제1 하드마스크(118)의 식각량이 50Å 이내가 되도록 조절한다.The landing plug contacts 160a are electrically separated from each other by etching the conductive layer to be lower than the height of the gate pattern using the mixed solution. In order to secure the reliability of the electrical separation between the landing plug contacts 160a, cleaning using a phosphoric acid (H 3 PO 4) solution may be further performed. At this time, the etching amount of the first hard mask 118 is adjusted to be within 50 dB.

이와 같이 본 발명에 따르면, 랜딩 플러그 컨택홀 내에 폴리실리콘막을 증착하고 에치백을 실시한 후 CMP를 실시하고, 습식식각 용액을 이용하여 폴리실리콘막의 상부를 식각함으로써 컨택 플러그 사이의 절연을 용이하게 하고 게이트 하드마스크의 마진을 충분히 확보할 수 있다.As described above, according to the present invention, the polysilicon film is deposited in the landing plug contact hole, the etching back is performed, and then the CMP is performed. The margin of the hard mask can be secured enough.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

도 1 내지 도 5는 본 발명에 따른 반도체 소자의 랜딩 플러그 컨택 형성방법을 설명하기 위한 단면도들이다.1 to 5 are cross-sectional views illustrating a method for forming a landing plug contact of a semiconductor device according to the present invention.

Claims (8)

반도체기판 상에 복수 개의 게이트 패턴을 형성하는 단계;Forming a plurality of gate patterns on the semiconductor substrate; 상기 게이트 패턴을 덮는 층간절연막을 형성하는 단계;Forming an interlayer insulating film covering the gate pattern; 랜딩 플러그 컨택이 형성될 영역의 상기 층간절연막을 식각하여 상기 반도체기판을 노출시키는 개구부를 형성하는 단계;Etching the interlayer insulating film in a region where a landing plug contact is to be formed to form an opening exposing the semiconductor substrate; 상기 개구부가 매립되도록 결과물 상에 도전층을 형성하는 단계;Forming a conductive layer on a resultant to fill the opening; 상기 개구부 내에만 남도록 상기 도전층을 에치백하는 단계; 및Etching back the conductive layer so as to remain only in the opening; And 상기 도전층의 상부를 습식식각하여 랜딩 플러그 컨택을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.And forming a landing plug contact by wet etching an upper portion of the conductive layer. 제1항에 있어서,The method of claim 1, 상기 층간절연막 상에, 하드마스크를 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.And forming a hard mask on the interlayer insulating layer. 제2항에 있어서,The method of claim 2, 상기 하드마스크는 아몰퍼스 카본막과 테오스(TEOS)막의 이중막으로 형성하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.The hard mask may be formed of a double layer of an amorphous carbon film and a TEOS film. 제1항에 있어서,The method of claim 1, 상기 도전층을 에치백하는 단계 후에, 랜딩 플러그 컨택이 형성될 영역과 이외의 영역 사이의 평탄화를 위한 화학적기계적연마(CMP) 공정을 실시하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.After the step of etching back the conductive layer, a chemical mechanical polishing (CMP) process for planarization between a region where the landing plug contact is to be formed and a region other than the region where the landing plug contact is to be formed. 제4항에 있어서,The method of claim 4, wherein 상기 화학적기계적연마(CMP) 공정은, 폴리실리콘막과 질화막에 대한 연마량의 비가 1:20인 슬러리를 사용하여 진행하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.The chemical mechanical polishing (CMP) process is a landing plug contact forming method of a semiconductor device, characterized in that the progress of the slurry using a 1:20 ratio of the polishing amount to the polysilicon film and the nitride film. 제1항에 있어서,The method of claim 1, 상기 도전층의 상부를 습식식각하는 단계에서, 질산(HNO3)과 불산(HF)의 혼합용액을 사용하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.And wet etching the upper portion of the conductive layer, using a mixed solution of nitric acid (HNO 3 ) and hydrofluoric acid (HF). 제6항에 있어서,The method of claim 6, 상기 질산(HNO3)과 불산(HF)의 혼합비를 1:0 ∼ 1:1로 하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.And a mixing ratio of nitric acid (HNO 3 ) and hydrofluoric acid (HF) in a range of 1: 0 to 1: 1. 제1항에 있어서,The method of claim 1, 상기 도전층의 상부를 습식식각하여 랜딩 플러그 컨택을 형성하는 단계 후에,After the wet etching the upper portion of the conductive layer to form a landing plug contact, 상기 도전층의 상부를 인산(H3PO4) 용액을 사용하여 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 컨택 형성방법.And cleaning the upper portion of the conductive layer using a phosphoric acid (H 3 PO 4 ) solution.
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Publication number Priority date Publication date Assignee Title
US11152368B2 (en) 2019-11-19 2021-10-19 Samsung Electronics Co., Ltd. Semiconductor device including storage node electrode having filler and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11152368B2 (en) 2019-11-19 2021-10-19 Samsung Electronics Co., Ltd. Semiconductor device including storage node electrode having filler and method for manufacturing the same

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