KR20090104378A - Method for fabricating multi-layer using anodizing - Google Patents

Method for fabricating multi-layer using anodizing Download PDF

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KR20090104378A
KR20090104378A KR1020080029778A KR20080029778A KR20090104378A KR 20090104378 A KR20090104378 A KR 20090104378A KR 1020080029778 A KR1020080029778 A KR 1020080029778A KR 20080029778 A KR20080029778 A KR 20080029778A KR 20090104378 A KR20090104378 A KR 20090104378A
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metal layer
layer
photoresist pattern
metal
interlayer insulating
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KR100939273B1 (en
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서수정
임승규
박인수
나성훈
김진수
김태성
염광섭
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성균관대학교산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A multilayer manufacturing method using the anode oxidation is provided to apply the aluminum oxide to the interlayer dielectric layer and to improve the high electrical characteristic of insulation performance. CONSTITUTION: The multilayer manufacturing method using the anode oxidation comprises as follows. The first metal layer is formed in the surface of a substrate(S1). The first circuit has the first part oxidative region and the first metal wirings by oxidizing the first metal layer partially. The interlayer dielectric layer is formed by anodizing extensively the first metal layer and the first part oxidative region(S3). The penetration hole is formed by partially etching the interlayer dielectric layer. The second metal layer is formed within the surface and penetration hole of the interlayer dielectric layer(S5). The second circuit has the second part oxidative region and the second metal wirings.

Description

양극산화를 이용한 멀티레이어 제조방법{METHOD FOR FABRICATING MULTI-LAYER USING ANODIZING}Multi-layer manufacturing method using anodization {METHOD FOR FABRICATING MULTI-LAYER USING ANODIZING}

본 발명은 반도체 패키징 또는 디스플레이 분야 등에 이용되는 멀티레이어에 관한 것이며, 보다 상세하게는 보다 간단한 공정 내지 적은 비용으로 멀티레이어를 제조할 수 있는, 양극산화를 이용한 멀티레이어 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multilayers used in the field of semiconductor packaging or display, and more particularly, to a multilayer manufacturing method using anodization, which can produce multilayers in a simpler process or at a lower cost.

반도체 패키징 또는 COG(칩온글라스)기판 등과 같은 디스플레이 분야는 고성능화 내지 고집적화에 따라 멀티레이어이 필수적으로 사용된다. 이러한 멀티레이어은 다층의 금속배선구조로 이루어지고, 상부 및 하부의 금속배선들 사이에는 층간절연층이 개재된다. In the field of display such as semiconductor packaging or COG (chip-on-glass) substrate, multilayers are essentially used according to high performance and high integration. The multilayer has a multi-layered metal wiring structure, and an interlayer insulating layer is interposed between upper and lower metal wirings.

그리고 멀티레이어에서는 단차가 심하게 발생되므로, 하부 금속배선과 상부 금속배선 사이 층간절연층의 상부에는 평탄화를 목적으로 SOG막(또는 폴리이미드층)을 형성한 다음, SOG막과 층간절연층과의 식각선택비를 결정하여서 SOG막의 예정된 두께를 에치백(etch back)함으로써 평탄하게 형성한 다음, (여기서 하부 금속배선의 단차가 낮은 부분에서는 SOG막이 두껍게 형성되고, 하부 금속배선의 단차가 높은 부분에서는 SOG막이 얇게 형성된다.) 평탄화된 SOG막 상부에 예정두께의 층간 절연층을 형성하고, 이어서 상부 금속배선과 하부 금속배선이 접할 부분의 층간절연층을 제거하여 다수의 관통홀을 형성한다. 이때 관통홀의 깊이가 다를 경우 단차가 높은 하부 도전층은 단차가 낮은 하부 도전층이 노출되기까지 층간절연층 식각공정에 노출된 상태로 유지되기 때문에, 단차가 높은 도전층의 표면이 손상을 입게 된다. 또 관통홀이 깊은 하부 도전층에서는 상부 도전층과 접할 때 스텝커버리지가 불량하여 소자의 신뢰성이 저하되는 문제점이 발생한다.In the multilayer, since the step is severely generated, an SOG film (or a polyimide layer) is formed on the upper part of the interlayer insulating layer between the lower metal wiring and the upper metal wiring for the purpose of flattening, and then the etching of the SOG film and the interlayer insulating layer is performed. The selectivity ratio was determined to etch back the predetermined thickness of the SOG film to form a flat surface (where the SOG film was formed thick in the lower stepped portion of the lower metallization, and the SOG film was formed in the higher stepped level of the lower metallization). A thin film is formed.) An interlayer insulating layer having a predetermined thickness is formed on the planarized SOG film, and then a plurality of through holes are formed by removing the interlayer insulating layer in a portion where the upper metal wiring and the lower metal wiring are in contact. In this case, if the depth of the through-holes is different, the lower conductive layer having a high level of step remains exposed to the interlayer insulating layer etching process until the lower conductive layer having a low level is exposed, thereby damaging the surface of the conductive layer having a high level of step. . In addition, in the lower conductive layer having a deep through hole, the step coverage is poor when the upper conductive layer is in contact with the lower conductive layer.

한편, 이러한 종래의 멀티레이어 제조방법에서 층간절연층은 SiO2, DSG(SiOF), TFOS, BPSG 등의 재질로 이루어지고, 이들은 CVD 또는 PVD 등을 통해 증착된다. 그렇기 때문에, 종래의 멀티레이어 제조방법은 층간절연층의 증착 시에 전체 분위기를 진공상태로 만드는 진공프로세스가 필수적으로 요구되는 등 전체 제조비용을 상승시키는 단점이 있었다. On the other hand, in such a conventional multilayer manufacturing method, the interlayer insulating layer is made of a material such as SiO 2 , DSG (SiOF), TFOS, BPSG, etc., which are deposited through CVD or PVD. Therefore, the conventional multilayer manufacturing method has the disadvantage of increasing the overall manufacturing cost, such as the need for a vacuum process to make the entire atmosphere in a vacuum state when the interlayer insulating layer is deposited.

본 발명은 상기와 같은 점을 감안하여 발명된 것으로서, 양극산화공정을 통해 층간절연층 및 각 층의 회로 패턴 등을 형성함으로써 제조공정을 매우 단순화할 수 있고, 또한 미세한 피치의 금속배선을 형성할 수 있는, 양극산화를 이용한 멀티레이어 제조방법을 제공하는 데 목적이 있다. The present invention has been invented in view of the above, and by forming an interlayer insulating layer and a circuit pattern of each layer through anodization, the manufacturing process can be greatly simplified, and fine pitch metal wiring can be formed. It is an object of the present invention to provide a multilayer manufacturing method using anodization.

상기 목적을 달성하기 위한 본 발명의 양극산화를 이용한 멀티레이어 제조방 법은, The multilayer production method using the anodization of the present invention for achieving the above object,

기판의 표면에 제1금속층을 형성하는 제1단계;Forming a first metal layer on a surface of the substrate;

상기 제1금속층을 부분적으로 양극산화시킴으로써 제1부분산화영역 및 제1금속배선을 가지는 제1회로를 형성하는 제2단계;Forming a first circuit having a first partial oxidation region and a first metal wiring by partially anodizing the first metal layer;

상기 제1금속층 및 제1부분산화영역을 전면적으로 양극산화시킴으로써 층간절연층을 형성하는 제3단계;A third step of forming an interlayer insulating layer by anodizing the first metal layer and the first partial oxidation region entirely;

상기 층간절연층을 부분적으로 에칭함으로써 하나 이상의 관통홀을 형성하는 제4단계;A fourth step of forming at least one through hole by partially etching the interlayer insulating layer;

상기 층간절연층의 표면 및 관통홀 내에 제2금속층을 형성하는 제5단계; 및 A fifth step of forming a second metal layer in a surface of the interlayer insulating layer and through holes; And

상기 제2금속층의 표면을 부분적으로 양극산화시킴으로서 제2부분산화영역 및 제2금속배선을 가지는 제2회로를 형성하는 제6단계를 포함한다. And partially forming the second circuit having the second partial oxidation region and the second metal wiring by partially anodizing the surface of the second metal layer.

이와 같이 본 발명은 금속층의 부분적인 양극산화 내지 전면적인 양극산화공정을 통해 다층 배선구조를 보다 용이하게 형성시킬 수 있고, 또한 종래기술과 달리 절연층의 증착 내지 에칭 시에 요구되는 진공프로세스가 감소함에 따라 공정비용을 대폭 절감할 수 있는 장점이 있다. As described above, the present invention can more easily form a multilayer wiring structure through partial anodization or full anodization of the metal layer, and unlike the prior art, the vacuum process required for deposition or etching of the insulating layer is reduced. As a result, the process cost can be greatly reduced.

상기 제2단계에서는, 상기 제1금속층의 표면에 제1포토레지스트패턴을 형성하고, 상기 제1포토레지스트패턴을 통해 상기 제1금속층을 부분적으로 양극산화시킴으로써 제1부분산화영역 및 제1금속배선을 형성시킨 후에 상기 제1포토레지스트 패턴을 제거한다. In the second step, a first photoresist pattern is formed on the surface of the first metal layer, and the first partial oxidation region and the first metal wiring are formed by partially anodizing the first metal layer through the first photoresist pattern. After the formation of the first photoresist pattern is removed.

제4단계에서는, 상기 제1층간절연층의 표면에 제2포토레지스트패턴을 형성하 고, 상기 제2포토레지스트패턴을 통해 상기 제1층간절연층을 부분적으로 에칭함으로써 관통홀을 형성시킨 후에 제2포토레지스트패턴을 제거한다. In the fourth step, a second photoresist pattern is formed on the surface of the first interlayer insulating layer, and the through hole is formed by partially etching the first interlayer insulating layer through the second photoresist pattern. 2 Remove the photoresist pattern.

제6단계는, 상기 제2금속층의 표면에 제3포토레지스트패턴을 형성하고, 상기 제3포토레지스트패턴을 통해 상기 제2금속층을 부분적으로 양극산화시킴으로써 제2부분산화층 및 제2금속배선을 형성시킨 후에 상기 제3포토레지스트패턴을 제거한다.In a sixth step, a third photoresist pattern is formed on the surface of the second metal layer, and the second metal oxide layer and the second metal wiring are formed by partially anodizing the second metal layer through the third photoresist pattern. After the removal, the third photoresist pattern is removed.

한편 제1 및 제2 금속층은 알루미늄이고, 상기 제1 및 제2 부분산화영역과 층간절연층은 알루미나이다. Meanwhile, the first and second metal layers are aluminum, and the first and second partial oxidation regions and the interlayer insulating layer are alumina.

또 제2회로의 표면에 상기 제3 내지 제6단계는 1번 이상 반복적으로 수행될 수 있다.In addition, the third to sixth steps may be repeatedly performed one or more times on the surface of the second circuit.

이상과 같은 본 발명은, 양극산화공정을 통해 층간절연막 내지 각 층의 회로패턴을 형성함으로써 제조공정을 매우 단순화할 수 있고, 또한 미세한 피치의 다층 금속배선을 형성할 수 있다. The present invention as described above can greatly simplify the manufacturing process by forming the interlayer insulating film or the circuit pattern of each layer through the anodization process, and it is possible to form a multilayer metal wiring with a fine pitch.

또한, 본 발명은 층간절연층에 산화알루미늄을 적용함으로써 절연성능을 더욱 향상시켜 높은 전기적 특성을 제공할 수 있는 장점이 있다. In addition, the present invention has the advantage that by applying aluminum oxide to the interlayer insulating layer to further improve the insulating performance to provide a high electrical characteristics.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 14는 본 발명에 의한 양극산화를 이용한 멀티레이어 제조방법 을 도시한다.1 to 14 illustrate a multilayer manufacturing method using anodization according to the present invention.

도 1을 참조하여 전체적인 공정을 간단히 설명하면, 먼저 기판(10)의 표면에 제1금속층(11)을 형성하고(S1), 상기 제1금속층(11)을 부분적으로 양극산화시킴으로써 도 5에 나타난 바와 같은 제1부분산화영역(11a) 및 제1금속배선(11b)을 가진 제1회로를 형성한다(S2). 다음으로 제1부분산화영역(11a) 및 제1금속배선(11b)을 전면적으로 양극산화시킴으로써 층간절연층(13)을 형성시킨다(S3). 이어서 층간절연층(13)을 부분적으로 에칭함으로써 관통홀(15)을 형성시키며(S4), 상기 층간절연층(13)의 표면 및 관통홀(15) 내에 제2금속층(16)을 형성시키고(S5), 상기 제2금속층(16)의 표면을 부분적으로 양극산화시킴으로서 제2부분산화영역(16a) 및 제2금속배선(16b)을 가진 제2회로를 형성(S6)시킨다. Referring to FIG. 1, the overall process will be briefly described. First, a first metal layer 11 is formed on a surface of a substrate 10 (S1), and the first metal layer 11 is partially anodized, as shown in FIG. 5. A first circuit having the first partial oxidation region 11a and the first metal wiring 11b as described above is formed (S2). Next, the interlayer insulating layer 13 is formed by anodizing the first partial oxidation region 11a and the first metal wiring 11b entirely (S3). Subsequently, the through hole 15 is formed by partially etching the interlayer insulating layer 13 (S4), and the second metal layer 16 is formed in the surface of the interlayer insulating layer 13 and the through hole 15 ( S5) and partially anodize the surface of the second metal layer 16 to form a second circuit having a second partial oxidation region 16a and a second metal wiring 16b (S6).

이하, 각 공정을 도 2 내지 도 14를 참조하여 보다 상세히 설명한다. Hereinafter, each process will be described in more detail with reference to FIGS. 2 to 14.

도 2 및 도 3에 나타난 바와 같이, 준비된 기판(10)의 표면에 제1금속층(11)을 이베포레이션 공정에 의해 균일한 두께로 증착한다(S1). 여기서, 제1금속층(11)은 알루미늄이다. 2 and 3, the first metal layer 11 is deposited on the surface of the prepared substrate 10 to a uniform thickness by an evaporation process (S1). Here, the first metal layer 11 is aluminum.

그리고 도 4에 도시된 바와 같이 제1금속층(11)의 표면에 제1포토레지스트패턴(12)을 형성하고, 이어서 제1금속층(11)에 양극산화공정을 실시한다. 이에 의해, 도 5에 도시된 바와 같이 제1금속층(11)은 제1부분산화영역(11a)과 제1금속배선(11b)으로 구분된다. 즉, 제1포토레지스트패턴(12)이 형성되지 않은 영역은 양극산화공정에 의해 산화되어 절연영역인 제1부분산화영역(11a)으로 변하고, 제1포토레지스트패턴(12)이 형성된 영역은 포토레지스트패턴(13)에 의해 양극산화되지 않 으므로 제1금속배선(11b)이 된다. 여기서, 제1부분산화영역(11a)은 산화알루미늄(알루미나, Al2O3)이 된다. 그리고 도 6과 같이 제1포토레지스트패턴(12)을 제거함으로써 제1부분산화영역(11a) 및 제1금속배선(11b)을 가진 제1회로를 형성한다(S2). 이러한 제1회로의 패턴은 제1포토레지스트패턴(13)의 패턴형상에 따라 다양하게 형성될 수 있다. As shown in FIG. 4, the first photoresist pattern 12 is formed on the surface of the first metal layer 11, and then the first metal layer 11 is subjected to anodization. As a result, as shown in FIG. 5, the first metal layer 11 is divided into a first partial oxidation region 11a and a first metal wiring 11b. That is, the region where the first photoresist pattern 12 is not formed is oxidized by an anodizing process to change into the first partial oxidation region 11a which is an insulating region, and the region where the first photoresist pattern 12 is formed is a photo. Since it is not anodized by the resist pattern 13, it becomes the first metal wiring 11b. Here, the first partial oxidation region 11a is made of aluminum oxide (alumina, Al 2 O 3 ). 6, the first circuit having the first partial oxidation region 11a and the first metal wiring 11b is formed by removing the first photoresist pattern 12 (S2). The pattern of the first circuit may be variously formed according to the pattern shape of the first photoresist pattern 13.

이어서, 제1부분산화영역(11a)과 제1금속배선(11b)을 전면적으로 양극산화시킴으로써 도 7과 같은 층간절연층(13)을 형성한다(S3).Subsequently, the interlayer insulating layer 13 shown in FIG. 7 is formed by anodizing the first partial oxidation region 11a and the first metal wiring 11b entirely (S3).

그리고 도 8에 도시된 바와 같이 층간절연층(13)의 표면에 제2포토레지스트패턴(14)을 형성한 후에, 도 9와 같이 제2포토레지스트패턴(14)이 형성되지 않은 영역을 부분적으로 습식에칭함으로써 하나 이상의 관통홀(15)을 형성한다(S4). 이때, 관통홀(15)은 제1금속층(11)의 제1금속배선(11b)까지 연장된다. 그리고 도 10과 같이 제2포토레지스트패턴(14)을 제거한다. 관통홀(15)의 패턴은 제1포토레지스트패턴(14)의 패턴형상에 따라 다양하게 형성될 수 있다.As shown in FIG. 8, after the second photoresist pattern 14 is formed on the surface of the interlayer insulating layer 13, the region in which the second photoresist pattern 14 is not formed is partially formed as shown in FIG. 9. One or more through holes 15 are formed by wet etching (S4). In this case, the through hole 15 extends to the first metal wiring 11b of the first metal layer 11. 10, the second photoresist pattern 14 is removed. The pattern of the through hole 15 may be variously formed according to the pattern shape of the first photoresist pattern 14.

이어서, 도 11에 도시된 바와 같이 층간절연층(13)의 표면과 관통홀(15)의 내에는 이베포레이션 공정에 의해 제2금속층(16)을 증착한다(S5). Subsequently, as illustrated in FIG. 11, the second metal layer 16 is deposited on the surface of the interlayer insulating layer 13 and the through hole 15 by an evaporation process (S5).

그런 다음, 도 12와 같이 제2금속층(16)의 표면에 제3포토레지스트패턴(17)을 형성하고, 이어서 제2금속층(16) 및 제3포토레지스트패턴(17)에 양극산화공정을 수행한다. 이에 의해 층간절연층(13)의 표면에 증착된 제2금속층(16)은 도 13과 같이 제2부분산화영역(16a) 및 제2금속배선(16b)으로 구분된다. 즉, 제3포토레지스트 패턴(17)이 형성되지 않은 영역은 양극산화됨으로써 제2부분산화영역(16a)이 되고, 제3포토레지스트패턴(17)이 형성된 영역은 제3포토레지스트패턴(17)에 의해 제2금속배선(16b)으로 남는다. Next, as shown in FIG. 12, a third photoresist pattern 17 is formed on the surface of the second metal layer 16, and then anodization is performed on the second metal layer 16 and the third photoresist pattern 17. do. As a result, the second metal layer 16 deposited on the surface of the interlayer insulating layer 13 is divided into a second partial oxidation region 16a and a second metal wiring 16b as shown in FIG. 13. That is, the region where the third photoresist pattern 17 is not formed is anodized to become the second partial oxidation region 16a, and the region where the third photoresist pattern 17 is formed is the third photoresist pattern 17. This leaves the second metal wiring 16b.

여기서, 제2부분산화영역(16a)은 산화알루미늄(알루미나, Al2O3)이 된다. 그리고 관통홀(15) 내에는 제2금속층(16c)이 메워져 형성된다. Here, the second partial oxidation region 16a is made of aluminum oxide (alumina, Al 2 O 3 ). The second metal layer 16c is filled in the through hole 15.

최종적으로, 도 14와 같이 제3포토레지스트패턴(17)을 제거함으로써 제2부분산화영역(16a) 및 제2금속배선(16b)을 가진 제2회로를 형성한다(S6). 이러한 제2회로의 패턴은 제3포토레지스트패턴(17)의 패턴형상에 따라 다양하게 형성될 수 있다. Finally, as shown in FIG. 14, the second circuit having the second partial oxidation region 16a and the second metal wiring 16b is formed by removing the third photoresist pattern 17 (S6). The pattern of the second circuit may be variously formed according to the pattern shape of the third photoresist pattern 17.

한편, 상기 제2회로의 상부에 S3 내지 S6단계를 1번 이상 반복적으로 수행함으로써 3층 이상의 회로가 적층된 멀티레이어를 형성할 수 있다. Meanwhile, by repeatedly performing steps S3 to S6 one or more times on the second circuit, a multilayer in which circuits of three or more layers are stacked may be formed.

이와 같이 본 발명은 금속층의 부분적인 양극산화 내지 전면적인 양극산화공정을 통해 다층 배선구조를 보다 용이하게 형성시킬 수 있고, 또한 종래기술과 달리 절연층의 증착 내지 에칭 시에 요구되는 진공프로세스가 감소함에 따라 공정비용을 대폭 절감할 수 있는 장점이 있다. As described above, the present invention can more easily form a multilayer wiring structure through partial anodization or full anodization of the metal layer, and unlike the prior art, the vacuum process required for deposition or etching of the insulating layer is reduced. As a result, the process cost can be greatly reduced.

도 1은 본 발명의 한 실시예에 따른 양극산화를 이용한 멀티레이어 제조방법을 도시한 공정도이다. 1 is a process chart showing a multilayer manufacturing method using anodization according to an embodiment of the present invention.

도 2 내지 도 14는 본 발명에 의한 양극산화를 이용한 멀티레이어 제조방법을 공정별로 도시한 단면도이다. 2 to 14 is a cross-sectional view showing a multi-layer manufacturing method using anodization according to the present invention for each process.

* 도면의 주요 부분에 대한 부호의 간단한 설명 *Brief description of symbols for the main parts of the drawings

10: 기판 11: 제1금속층10: substrate 11: first metal layer

12: 제1포토레지스트패턴 13: 층간절연층12: first photoresist pattern 13: interlayer insulating layer

14: 제2포토레지스트패턴 15: 관통홀14 second photoresist pattern 15 through hole

16: 제2금속층 17: 제3포토레지스트패턴16: second metal layer 17: third photoresist pattern

Claims (6)

기판의 표면에 제1금속층을 형성하는 제1단계;Forming a first metal layer on a surface of the substrate; 상기 제1금속층을 부분적으로 양극산화시킴으로써 제1부분산화영역 및 제1금속배선을 가지는 제1회로를 형성하는 제2단계;Forming a first circuit having a first partial oxidation region and a first metal wiring by partially anodizing the first metal layer; 상기 제1금속층 및 제1부분산화영역을 전면적으로 양극산화시킴으로써 층간절연층을 형성하는 제3단계;A third step of forming an interlayer insulating layer by anodizing the first metal layer and the first partial oxidation region entirely; 상기 층간절연층을 부분적으로 에칭함으로써 하나 이상의 관통홀을 형성하는 제4단계;A fourth step of forming at least one through hole by partially etching the interlayer insulating layer; 상기 층간절연층의 표면 및 관통홀 내에 제2금속층을 형성하는 제5단계; 및 A fifth step of forming a second metal layer in a surface of the interlayer insulating layer and through holes; And 상기 제2금속층의 표면을 부분적으로 양극산화시킴으로서 제2부분산화영역 및 제2금속배선을 가지는 제2회로를 형성하는 제6단계를 포함하는 것을 특징으로 하는, 양극산화를 이용한 멀티레이어 제조방법.And a sixth step of forming a second circuit having a second partial oxidation region and a second metal wiring by partially anodizing the surface of the second metal layer. 제1항에 있어서, The method of claim 1, 상기 제2단계에서, 상기 제1금속층의 표면에 제1포토레지스트패턴을 형성하고, 상기 제1포토레지스트패턴을 통해 상기 제1금속층을 부분적으로 양극산화시킴으로써 제1부분산화영역 및 제1금속배선을 형성시킨 후에 상기 제1포토레지스트 패턴을 제거하는 것을 특징으로 하는, 양극산화를 이용한 멀티레이어 제조방법.In the second step, a first photoresist pattern is formed on the surface of the first metal layer, and the first partial oxidation region and the first metal wiring are formed by partially anodizing the first metal layer through the first photoresist pattern. After the formation of the first photoresist pattern, characterized in that the multilayer manufacturing method using anodization. 제1항에 있어서, The method of claim 1, 제4단계에서, 상기 층간절연층의 표면에 제2포토레지스트패턴을 형성하고, 상기 제2포토레지스트패턴을 통해 상기 층간절연층을 부분적으로 에칭함으로써 관통홀을 형성시킨 후에 제2포토레지스트패턴을 제거하는 것을 특징으로 하는, 양극산화를 이용한 멀티레이어 제조방법.In the fourth step, a second photoresist pattern is formed on the surface of the interlayer insulating layer, and the second photoresist pattern is formed after the through hole is formed by partially etching the interlayer insulating layer through the second photoresist pattern. A method for producing a multilayer using anodization, characterized in that the removal. 제1항에 있어서, The method of claim 1, 제6단계에서, 상기 제2금속층의 표면에 제3포토레지스트패턴을 형성하고, 상기 제3포토레지스트패턴을 통해 상기 제2금속층을 부분적으로 양극산화시킴으로써 제2부분산화층 및 제2금속배선을 형성시킨 후에 상기 제3포토레지스트패턴을 제거하는 것을 특징으로 하는, 양극산화를 이용한 멀티레이어 제조방법.In a sixth step, a third photoresist pattern is formed on the surface of the second metal layer, and the second partial oxide layer and the second metal wiring are formed by partially anodizing the second metal layer through the third photoresist pattern. After removing the third photoresist pattern, a multilayer manufacturing method using anodization. 제4항에 있어서, The method of claim 4, wherein 상기 제1금속층 및 제2금속층이 알루미늄이고, 상기 제1 및 제2 부분산화영역과 층간절연층이 알루미나인 것을 특징으로 하는, 양극산화를 이용한 멀티레이어 제조방법. And the first metal layer and the second metal layer are aluminum, and the first and second partial oxidation regions and the interlayer insulating layer are alumina. 제5항에 있어서, The method of claim 5, 상기 제2회로의 상부에 상기 제3 내지 제6단계를 1번 이상 반복적으로 수행하는 것을 특징으로 하는, 양극산화를 이용한 멀티레이어 제조방법. The method of manufacturing a multilayer using anodization, characterized in that the third to sixth steps are repeatedly performed one or more times on the second circuit.
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