KR20090070783A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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KR20090070783A
KR20090070783A KR1020070138912A KR20070138912A KR20090070783A KR 20090070783 A KR20090070783 A KR 20090070783A KR 1020070138912 A KR1020070138912 A KR 1020070138912A KR 20070138912 A KR20070138912 A KR 20070138912A KR 20090070783 A KR20090070783 A KR 20090070783A
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high voltage
trench
voltage device
device region
region
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KR1020070138912A
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KR100906557B1 (en
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문남칠
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and a manufacturing method thereof are provided to reduce an area of a power device by suppressing the lateral diffusion of a deep drain by forming a trench isolation layer between a body and the drain. A trench isolation layer(150) is formed inside a high voltage device region. A drain region(160) is formed in one side of the trench isolation layer inside the high voltage device region. A device isolation layer is formed on the trench isolation layer inside the high voltage device region. A trench gate(173,174) is formed in the other side of the trench isolation layer inside the high voltage device region. A gate(195) is formed in the device isolation layer inside the high voltage device region. A source region is formed in the other side of the trench isolation layer inside the high voltage device region.

Description

반도체소자 및 그 제조방법{Semiconductor Device and Method for manufacturing the same}Semiconductor device and method for manufacturing same

실시예는 반도체소자 및 그 제조방법에 관한 것이다.The embodiment relates to a semiconductor device and a manufacturing method thereof.

종래기술에 따른 트렌치 모스펫(Trench MOSFET)(미도시)은 이온주입 및 확산 공정을 이용하여 드레인(drain) 구조를 형성함으로 트렌치(Trench) MOSFET 면적을 줄이는데 한계가 있다. 이는 드레인(drain)의 측면확산(lateral diffusion)에 의한 BV(Breakdown Voltage) 저하 때문이다.The trench MOSFET (not shown) according to the prior art has a limit in reducing the trench MOSFET area by forming a drain structure using ion implantation and diffusion processes. This is because of the breakdown voltage (BV) caused by the lateral diffusion of the drain.

실시예는 트렌치 MOSFET에서 종래의 확산에 의해 형성되는 드레인(drain) 면적을 줄임으로써, 트렌치 MOSFET의 전기적 특성 저하 없이 전력소자의 면적을 줄일 수 있는 반도체소자 및 그 제조방법을 제공하고자 한다.Embodiments provide a semiconductor device and a method of manufacturing the same, which can reduce the area of a power device without deteriorating the electrical characteristics of the trench MOSFET by reducing the drain area formed by conventional diffusion in the trench MOSFET.

실시예에 따른 반도체소자는 저전압소자영역과 고전압소자영역 포함하는 반도체소자에 있어서, 상기 고전압소자영역은, 상기 고전압소자영역 내에 형성된 트렌치 절연층; 상기 고전압소자영역 내의 상기 트렌치 절연층의 일측에 형성된 드레인영역; 상기 고전압소자영역 내의 상기 트렌치 절연층 상에 형성된 소자분리막; 상기 고전압소자영역 내의 상기 트렌치 절연층의 타측에 형성된 트렌치 게이트; 상기 고전압소자영역 내의 상기 소자분리막 상에 형성된 게이트; 및 상기 고전압소자영역 내의 상기 트렌치 절연층 타측에 형성된 소스영역;을 포함하는 것을 특징으로 한다.A semiconductor device according to an embodiment includes a semiconductor device including a low voltage device region and a high voltage device region, wherein the high voltage device region comprises a trench insulating layer formed in the high voltage device region; A drain region formed on one side of the trench insulating layer in the high voltage device region; An isolation layer formed on the trench insulating layer in the high voltage device region; A trench gate formed on the other side of the trench insulating layer in the high voltage device region; A gate formed on the device isolation layer in the high voltage device region; And a source region formed on the other side of the trench insulating layer in the high voltage device region.

또한, 실시예에 따른 반도체소자의 제조방법은 저전압소자영역과 고전압소자영역을 설정하는 단계; 상기 고전압소자영역 내에 트렌치 절연층을 형성하는 단계; 상기 고전압소자영역 내의 상기 트렌치 절연층의 일측에 드레인영역을 형성하는 단계; 상기 고전압소자영역 내의 상기 트렌치 절연층 상에 소자분리막을 형성하는 단계; 상기 고전압소자영역 내의 상기 트렌치 절연층의 타측에 트렌치 게이트를 형성하는 단계; 상기 고전압소자영역 내의 상기 소자분리막 상에 게이트를 형성하는 단 계; 상기 고전압소자영역 내의 상기 트렌치 절연층 타측에 소스영역을 형성하는 단계;를 포함하는 것을 특징으로 한다.In addition, the semiconductor device manufacturing method according to the embodiment comprises the steps of setting a low voltage device region and a high voltage device region; Forming a trench insulating layer in the high voltage device region; Forming a drain region on one side of the trench insulating layer in the high voltage device region; Forming an isolation layer on the trench insulating layer in the high voltage device region; Forming a trench gate on the other side of the trench insulating layer in the high voltage device region; Forming a gate on the device isolation layer in the high voltage device region; And forming a source region on the other side of the trench insulating layer in the high voltage device region.

실시예에 따른 반도체소자 및 그 제조방법에 의하면, 트렌치 절연층(trench Isolation)을 바디(Body)와 드레인(Drain)사이에 형성함으로 깊은 드레인(Deep drain)의 측면확산(lateral diffusion)을 억제하여 전력소자(Power device) 면적을 줄일 수 있는 새로운 구조의 트렌치(Trench) MOSFET 구조를 제공한다.According to a semiconductor device and a method of manufacturing the same, a trench isolation layer is formed between a body and a drain to suppress lateral diffusion of a deep drain. There is a new trench MOSFET structure that can reduce the power device area.

이하, 실시예에 따른 반도체소자 및 그 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments will be described in detail with reference to the accompanying drawings.

실시예의 설명에 있어서, 각 층의 "상/아래(on/under)"에 형성되는 것으로 기재되는 경우에 있어, 상/아래는 직접(directly)와 또는 다른 층을 개재하여(indirectly) 형성되는 것을 모두 포함한다.In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

(실시예)(Example)

도 1은 실시예에 따른 반도체소자의 단면도이나, 본 발명이 도 1과 같은 구조에 한정되는 것은 아니다.1 is a cross-sectional view of a semiconductor device according to an embodiment, but the present invention is not limited to the structure shown in FIG. 1.

실시예에 따른 반도체소자는 저전압소자영역(LV)과 고전압소자영역(HV)을 포함하며, 상기 고전압소자영역(HV)은, 상기 고전압소자영역 내에 형성된 트렌치 절연층(150); 상기 고전압소자영역 내의 상기 트렌치 절연층(150)의 일측에 형성된 드레인영역(160); 상기 고전압소자영역 내의 상기 트렌치 절연층(150) 타측에 형성 된 트렌치 게이트(173, 174); 상기 고전압소자영역 내의 상기 트렌치 절연층(150) 상에 형성된 소자분리막(193); 상기 고전압소자영역 내의 상기 소자분리막(193) 상에 형성된 게이트(195); 및 상기 고전압소자영역 내의 상기 트렌치 절연층(150) 타측에 형성된 소스영역(180);을 포함할 수 있다.In an exemplary embodiment, a semiconductor device includes a low voltage device region LV and a high voltage device region HV. The high voltage device region HV may include a trench insulating layer 150 formed in the high voltage device region; A drain region 160 formed on one side of the trench insulating layer 150 in the high voltage device region; Trench gates 173 and 174 formed on the other side of the trench insulating layer 150 in the high voltage device region; An isolation layer 193 formed on the trench insulating layer 150 in the high voltage device region; A gate 195 formed on the device isolation layer 193 in the high voltage device region; And a source region 180 formed on the other side of the trench insulating layer 150 in the high voltage device region.

실시예에서 상기 고전압소자영역(HV)은 상기 고전압소자영역 내에 형성된 제1 도전형 매립층(120)을 더 포함하고, 상기 트렌치 절연층(150)은 상기 제1 도전형 매립층(120)과 접촉하여 형성될 수 있다.In an embodiment, the high voltage device region HV further includes a first conductive buried layer 120 formed in the high voltage device region, and the trench insulating layer 150 is in contact with the first conductive buried layer 120. Can be formed.

또한, 실시예에서 상기 드레인영역(160)은 상기 제1 도전형 매립층(120)과 접촉하여 형성될 수 있다.In an embodiment, the drain region 160 may be in contact with the first conductivity type buried layer 120.

또한, 상기 트렌치 절연층(150)은 상기 고전압소자영역에 형성된 제1 트렌치(T1)(도 3 참조), 상기 제1 트렌치(T1)의 측벽에 형성된 절연막(152) 및 상기 절연막(152) 상에 형성된 도전성물질(154)을 포함할 수 있다.In addition, the trench insulating layer 150 may include a first trench T1 (see FIG. 3) formed in the high voltage device region, an insulating film 152 formed on sidewalls of the first trench T1, and an insulating film 152. It may include a conductive material 154 formed in.

도 1에서의 미설명 부호는 아래 제조방법을 설명하면서 설명하기로 한다.Reference numerals in FIG. 1 will be described with reference to the following manufacturing method.

실시예에 따른 반도체소자에 의하면, 트렌치 절연층(trench Isolation)(150)을 바디(Body)(140)와 드레인(Drain)(160)사이에 형성함으로 깊은 드레인(Deep drain)(160)의 측면확산(lateral diffusion)을 억제하여 전력소자(Power device) 면적을 줄일 수 있는 새로운 구조의 트렌치(Trench) MOSFET 구조를 제공할 수 있다.According to the semiconductor device according to the embodiment, the trench isolation layer 150 is formed between the body 140 and the drain 160 to form a side surface of the deep drain 160. It is possible to provide a trench MOSFET structure having a new structure that can suppress a lateral diffusion to reduce a power device area.

이하, 도 2 내지 도 12를 참조하여 실시예에 따른 반도체소자의 제조방법을 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. 2 through 12.

우선, 도 2와 같이 기판에 저전압소자영역(LV)(210)과 고전압소자영역(HV)(110)을 설정한다. 이후, 고전압소자영역 기판(110)에 제1 도전형 매립층(120)을 형성할 수 있다. 예를 들어, 고전압소자영역 기판(110)이 P형 기판인 경우, 5족 이온을 주입하여 N형 매립층(120)을 형성할 수 있다.First, as shown in FIG. 2, a low voltage device region LV 210 and a high voltage device region HV 110 are set in a substrate. Thereafter, the first conductivity type buried layer 120 may be formed on the high voltage device region substrate 110. For example, when the high voltage device region substrate 110 is a P type substrate, the N type buried layer 120 may be formed by implanting group 5 ions.

이후, 상기 기판의 전면에 제1 트렌치(T1)(도 3 참조) 형성을 위한 하드마스크를 형성한다. 예를 들어, 제1 산화막(121), 질화막(123), 제2 산화막(125)에 의한 하드마스크를 형성할 수 있다.Thereafter, a hard mask for forming a first trench T1 (see FIG. 3) is formed on the entire surface of the substrate. For example, a hard mask may be formed by the first oxide film 121, the nitride film 123, and the second oxide film 125.

다음으로, 도 3과 같이 상기 하드마스크를 감광막(미도시)에 의해 패턴하고, 상기 하드마스크를 식각마스크로 하여 상기 고전압소자영역 기판(110)에 제1 트렌치(T1)를 형성할 수 있다. 이때, 상기 제1 트렌치(T1)에 의해 상기 제1 도전형 매립층(120)의 상측이 노출될 수 있다.Next, as shown in FIG. 3, the hard mask may be patterned by a photoresist film (not shown), and the first trench T1 may be formed in the high voltage device region substrate 110 using the hard mask as an etching mask. In this case, an upper side of the first conductivity type buried layer 120 may be exposed by the first trench T1.

다음으로, 도 4와 같이 상기 제1 트렌치(T1)의 측벽에 절연막(152)을 형성한다. 예를 들어, 상기 제1 트렌치(T1)의 측벽에 열산화에 또는 증착에 의해 산화막 절연막(152)을 형성할 수 있다. 상기 절연막(152)은 열산화인 경우는 제1 트렌치(T1)의 측벽에 형성될 수 있고, 증착에 의한 경우는 제1 트렌치(T1)의 측벽과 하측에도 형성될 수 있다. 한편, 상기 하드마스크 중 제2 산화막(125)는 세정(cleaning)에 의해 제거될 수 있다.Next, as shown in FIG. 4, an insulating film 152 is formed on the sidewall of the first trench T1. For example, the oxide film insulating layer 152 may be formed on the sidewall of the first trench T1 by thermal oxidation or deposition. The insulating layer 152 may be formed on the sidewall of the first trench T1 in case of thermal oxidation, and may be formed on the sidewall and the lower side of the first trench T1 in the case of deposition. Meanwhile, the second oxide layer 125 of the hard mask may be removed by cleaning.

이후, 상기 절연막(152) 상에 도전성물질(154)로 제1 트렌치(T1)를 메워서 트렌치 절연층(150)을 완성할 수 있다. 예를 들어, 폴리실리콘(154)을 증착할 수 있다.Subsequently, the trench insulating layer 150 may be completed by filling the first trenches T1 with the conductive material 154 on the insulating layer 152. For example, polysilicon 154 may be deposited.

다음으로, 도 5와 같이 상기 질화막(123)을 제거하고 상기 고전압소자영역 기판(110) 내의 상기 트렌치 절연층(150)의 일측에 드레인영역(160)을 형성한다. 예를 들어, 옥시염화인(POCL3)를 이용하여 드레인영역(160)을 형성할 수 있으나 이에 한정되는 것은 아니다. 실시예에서의 드레인영역(160)은 이온주입후 열처리공정에 의해서 상기 제1 도전형 매립층(120)과 접촉되로록 확장될 수 있다. 이러한 드레인영역(160)의 확장은 한번의 열처리에 의해서 또는 추후 진행되는 드리프트영역(130)을 형성하기 위한 열처리에 의해서도 확장이 가능할 수 있다.Next, as illustrated in FIG. 5, the nitride layer 123 is removed and a drain region 160 is formed on one side of the trench insulating layer 150 in the high voltage device region substrate 110. For example, the drain region 160 may be formed using phosphorus oxychloride (POCL3), but is not limited thereto. In an exemplary embodiment, the drain region 160 may be extended to be in contact with the first conductivity type buried layer 120 by an ion implantation and heat treatment process. The drain region 160 may be expanded by a single heat treatment or by a heat treatment for forming a drift region 130 which is performed later.

이때, 상기 제1 산화막(121)을 그대로 이용하거나 또는 제1 산화막(121) 게거 후 별도의 버퍼산화막(미도시)을 형성한 상태에서 드레인영역(160)이 형성될 수 있다. 한편, 도전성물질(154) 상에도 산화막이 형성된 상태에서 드레인영역(160)이 형성될 수 있다.In this case, the drain region 160 may be formed using the first oxide layer 121 as it is or in a state in which a separate buffer oxide layer (not shown) is formed after the first oxide layer 121 is removed. Meanwhile, the drain region 160 may be formed on the conductive material 154 with the oxide film formed.

다음으로, 도 6과 같이 제1 도전형 드리프트(Drift)영역(130)을 형성할 수 있다. 예를 들어, 5족 이온을 이용하여 이온주입하고 어닐링을 통해 N형 드리프트 영역(130)을 형성할 수 있다.Next, as illustrated in FIG. 6, the first conductivity type drift region 130 may be formed. For example, the N-type drift region 130 may be formed by ion implantation using group 5 ions and annealing.

다음으로, 도 7과 같이 상기 고전압소자영역 기판(110)에 제2 도전형 바디영역(140)을 형성할 수 있다. 예를 들어, 상기 고전압소자영역 기판(110)에 3족 이온을 이온주입하고 어닐링하여 P형 바디영역(140)을 형성할 수 있다.Next, as shown in FIG. 7, a second conductive body region 140 may be formed on the high voltage device region substrate 110. For example, the P-type body region 140 may be formed by ion implanting and annealing group III ions into the high voltage device region substrate 110.

다음으로, 도 8과 같이 소자분리영역(193)을 형성한다. 예를 들어, 제2 질화막(310)을 형성하고, 소자분리막(193)이 형성될 위치의 제2 질화막(310)을 제거한 후 열산화에 의해 소자분리막(193)을 형성할 수 있으나 이에 한정되는 것은 아니 다.Next, the device isolation region 193 is formed as shown in FIG. 8. For example, the second nitride layer 310 may be formed, the second nitride layer 310 at the position where the device isolation layer 193 is to be formed may be removed, and the device isolation layer 193 may be formed by thermal oxidation. It is not.

다음으로, 도 9와 같이 상기 제2 질화막(310)을 제거한 후 제3 질화막(320)을 형성하고, 제2 트렌치(T2)(도 10 참조), 제3 트렌치(T3)(도 10 참조)가 형성될 영역의 제3 질화막(320)과 제1 산화막(121)을 제거하여 트렌치 하드마스크를 패턴한다.Next, after removing the second nitride film 310 as shown in FIG. 9, a third nitride film 320 is formed, and a second trench T2 (see FIG. 10) and a third trench T3 (see FIG. 10) are formed. The trench hard mask is patterned by removing the third nitride film 320 and the first oxide film 121 in the region where the is to be formed.

다음으로, 도 10과 같이 트렌치 하드 마스크를 식각마스크로 하여 상기 제2 도전형 바디영역(140)을 선택적으로 식각하여 제2 트렌치(T2), 제3 트렌치(T3)를 형성한다.Next, as shown in FIG. 10, the second conductive type body region 140 is selectively etched using the trench hard mask as an etch mask to form second trenches T2 and third trenches T3.

다음으로, 도 11과 같이 제3 질화막(320)을 제거한 후 상기 제2 트렌치(T2), 제3 트렌치(T3)의 측벽과 하측에 각각 제1 게이트절연막(171), 제2 게이트절연막(172)을 형성한다. 이후, 제2 트렌치(T2), 제3 트렌치(T3)를 도전성물질로 메워서 제1 트렌치 게이트(173)와 제2 트렌지 게이트(174)를 형성할 수 있다.Next, as shown in FIG. 11, after the third nitride film 320 is removed, the first gate insulating film 171 and the second gate insulating film 172 are disposed on the sidewalls and the lower side of the second trench T2 and the third trench T3, respectively. ). Thereafter, the first trench gate 173 and the second trench gate 174 may be formed by filling the second trench T2 and the third trench T3 with a conductive material.

다음으로, 도 12와 같이 도전성물질을 기판의 전면에 형성한 후 패턴 후 식각을 통해 소자분리막 상에 게이트(195)와 저전압소자영역에 게이트(220, 230)을 형성한다. 이후, 이온주입에 의해 고전압소자영역의 기판에 소스영역(180)을 형성하고, 저전압소자영역 기판(210)에 소스, 드레인을 형성할 수 있다. Next, as shown in FIG. 12, after the conductive material is formed on the entire surface of the substrate, the gates 195 and the gates 220 and 230 are formed on the device isolation layer through etching after patterning. Thereafter, the source region 180 may be formed on the substrate of the high voltage device region by ion implantation, and the source and the drain may be formed on the substrate of the low voltage device region 210.

한편, 상기 소자분리막 상에 게이트(195)는 도 11의 공정단계에서 별도로 진행될 수도 있다. 예를 들어, 기판 전면에 도전성물질을 형성하고 소자분리막 상의 게이트가 형성될 위치만을 노출하는 감광막패턴(미도시)을 형성하고, 상기 감광막패턴을 식각마스크로 하여 상기 도전성물질을 식각하여 소자분리막 상에 게이 트(195)와 제1 트렌치 게이트(173), 제2 트렌치 게이트(174)를 함께 형성할 수도 있다.Meanwhile, the gate 195 may be separately processed in the process step of FIG. 11. For example, a conductive material is formed on the entire surface of the substrate, and a photoresist pattern (not shown) exposing only a position where a gate on the device isolation layer is to be formed is formed. The gate 195, the first trench gate 173, and the second trench gate 174 may be formed together.

실시예에 따른 반도체소자의 제조방법에 의하면, 트렌치 절연층(trench Isolation)을 바디(Body)와 드레인(Drain)사이에 형성함으로 깊은 드레인(Deep drain)의 측면확산(lateral diffusion)을 억제하여 전력소자(Power device) 면적을 줄일 수 있는 새로운 구조의 트렌치(Trench) MOSFET 구조를 제공할 수 있다.According to the method of manufacturing the semiconductor device according to the embodiment, the trench isolation layer is formed between the body and the drain, thereby suppressing the lateral diffusion of the deep drain and thus the power. It is possible to provide a new trench MOSFET structure that can reduce the power device area.

본 발명은 기재된 실시예 및 도면에 의해 한정되는 것이 아니고, 청구항의 권리범위에 속하는 범위 안에서 다양한 다른 실시예가 가능하다.The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

도 1은 실시예에 따른 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device according to an embodiment.

도 2 내지 도 12는 실시예에 따른 반도체소자의 제조방법의 공정단면도.2 to 12 are process cross-sectional views of a method of manufacturing a semiconductor device according to the embodiment.

Claims (8)

저전압소자영역과 고전압소자영역 포함하는 반도체소자에 있어서,A semiconductor device comprising a low voltage device region and a high voltage device region, 상기 고전압소자영역은,The high voltage device region, 상기 고전압소자영역 내에 형성된 트렌치 절연층;A trench insulating layer formed in the high voltage device region; 상기 고전압소자영역 내의 상기 트렌치 절연층의 일측에 형성된 드레인영역;A drain region formed on one side of the trench insulating layer in the high voltage device region; 상기 고전압소자영역 내의 상기 트렌치 절연층 상에 형성된 소자분리막;An isolation layer formed on the trench insulating layer in the high voltage device region; 상기 고전압소자영역 내의 상기 트렌치 절연층의 타측에 형성된 트렌치 게이트;A trench gate formed on the other side of the trench insulating layer in the high voltage device region; 상기 고전압소자영역 내의 상기 소자분리막 상에 형성된 게이트; 및A gate formed on the device isolation layer in the high voltage device region; And 상기 고전압소자영역 내의 상기 트렌치 절연층 타측에 형성된 소스영역;을 포함하는 것을 특징으로 하는 반도체소자.And a source region formed at the other side of the trench insulating layer in the high voltage device region. 제1 항에 있어서,According to claim 1, 상기 고전압소자영역은,The high voltage device region, 상기 고전압소자영역 내에 형성된 제1 도전형 매립층을 더 포함하고,Further comprising a first conductive buried layer formed in the high voltage device region, 상기 트렌치 절연층은 상기 제1 도전형 매립층과 접촉하는 것을 특징으로 하는 반도체소자.And the trench insulating layer is in contact with the first conductivity type buried layer. 제2 항에 있어서,The method of claim 2, 상기 드레인영역은,The drain region, 상기 제1 도전형 매립층과 접촉하여 형성되는 것을 특징으로 하는 반도체소자.The semiconductor device is formed in contact with the first conductive type buried layer. 제1 항 내지 제3 항 중 어느 하나의 항에 있어서,The method according to any one of claims 1 to 3, 상기 트렌치 절연층은,The trench insulating layer, 상기 고전압소자영역에 형성된 제1 트렌치;A first trench formed in the high voltage device region; 상기 제1 트렌치 상에 형성된 절연막; 및An insulating film formed on the first trench; And 상기 절연막 상에 형성된 도전성물질;을 포함하는 것을 특징으로 하는 반도체소자.And a conductive material formed on the insulating film. 저전압소자영역과 고전압소자영역을 설정하는 단계;Setting a low voltage device region and a high voltage device region; 상기 고전압소자영역 내에 트렌치 절연층을 형성하는 단계;Forming a trench insulating layer in the high voltage device region; 상기 고전압소자영역 내의 상기 트렌치 절연층의 일측에 드레인영역을 형성하는 단계;Forming a drain region on one side of the trench insulating layer in the high voltage device region; 상기 고전압소자영역 내의 상기 트렌치 절연층 상에 소자분리막을 형성하는 단계;Forming an isolation layer on the trench insulating layer in the high voltage device region; 상기 고전압소자영역 내의 상기 트렌치 절연층의 타측에 트렌치 게이트를 형성하는 단계;Forming a trench gate on the other side of the trench insulating layer in the high voltage device region; 상기 고전압소자영역 내의 상기 소자분리막 상에 게이트를 형성하는 단계; Forming a gate on the isolation layer in the high voltage device region; 상기 고전압소자영역 내의 상기 트렌치 절연층 타측에 소스영역을 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체소자의 제조방법.And forming a source region on the other side of the trench insulating layer in the high voltage device region. 제5 항에 있어서,The method of claim 5, 상기 트렌치 절연층을 형성하는 단계 전에 상기 고전압소자영역 내에 제1 도전형 매립층을 형성하는 단계를 더 포함하고,Forming a first conductive buried layer in the high voltage device region before forming the trench insulating layer; 상기 트렌치 절연층은 상기 제1 도전형 매립층과 접촉하는 것을 특징으로 하는 반도체소자의 제조방법.And the trench insulating layer is in contact with the first conductivity type buried layer. 제6 항에 있어서,The method of claim 6, 상기 드레인영역을 형성하는 단계는,Forming the drain region, 상기 제1 도전형 매립층과 접촉하여 형성되는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device, characterized in that formed in contact with the first conductive buried layer. 제5 항 내지 제7 항 중 어느 하나의 항에 있어서,The method according to any one of claims 5 to 7, 상기 트렌치 절연층을 형성하는 단계는,Forming the trench insulating layer, 상기 고전압소자영역에 제1 트렌치를 형성하는 단계;Forming a first trench in the high voltage device region; 상기 제1 트렌치 상에 절연막을 형성하는 단계; 및Forming an insulating film on the first trench; And 상기 절연막 상에 도전성물질로 제1 트렌치를 메우는 단계;를 포함하는 것을 특징으로 하는 반도체소자의 제조방법.And filling a first trench with a conductive material on the insulating film.
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CN101969072A (en) * 2010-08-27 2011-02-09 东南大学 Consumption type N-type lateral double-diffusion metal-oxide semiconductor for reducing voltage
US8704279B2 (en) 2012-05-25 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded JFETs for high voltage applications
US9190535B2 (en) 2012-05-25 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bootstrap MOS for high voltage applications

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KR100306797B1 (en) 1997-12-29 2002-06-20 박종섭 Semiconductor power device and fabricating method thereof

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CN101969072A (en) * 2010-08-27 2011-02-09 东南大学 Consumption type N-type lateral double-diffusion metal-oxide semiconductor for reducing voltage
US8704279B2 (en) 2012-05-25 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded JFETs for high voltage applications
US9190535B2 (en) 2012-05-25 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bootstrap MOS for high voltage applications
US9257979B2 (en) 2012-05-25 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded JFETs for high voltage applications
US9660108B2 (en) 2012-05-25 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Bootstrap MOS for high voltage applications
US9673323B2 (en) 2012-05-25 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded JFETs for high voltage applications
US10510882B2 (en) 2012-05-25 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded JFETs for high voltage applications
US11069805B2 (en) 2012-05-25 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded JFETs for high voltage applications

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