KR20090070687A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20090070687A
KR20090070687A KR1020070138792A KR20070138792A KR20090070687A KR 20090070687 A KR20090070687 A KR 20090070687A KR 1020070138792 A KR1020070138792 A KR 1020070138792A KR 20070138792 A KR20070138792 A KR 20070138792A KR 20090070687 A KR20090070687 A KR 20090070687A
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thin film
amorphous carbon
carbon thin
temperature amorphous
high temperature
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KR1020070138792A
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Korean (ko)
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김형수
서재욱
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02444—Carbon, e.g. diamond-like carbon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method for forming a semiconductor device is provided to improve yield of the semiconductor device by preventing the alignment overlay from getting worse due to the distortion of a wafer by the thin film stress. A low temperature amorphous carbon thin film(12) is formed in an upper part of a semiconductor substrate(10) with a lower structure. A high temperature amorphous carbon thin film(14) is formed in the upper part of the low temperature amorphous carbon thin film. An interlayer material(18) protecting the amorphous carbon thin film is formed in the high temperature amorphous carbon thin film. The interlayer material is made of SiON or PE-TEOS. The low temperature amorphous carbon thin film and the high temperature amorphous carbon thin film are formed by using the hydrocarbon material respectively. The thickness of the high temperature amorphous carbon thin film is between 0 and 60 % of the overall thickness forming the high temperature amorphous carbon thin film and the low temperature amorphous carbon thin film.

Description

반도체 소자 형성 방법{Method for manufacturing semiconductor device}Method for manufacturing semiconductor device

본 발명은 반도체 소자 형성 방법에 관한 것으로, 더욱 상세하게는 저온 비정질 탄소 박막과 고온 비정질 탄소 박막을 교대로 증착하는 이중 층(dual layer)을 형성하여 스트레스에 의해 웨이퍼가 왜곡되어 정렬 정밀도(overlay)가 나빠지는 현상을 개선함으로써 마스크 공정의 불량 및 재작업을 줄여 수율을 향상시킬 수 있는 반도체 소자 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to form a dual layer in which a low temperature amorphous carbon thin film and a high temperature amorphous carbon thin film are alternately deposited, thereby distorting the wafer due to stress, thereby causing an alignment accuracy. The present invention relates to a method of forming a semiconductor device capable of improving yield by reducing defects and rework of a mask process by improving a phenomenon of deterioration.

반도체 소자가 고집적화됨에 따라 웨이퍼 직경이 대구형화되며, 웨이퍼 상에 여러 층의 금속막을 증착하고, 이들을 서로 절연하기 위한 절연막을 증착하여 다층화되고 있다.As semiconductor devices have been highly integrated, wafer diameters have become large, and multiple layers of metal films are deposited on the wafer, and insulating films for insulating them from each other are deposited.

이러한 다층화는 박막 간의 열팽창도(thermal expansion coefficient) 및 공정 온도가 올라감에 따라 열응력(thermal stress)의 발생이 불가피하게 된다.In this multilayering, thermal stress is inevitably generated as the thermal expansion coefficient between the thin films and the process temperature increase.

이러한 열응력은 박막과 웨이퍼 사이의 계면 박리, 막과 막 사이의 계면 박리 또는 웨이퍼 휨(warpage)을 초래하게 되어 노광 공정에서 정렬 정밀도(overlay) 를 악화시키는 불량이 발생하고, 후속 공정 또는 최종 제품의 수율에 악영향을 미치게 된다.These thermal stresses result in interfacial delamination between the thin film and the wafer, interfacial delamination between the film and the film or wafer warpage, resulting in a defect that worsens the alignment accuracy in the exposure process, and subsequent processing or final product. Will adversely affect the yield.

또한, 증착된 박막의 응력(stress)에는 웨이퍼를 하향 굽음(downward bending)을 일으키는 압축 응력(compressive stress)과 상향 굽음(upward bending)을 일으키는 인장 응력(tensile stress)이 있다. 여기서 응력(stress)의 양과 방향은 정렬 정밀도(overlay)에 큰 영향을 주는 요인으로 작용한다. In addition, the stress of the deposited thin film includes compressive stress causing downward bending of the wafer and tensile stress causing upward bending. In this case, the amount and direction of stress act as a factor that greatly affects the alignment accuracy.

도 1은 일반적인 저장 노드 마스크 공정(storage node mask process)에서 측정한 반도체 기판상에 형성된 박막 종류별 정렬 정밀도(overlay)를 나타낸 그래프로써, 버퍼 산화막(buffer oxide), 질화막(nitride), 층간 절연막(PSG, TEOS) 등은 거의 비슷한 정렬 정밀도를 나타내고 있는 반면에, 비정질 탄소(amorphous carbon; a-C) 박막의 경우 정렬 정밀도가 급격히 나빠지는 것을 알 수 있다. 특히, 일반적인 비정질 탄소 박막 상에서 노광 공정을 수행했을 때 발생하는 정렬 정밀도(overlay) 불량은 웨이퍼의 아래쪽 가장 자리에서 많이 발생한다.FIG. 1 is a graph illustrating the alignment accuracy of each thin film formed on a semiconductor substrate measured by a general storage node mask process. , TEOS) and the like show almost similar alignment accuracy, whereas in the case of amorphous carbon (aC) thin films, the alignment accuracy deteriorates sharply. In particular, the misalignment caused when the exposure process is performed on a typical amorphous carbon thin film occurs frequently at the bottom edge of the wafer.

본 발명은 박막 응력(stress)에 의해 웨이퍼가 왜곡되어 정렬 정밀도(overlay)가 나빠지는 현상을 개선함으로써 마스크 공정의 불량 및 재작업을 줄여 수율을 향상시킬 수 있는 반도체 소자 형성 방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a method of forming a semiconductor device that can improve the yield by reducing the defect and rework of the mask process by improving the phenomenon that the wafer is distorted due to the thin film stress (stress) and the alignment is bad (overlay) It is done.

본 발명에 따른 반도체 소자 형성 방법은 The method of forming a semiconductor device according to the present invention

하부 구조물이 형성된 반도체 기판 상부에 저온 비정질 탄소 박막을 형성하는 단계; 및Forming a low temperature amorphous carbon thin film on the semiconductor substrate on which the lower structure is formed; And

상기 저온 비정질 탄소 박막 상부에 고온 비정질 탄소 박막을 형성하는 단계를 포함하는 것을 특징으로 한다.And forming a high temperature amorphous carbon thin film on the low temperature amorphous carbon thin film.

또한, 상기 고온 비정질 탄소 박막 상부에 상기 비정질 탄소 박막을 보호하는 층간 물질을 형성하는 단계를 더 포함하고,The method may further include forming an interlayer material on the high temperature amorphous carbon thin film to protect the amorphous carbon thin film.

상기 저온 비정질 탄소 박막 및 상기 고온 비정질 탄소 박막은 각각 탄화수소계 물질을 이용하여 형성하고,The low temperature amorphous carbon thin film and the high temperature amorphous carbon thin film are each formed using a hydrocarbon-based material,

상기 고온 비정질 탄소 박막의 두께는 상기 저온 비정질 탄소 박막과 상기 고온 비정질 탄소 박막이 형성하는 전체 두께의 0 초과 60%이하로 형성하고,The thickness of the high temperature amorphous carbon thin film is greater than 0 and less than 60% of the total thickness formed by the low temperature amorphous carbon thin film and the high temperature amorphous carbon thin film,

상기 층간 물질은 실리콘 질산화막(SiON) 또는 PETEOS로 형성하고,The interlayer material is formed of silicon nitride oxide (SiON) or PETEOS,

상기 저온 비정질 탄소 박막은 200~380℃ 온도 구간에서 형성하고, 상기 고온 비정질 탄소 박막은 381~650℃ 온도 구간에서 형성하는 것을 특징으로 한다.The low temperature amorphous carbon thin film is formed at a temperature range of 200 to 380 ° C., and the high temperature amorphous carbon thin film is formed at a temperature range of 381 to 650 ° C.

본 발명은 저온 비정질 탄소 박막과 고온 비정질 탄소 박막을 교대로 증착하는 이중 층(dual layer)을 형성하여 응력(stress)에 의해 웨이퍼가 왜곡되어 정렬 정밀도(overlay)가 나빠지는 현상을 개선함으로써 마스크 공정의 불량 및 재작업을 줄여 수율을 향상시킬 수 있는 효과가 있다.The present invention provides a mask process by forming a dual layer for alternately depositing a low temperature amorphous carbon thin film and a high temperature amorphous carbon thin film, thereby improving the phenomenon in which the wafer is distorted due to stress and the alignment accuracy is degraded. This can improve the yield by reducing defects and rework.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명은 여기서 설명되는 실시예에 한정되지 않고 다른 형태로 구체화될 수 있다. 오히려, 여기서 소개되는 실시예는 본 발명의 기술적 사상이 철저하고 완전하게 개시되고 당업자에게 본 발명의 사상이 충분히 전달되기 위해 제공되는 것이다. 또한, 명세서 전체에 걸쳐서 동일한 참조 번호들은 동일한 구성요소를 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

일반적으로 비정질 탄소 박막은 형성 온도와 압력에 따라 저온 비정질 탄소 박막(low temperature amorphous carbon film) 및 고온 비정질 탄소 박막(high temperature amorphous carbon film)으로 나뉜다. In general, an amorphous carbon thin film is divided into a low temperature amorphous carbon film and a high temperature amorphous carbon film according to the formation temperature and pressure.

비정질 탄소 박막 제조 방법에 따른 스트레스 값은 [표 1]과 같다.The stress values according to the amorphous carbon thin film manufacturing method are shown in [Table 1].

stackstack stressstress nn kk HTHT 3K3K 2.73E+082.73E + 08 1.871.87 0.390.39 LTLT 3K3K HTHT 2K2K -5.67E+06-5.67E + 06 1.871.87 0.370.37 LTLT 4K4K HT(550℃)HT (550 ℃) singlesingle 8.0E+088.0E + 08 1.871.87 0.3740.374 LT(300℃)LT (300 ℃) singlesingle -3.7E+09-3.7E + 09 1.891.89 0.0850.085

[표 1]을 참조하면, 저온 비정질 탄소 박막은 200~380℃ 온도에서 증착되며 (-) 부호를 갖는 강한 압축 응력(compressive stress)을 나타내고, 고온 비정질 탄소 박막은 381~650℃ 온도에서 증착하며 (+) 부호를 갖는 강한 인장 응력(tensile stress)을 나타내는 특징이 있다.Referring to [Table 1], the low temperature amorphous carbon thin film is deposited at a temperature of 200 to 380 ° C and exhibits a strong compressive stress having a negative sign, and the high temperature amorphous carbon thin film is deposited at a temperature of 381 to 650 ° C. It is characterized by a strong tensile stress with a (+) sign.

본 발명은 탄소 박막 형성 방법에 따라 스트레스 방향이 바뀌는 것에 착안하여 비정질 탄소 박막을 단일 층(single layer)으로 형성하지 않고 저온 비정질 탄소 박막과 고온 비정질 탄소 박막을 교대로 증착하는 이중 층(dual layer)을 형성한다. 따라서, 저온 비정질 탄소 박막의 (-) 부호를 갖는 강한 압축 응력(compressive stress)과 고온 비정질 탄소 박막의 (+) 부호를 갖는 강한 인장 응력(tensile stress)을 서로 상쇄시킬 수 있다. 즉, 저온 비정질 탄소 박막과 고온 비정질 탄소 박막을 교대로 증착하는 이중 층(dual layer)의 박막 응력(film stress)이 단일 비정질 탄소층(single amorphous carbon layer) 대비 절대값이 10% 이상 낮아지는 것을 알 수 있다.The present invention focuses on the change in the direction of stress according to the carbon thin film formation method, thereby forming a dual layer alternately depositing a low temperature amorphous carbon thin film and a high temperature amorphous carbon thin film without forming an amorphous carbon thin film as a single layer. To form. Therefore, the strong compressive stress having the (-) sign of the low temperature amorphous carbon thin film and the strong tensile stress having the (+) sign of the high temperature amorphous carbon thin film can be offset each other. That is, the film stress of the dual layer in which the low temperature amorphous carbon thin film and the high temperature amorphous carbon thin film are alternately deposited is 10% lower than the absolute value of the single amorphous carbon layer. Able to know.

도 2a 내지 도 2c는 본 발명에 따른 저온 비정질 탄소 박막과 고온 비정질 탄소 박막을 교대로 증착하는 이중 층(dual layer)을 포함하는 반도체 소자 형성 방법을 나타낸 단면도들이다. 여기서는 C3H6로 대표되는 탄화수소(CxHy)계 물질을 이용하여 비정질 탄소 박막(amorphous carbon film)을 형성하는 경우를 예를 들어 설명한다.2A to 2C are cross-sectional views illustrating a method of forming a semiconductor device including a dual layer for alternately depositing a low temperature amorphous carbon thin film and a high temperature amorphous carbon thin film according to the present invention. Here, an example of forming an amorphous carbon film using a hydrocarbon (CxHy) -based material represented by C 3 H 6 will be described.

먼저, 도 2a를 참조하면, 하부 구조물이 형성된 반도체 기판(10) 상부에 목표 두께보다 낮은 두께를 갖는 저온 비정질 탄소 박막(12)을 형성한다. First, referring to FIG. 2A, a low temperature amorphous carbon thin film 12 having a thickness lower than a target thickness is formed on a semiconductor substrate 10 on which a lower structure is formed.

도 2b를 참조하면, 저온 비정질 탄소 박막(12) 상부에 고온 비정질 탄소 박막(14)을 저온 비정질 탄소 박막(12)의 두께에 더하여 목표 두께가 되는 두께로 형성한다. 이때, 고온 비정질 탄소 박막(14)의 두께는 노광 공정에서 필요한 비정질 탄소 박막의 투광도를 향상시키기 위해 목표 비정질 탄소 박막(16) 두께의 60%를 넘지 않도록 형성한다.Referring to FIG. 2B, the high temperature amorphous carbon thin film 14 is formed on the low temperature amorphous carbon thin film 12 to a thickness that becomes a target thickness in addition to the thickness of the low temperature amorphous carbon thin film 12. At this time, the thickness of the high temperature amorphous carbon thin film 14 is formed not to exceed 60% of the target amorphous carbon thin film 16 in order to improve the light transmittance of the amorphous carbon thin film required in the exposure process.

도 2c를 참조하면, 저온 비정질 탄소 박막(12) 및 고온 비정질 탄소 박막(14)의 이중 층(dual layer)으로 형성된 비정질 탄소 박막(16)을 산소 플라즈마로부터 보호하기 위한 실리콘 질산화막(SiON), PE-TEOS(Plasma Enhanced Tetra Ethyl OrthoSilicate) 등의 층간 물질(18)을 형성한 후 후속 마스크 공정을 수행한다.Referring to FIG. 2C, a silicon nitride oxide film (SiON) for protecting an amorphous carbon thin film 16 formed of a dual layer of the low temperature amorphous carbon thin film 12 and the high temperature amorphous carbon thin film 14 from oxygen plasma, After forming an interlayer material 18 such as Plasma Enhanced Tetra Ethyl OrthoSilicate (PE-TEOS), a subsequent mask process is performed.

상기한 바와 같이 본 발명은 응력(stress)에 의해 웨이퍼가 왜곡되어 정렬 정밀도(overlay)가 나빠지는 현상을 개선함으로써 마스크 공정의 불량 및 재작업을 줄여 수율을 향상시킬 수 있는 기술을 개시한다.As described above, the present invention discloses a technique capable of improving the yield by reducing defects and rework of the mask process by improving the phenomenon in which the wafer is distorted due to stress and the alignment is degraded.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다. In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

도 1은 일반적인 저장 노드 마스크 공정에서 측정한 반도체 기판상에 형성된 박막 종류별 정렬 정밀도(overlay)를 나타낸 그래프이다.FIG. 1 is a graph showing the alignment accuracy of each thin film formed on a semiconductor substrate measured in a general storage node mask process.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 형성 방법을 나타낸 단면도들이다. 2A through 2C are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

10: 반도체 기판10: semiconductor substrate

12: 저온 비정질 탄소 박막12: low temperature amorphous carbon thin film

14: 고온 비정질 탄소 박막14: high temperature amorphous carbon thin film

16: 비정질 탄소 박막16: amorphous carbon thin film

18: 층간 물질18: interlayer material

Claims (6)

하부 구조물이 형성된 반도체 기판 상부에 저온 비정질 탄소 박막을 형성하는 단계; 및Forming a low temperature amorphous carbon thin film on the semiconductor substrate on which the lower structure is formed; And 상기 저온 비정질 탄소 박막 상부에 고온 비정질 탄소 박막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성 방법.And forming a high temperature amorphous carbon thin film on the low temperature amorphous carbon thin film. 제 1 항에 있어서,The method of claim 1, 상기 고온 비정질 탄소 박막 상부에 상기 비정질 탄소 박막을 보호하는 층간 물질을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 형성 방법.And forming an interlayer material protecting the amorphous carbon thin film on the high temperature amorphous carbon thin film. 제 2 항에 있어서, The method of claim 2, 상기 층간 물질은 실리콘 질산화막(SiON) 또는 PE-TEOS로 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.The interlayer material is formed of silicon nitride oxide (SiON) or PE-TEOS. 제 1 항에 있어서,The method of claim 1, 상기 저온 비정질 탄소 박막 및 상기 고온 비정질 탄소 박막은 각각 탄화수 소계 물질을 이용하여 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.The low temperature amorphous carbon thin film and the high temperature amorphous carbon thin film are each formed using a hydrocarbon-based material. 제 1 항에 있어서,The method of claim 1, 상기 고온 비정질 탄소 박막의 두께는 상기 저온 비정질 탄소 박막과 상기 고온 비정질 탄소 박막이 형성하는 전체 두께의 0 초과 60%이하로 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.And the thickness of the high temperature amorphous carbon thin film is greater than 0 and less than 60% of the total thickness formed by the low temperature amorphous carbon thin film and the high temperature amorphous carbon thin film. 제 1 항에 있어서,The method of claim 1, 상기 저온 비정질 탄소 박막은 200~380℃ 온도 구간에서 형성하고, 상기 고온 비정질 탄소 박막은 381~650℃ 온도 구간에서 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.The low temperature amorphous carbon thin film is formed at a temperature range of 200 to 380 ° C., and the high temperature amorphous carbon thin film is formed at a temperature range of 381 to 650 ° C. A method of forming a semiconductor device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9087789B2 (en) 2011-12-27 2015-07-21 Samsung Electronics Co., Ltd. Methods of manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9087789B2 (en) 2011-12-27 2015-07-21 Samsung Electronics Co., Ltd. Methods of manufacturing a semiconductor device

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