KR20090042422A - Exposure mask and forming method of micro pattern in semiconductor device - Google Patents

Exposure mask and forming method of micro pattern in semiconductor device Download PDF

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Publication number
KR20090042422A
KR20090042422A KR1020070108167A KR20070108167A KR20090042422A KR 20090042422 A KR20090042422 A KR 20090042422A KR 1020070108167 A KR1020070108167 A KR 1020070108167A KR 20070108167 A KR20070108167 A KR 20070108167A KR 20090042422 A KR20090042422 A KR 20090042422A
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KR
South Korea
Prior art keywords
opening
openings
dummy
exposure
exposure mask
Prior art date
Application number
KR1020070108167A
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Korean (ko)
Inventor
양철훈
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070108167A priority Critical patent/KR20090042422A/en
Publication of KR20090042422A publication Critical patent/KR20090042422A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The present invention includes a plurality of openings arranged in a line, formed between a first opening disposed at an edge of the openings and a second opening adjacent to the first opening, wherein the dummy opening includes a dummy opening having a width equal to or smaller than the width of the openings. An exposure mask and a method for forming a fine pattern of a semiconductor device using the same are provided.

Description

Exposure mask and forming method of micro pattern in semiconductor device using same

The present invention relates to an exposure mask and a method of forming a micropattern of a semiconductor device using the same. In particular, when a plurality of openings are arranged in a row, an exposure mask and a semiconductor device using the same to prevent the size of the openings disposed on both edges thereof from increasing. It relates to a method of forming a fine pattern.

The semiconductor device includes devices including a plurality of memory cells and transistors. Recently, as the degree of integration of semiconductor devices increases, the size of these devices decreases. For this purpose, an exposure process capable of forming a fine pattern should also be improved. On the other hand, the case of a flash element is demonstrated as follows.

The flash device has a plurality of contact plugs for electrically connecting the underlying structure and the upper structure. For example, in the case of a NAND flash device, a contact plug may be formed between the drain select transistors to electrically connect the drain select transistor to the upper metal wiring. In order to form the contact plugs, a mask pattern is formed by performing an exposure and development process on the mask layer. Subsequently, an etching process is performed according to a mask pattern to form a contact hole in a region where a contact plug is to be formed, and then the inside of the contact hole is filled with a conductive film or a metal film.

On the other hand, the above-described exposure (exposure) and development (develop) process (develop) process can be said to be one of the processes that are very affected by the degree of integration of the semiconductor device. Specifically, the exposure step is a step of irradiating a light source to the hard mask film using an exposure mask in which a pattern to be formed is opened, and the developing step removes an area to which the light source is irradiated (or an area where the light source is not irradiated). To form a hard mask pattern.

The light source used in the exposure process varies in resolution depending on the type, which requires a higher resolution as a micro pattern with a narrower interval (or width) is formed. In addition, the light source used in the exposure process has a specific wavelength (or energy) according to the kind, and the exposure process is performed by adjusting the intensity | strength of this wavelength and the position (for example, height) of an exposure area | region. However, as the degree of integration of semiconductor devices increases, the width of the micropatterns narrows, and the size of the openings disposed at both edges of the openings arranged in a line is larger than the pattern of the exposure mask due to the scattering phenomenon of the light source. Can be formed. This will be described below with reference to FIG. 1.

1 is a photograph for explaining a conventional fine pattern. The drawing illustrates a patterned hard mask pattern, which includes a first opening 10a formed in a dense area and a second opening 10b formed in an area less dense than an area in which the first openings 10a are formed. As can be seen in the photograph, the first openings 10a having a tight spacing are formed to have a constant size or a small size, whereas the second openings 10b have a larger size than the first openings 10a. You can check it. This is due to the scattering phenomenon of the light source during the exposure process, and a region wider than the second opening 10b may be exposed to form a pattern larger than a desired size. When such a wide area is formed, a wide contact hole is formed in a subsequent etching process, which may cause a bridge phenomenon between neighboring holes, thereby reducing the reliability of the semiconductor device.

The problem to be solved by the present invention is that when a plurality of openings are arranged in a line, dummy openings are formed on both sides or one side of the openings disposed at both edges, so that during the exposure and development process, the holes corresponding to the openings arranged at the edges are formed. The increase in size can be suppressed.

In addition, by dividing the dummy opening into a plurality of dummy openings, it is possible to prevent the exposure area from being generated along the dummy opening even when the degree of integration of the semiconductor device is increased.

An exposure mask according to an embodiment of the present invention includes a plurality of openings arranged in a line. It is formed between the first opening disposed at the edge of the openings and the second opening adjacent to the first opening, and the exposure mask pattern includes a dummy opening having a width equal to or smaller than the width of the openings.

The gap between the first and second openings is wider than the gap between the openings, and the length of the dummy opening is 300% to 1000% of the second opening.

An exposure mask according to another embodiment of the present invention includes a plurality of openings arranged in a line. It is formed on both sides of an edge opening arranged at the edge of the openings, and consists of an exposure mask including a dummy opening whose width is equal to or smaller than the width of the openings.

The gap between the edge opening and the opening adjacent to the edge opening is wider than the gap of the openings, the width of the dummy opening corresponds to 50% to 100% of the width of the opening, and the length of the dummy opening is 300% to 1000% of the length of the opening. Corresponds to.

Two to eight dummy openings are arranged in a direction perpendicular to the direction in which the openings are arranged to form dummy openings, and the total length of the dummy openings corresponds to 300% to 1000% of the length of the openings.

In the method for forming a micropattern of a semiconductor device according to the present invention, a semiconductor substrate in which an interlayer insulating film, a hard mask film and a photoresist film are sequentially stacked is provided. A photoresist pattern is formed by performing an exposure and development process on the photoresist film with an exposure mask including a plurality of openings arranged in a row and dummy openings disposed on one or both sides of the openings positioned at the edges. The hard mask layer is etched according to the photoresist pattern to form a hard mask pattern having a fine pattern. A method of forming a fine pattern of a semiconductor device, the method including patterning an interlayer insulating layer by performing an etching process according to a hard mask pattern.

The dummy opening is formed at one side of the opening in which the exposure process is weak due to the gap between the openings in the exposure mask.

The dummy openings are formed on one side or both sides of the openings in which the exposure process is weak due to the gap between the openings formed in the exposure mask.

The dummy openings are formed with a width of 50% to 100% and a length of 300% to 1000% of the openings.

According to the present invention, when a plurality of openings are arranged in a line in the photoresist pattern, the size of the openings disposed at both edges can be suppressed from increasing.

In addition, by forming a dummy opening in the exposure mask, scattering of the light source during the exposure process can be suppressed, and by forming a plurality of dummy patterns, the exposure area according to the dummy pattern is increased even when the degree of integration of semiconductor elements is increased. It can be prevented from forming. As a result, an increase in the size of the opening disposed at the edge can be prevented, and a bridge phenomenon between the fine patterns of the semiconductor device can be suppressed, so that deterioration of electrical characteristics of the semiconductor device can be prevented.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 is a cross-sectional view illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.

Referring to FIG. 2, a process for forming contact holes in the micropattern forming process will be described as an example. An interlayer insulating layer 202 for forming contact holes is formed on the semiconductor substrate 200. The hard mask film 204 is formed over the interlayer insulating film 202, and the photoresist film 206 is formed over the hard mask film 204. Next, the exposure process is performed using the exposure mask 208 in which the opening part was formed in the area | region to be patterned. The exposure process irradiates the photoresist film 206 with a light source passing through the opening of the exposure mask 208 to vary the physical properties between the exposed and non-exposed areas of the photoresist film 206. The regions where the physical properties of the photoresist film 206 are different are divided into portions removed and remaining portions by a subsequent development process, thereby forming a photoresist pattern.

The exposure mask 208 used at the time of the above-mentioned exposure process is demonstrated concretely as follows.

3A to 3D are views for explaining an embodiment of an exposure mask according to the present invention.

3A, a first embodiment of an exposure mask 208 is shown. In the case of forming the first openings 210a having a tight spacing (W1) and the second openings 210b formed at an interval wider than the spacing W1 of the first openings 210a, the exposure mask 208 is as follows. same. In a subsequent exposure process, the region of the photoresist corresponding to the second opening 210b formed at a wider distance W2 than the space W1 between the first openings 210a may be affected by scattering of the light source. The exposure area can be widened by this.

In order to prevent this, the scattering phenomenon of the light source is suppressed between the openings of the exposure mask 208 which are vulnerable to the exposure process (for example, openings corresponding to areas where the exposure area of the photoresist film is widened among the openings of the exposure mask). A dummy opening 212 is formed for this purpose. At this time, the dummy opening 212 does not substantially form an exposure area in the photoresist film. To this end, the dummy opening 212 is preferably formed with a width M of 50% to 100% of the second opening 210b. In addition, although not shown sufficiently long due to constraints of the drawings, the total length L of the dummy opening 212 is preferably formed to be 300% to 1000% of the length of the second opening 210b.

Meanwhile, as the degree of integration of the semiconductor device increases, the size of the micropattern decreases. Accordingly, the size of the first and second openings 210a and 210b of the exposure mask 208 should also be reduced. As the size of the first and second openings 210a and 210b is made smaller, the size of the dummy opening 212 that suppresses scattering of the light source should be smaller.

However, due to the size limitation of the E-Beam used when forming the exposure mask 208, there is a limit to forming the dummy opening 212 small. For example, when the dummy openings 212 are formed to have a width of 50% of the first and second openings 210a and 210b, the dummy openings are 136 nm to 140 nm since they can be formed by E-Beam at present. It may be difficult to form a small size of 212. If the size of the dummy opening 212 is not reduced, an exposure area may be formed along the dummy opening 212 in the photoresist film during the exposure process. This may be substantially patterned during the subsequent etching process to form unnecessary contact holes along the region where the dummy opening 212 is formed.

In order to prevent this, the dummy opening 212 may be divided into two. That is, when it is difficult to form a narrow width M of the dummy openings 212, the dummy openings 212 may be formed in two by dividing the length of the dummy openings 212 in half. As a result, it is possible to prevent the exposure region from being formed along the dummy opening 212.

As described above, due to the scattering phenomenon of the light source, a plurality of dummy openings 212 may be divided and formed to prevent the expansion of the exposure area along the second opening 210b. For example, in FIG. 3B, the dummy openings 212 are divided into three, and in FIG. 3C, the dummy openings 212 are divided into four. The dummy openings 212 may be divided into more than the number shown in the drawing according to the resolution of the light source.

3D illustrates another example of the exposure mask according to the present invention. Referring to FIG. 3D, dummy openings 212 may be formed on both sides of the second opening 210b vulnerable to the exposure process. have. In this case, each of the dummy openings 212 may be formed by dividing into a plurality, as in the example of FIGS. 3A to 3C.

4 is a photograph for explaining a fine pattern of a semiconductor device according to the present invention. Referring to FIG. 4, an exposure and development process is performed using the exposure masks 208 described with reference to FIGS. 3A to 3D, and accordingly, photos having fine patterns of the first opening 600a and the second opening 600b are formed. The resist pattern can be seen. As can be seen from the photograph, it can be seen that the opening by the dummy opening is not formed between the first opening 600a and the second opening 600b, and the size of the second opening 600b is not expanded. .

As a result, it is possible to suppress the subsequent increase in the size of the fine pattern, thereby preventing the bridge phenomenon between the fine patterns to reduce the deterioration of the electrical characteristics of the semiconductor device.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a photograph for explaining a micropattern according to the prior art.

2 is a cross-sectional view illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.

3A to 3D are views for explaining an embodiment of an exposure mask according to the present invention.

4 is a photograph for explaining a fine pattern of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200 semiconductor substrate 202 interlayer insulating film

204: hard mask film 206: photoresist film

208: Exposure mask 210a: First opening

210b: second opening 212: dummy opening

Claims (13)

A plurality of openings arranged in a line; And And a dummy opening formed between a first opening disposed at an edge of the openings and a second opening adjacent to the first opening, the dummy opening having a width equal to or smaller than the width of the openings. The method of claim 1, An exposure mask having a larger spacing between the first and second openings than a spacing between the openings. The method of claim 1, The length of the dummy opening is an exposure mask to form a length of 300% to 1000% of the second opening. A plurality of openings arranged in a line; And An exposure mask formed on both sides of an edge opening disposed at an edge of the openings, the exposure mask including a dummy opening having a width equal to or smaller than the width of the openings. The method of claim 3, wherein An exposure mask having a larger gap between the edge opening and an opening adjacent to the edge opening than the gap between the openings. The method according to claim 1 or 3, And a width of the dummy opening corresponds to 50% to 100% of the width of the opening. The method according to claim 1 or 3, An exposure mask having a length corresponding to 300% to 1000% of a length of the opening. The method according to claim 1 or 3, And two to eight dummy openings arranged in a direction perpendicular to the direction in which the openings are arranged to form dummy openings. The method of claim 8, And a total length of the dummy openings corresponds to 300% to 1000% of the length of the opening. Providing a semiconductor substrate in which an interlayer insulating film, a hard mask film, and a photoresist film are sequentially stacked; Forming a photoresist pattern by performing an exposure and development process on the photoresist film with an exposure mask including a plurality of openings arranged in a row and dummy openings disposed on one or both sides of the openings positioned at edges; Etching the hard mask layer according to the photoresist pattern to form a hard mask pattern having a fine pattern formed thereon; And Patterning the interlayer insulating layer by performing an etching process according to the hard mask pattern. The method of claim 10, The dummy opening is formed on one side of the opening in which the exposure process is weak due to the gap between the openings in the exposure mask. The method of claim 10, The dummy opening may be formed on one side or both sides of an opening having a weak exposure process due to a gap between the openings formed in the exposure mask. The method of claim 10, The dummy opening may be formed to have a width of 50% to 100% and a length of 300% to 1000% of the opening.
KR1020070108167A 2007-10-26 2007-10-26 Exposure mask and forming method of micro pattern in semiconductor device KR20090042422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070108167A KR20090042422A (en) 2007-10-26 2007-10-26 Exposure mask and forming method of micro pattern in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070108167A KR20090042422A (en) 2007-10-26 2007-10-26 Exposure mask and forming method of micro pattern in semiconductor device

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KR20090042422A true KR20090042422A (en) 2009-04-30

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