KR20090040989A

KR20090040989A - Semiconductor device and method of manufacturing a semiconductor device

Info

Publication number: KR20090040989A
Application number: KR1020070106448A
Authority: KR
Inventors: 김진범; 이병찬; 이선길; 최시영
Original assignee: 삼성전자주식회사
Priority date: 2007-10-23
Filing date: 2007-10-23
Publication date: 2009-04-28

Abstract

A semiconductor device and a method for manufacturing the same are provided to prevent electrical connection between active regions by suppressing the growth of a source/drain lifted by a lower spacer unit of a gate spacer in a transverse direction. A semiconductor device includes a cell region and a peripheral circuit region. A substrate(100) includes an active region and a field region(105). A gate trench is formed in a part with a word line in the active region. The word line including a gate electrode(115), a silicide film(117), a gate mask(120) and a gate spacer(125) are formed on the gate trench. The gate spacer includes the oxide and/or the silicon nitride. A first contact region(130) and a second contact region(135) are formed by implanting the ion to the substrate between the gate structures by suing a gate mask and a gate spacer. The source and drain(140) is formed on the first and second contact region.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same to prevent electrical connection between the active region.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to such demands, manufacturing techniques have been developed for semiconductor devices to improve the degree of integration, reliability, and response speed.

As the design rules decrease in semiconductor devices, the performance of semiconductor devices is deteriorated due to short channel effects of transistors and resistance of contact plugs and wiring. In order to solve this problem, a selective epitaxial growth (SEG) process is used. In other words, an elevated source / drain technology (ESD), which is formed by selectively growing silicon on the active region and raising the source / drain, is applied. However, when silicon is selectively grown, there is a problem caused by silicon growing not only in the vertical direction but also in the transverse direction with respect to the substrate. In this case, the silicon growing in the lateral direction may be electrically connected to each other, so that adjacent active regions may be electrically connected to each other.

1 is a plan view showing the layout of a semiconductor device according to the prior art.

Referring to FIG. 1, the active region 20 is tilted at θ ° with respect to the word line 10 in a 100-plane wafer. When silicon is grown on the active region 20 exposed between the word lines 10 for the application of ESD technology, crystals grow in a direction to create a low index for minimizing interfacial energy, although not shown. That is, when silicon grows while making {111} planes, it is possible to grow while making {110} planes and {100} planes. However, when silicon to be used as a source / drain is grown on the {110} plane and the {100} plane on each active region 20, the active regions 20 are electrically connected through the growing source / drain. It adversely affects the reliability of the semiconductor device. The distance D between the active regions 20 required for the active regions 20 to be electrically connected is represented by B as the distance between the word lines 10 and A as the distance between the active regions 20. Appears as 1.

Equation 1:

The larger the distance B between the word lines 10, the shorter the distance D between the active regions 20, and the smaller the distance B between the word lines 10, the larger the distance D between the active regions 20. In other words, the larger the distance B between the word lines 10, the wider the region of silicon to be grown for the source / drain rise, so that the silicon grows in the direction perpendicular to the substrate and grows in the transverse direction. There is a greater possibility that the laterally grown silicon will come into contact with each other. Therefore, the wider the space between the word lines 10, the weaker the 2-bit bridge.

Accordingly, an object of the present invention is to provide a semiconductor device that prevents electrical connection between active regions.

It is also an object of the present invention to provide a method for manufacturing a semiconductor device that prevents electrical connection between active regions.

In order to achieve the above object of the present invention, a semiconductor device in which an elevated source / drain is electrically insulated is disclosed. The semiconductor device includes a substrate, a gate structure formed on the substrate, and a lower spacer portion formed on a side of the gate structure and having a first surface parallel to the substrate, and an upper spacer having a second surface inclined with the first surface. Word lines including gate spacers and raised source / drain regions formed on a substrate between the word lines.

In one embodiment according to the present invention, the height of the raised source / drain region may be substantially the same as the height of the lower spacer portion, and the raised source / drain may be substantially parallel to the first surface.

In one embodiment of the present invention, the lower portion of the gate structure may be a structure buried in a recess formed on the substrate.

In one embodiment of the present invention, the difference between the thickness of the lower spacer portion and the thickness of the upper spacer may be about 10 ~ 990Å. Alternatively, the ratio of the thickness of the lower spacer to the thickness of the upper spacer may be about 1.0: 1.1 to 1.0: 3.0.

In order to achieve the above object of the present invention, disclosed is a method of manufacturing a semiconductor device in which the elevated source / drain is electrically insulated from each other. A substrate is formed, and a gate structure including a gate electrode and a mask formed on the gate electrode is formed on the substrate. A preliminary gate spacer is formed on the side of the gate structure. A contact region is formed on the substrate between the gate structures. A raised source / drain is formed on the contact region. The preliminary gate spacers are isotropically etched to form gate spacers including a lower gate spacer portion having a first surface parallel to the raised source / drain and an upper spacer portion having a second surface inclined with the first surface.

In an embodiment of the present disclosure, the forming of the elevated source / drain may include a step of selectively epitaxially growing each of or simultaneously introducing a gas containing silicon atoms or germanium atoms.

In example embodiments, the forming of the gate structure may include forming a recess in the substrate and filling the gate electrode.

As described above, according to the present invention, it is possible to suppress the growth of silicon in the lateral direction and to block the connection between the silicon patterns, thereby improving the reliability of the semiconductor device.

Further, according to the present invention, a margin for forming a contact plug can be secured, even if a misalignment occurs. The reliability of the semiconductor device may be improved by preventing the source / drain from being electrically connected to the gate electrode.

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited to the following embodiments. Persons having the present invention may implement the present invention in various other forms without departing from the spirit of the present invention. That is, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms and should be construed as being limited to the embodiments described herein. Is not. It is not to be limited by the embodiments described in the text, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but such components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may exist in the middle. Will be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it will be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring", will likewise be interpreted.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "include" are intended to indicate that there is a feature, number, step, action, component, or combination thereof described, and one or more other features or numbers, It will be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries are to be interpreted as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a semiconductor device, according to example embodiments, cut in the bit line direction.

Referring to FIG. 2, a semiconductor device according to the present invention includes a cell area and a peripheral circuit area, and includes a substrate 100, a gate electrode 115, a silicide layer 117, and a gate. A word line including a mask 120 and a gate spacer 125, first and second contact regions 130 and 135, and an elevated source / drain 140 are included. Although the recessed gate electrode 115 is shown in FIG. 3, in another embodiment according to the present invention, the gate electrode 115 is not recessed and may be formed on a substrate.

The substrate 100 includes an active region and a field region 105. The substrate 100 may include substrates such as a metal oxide single crystal substrate, a silicon substrate, a germanium substrate, a silicon germanium substrate, an SOI substrate, and a GOI substrate. In the field region 105, trenches for device isolation are formed in which the silicon oxide film is filled with a partial thickness below the surface of the substrate 100. Each active region is isolated by the field region 105. As illustrated in FIG. 1, the active region may be tilted at a predetermined angle (θ °) with a word line.

A gate trench is formed in a portion where the word line is formed in the active region. For example, two gate trenches are formed in one isolated active region. The gate trench may have various shapes and two or more gate trenches may be formed. For example, as shown in FIG. 2, the lower portion may be a shepere shape, and the width thereof may be narrower or wider toward the lower portion. A gate insulating layer 110 is formed on the inner wall of the gate trench. The gate insulating layer 110 may include an oxide, such as silicon oxide, or a metal oxide having a high-k. For example, the gate insulating layer 110 includes titanium oxide, zirconium oxide, hafnium oxide, and aluminum.

A word line including the gate electrode 115, the silicide layer 117, the gate mask 120, and the gate spacer 125 is formed on the gate trench. For example, the gate electrode 115 fills the gate trench and partially protrudes onto the substrate 100. The gate electrode 115 includes a conductive material. For example, it may include polysilicon doped with an impurity. The silicide film 117 is formed on the gate electrode 115. The silicide layer 117 may function as an ohmic contact region that lowers a resistance between the gate electrode 115 and a plug (not shown) electrically connected to the gate electrode 115. The gate mask 120 is formed on the gate electrode 125. The gate electrode 115 and the silicide layer 117 are formed using the gate mask 120. The gate spacer 125 is formed on side surfaces of the gate electrode 115, the silicide layer 117, and the gate mask 120.

Gate spacer 125 may include silicon nitride and / or oxide. The gate spacer 125 has a step so that the thickness of the upper portion is thinner than the lower portion. For example, the gate spacer 125 may be formed on the lower space region 125a and the lower spacer portion 125a in contact with the raised source / drain 140 region based on the raised source / drain 140. The upper spacer portion 125b is included. In one embodiment according to the invention, the lower spacer portion 125a may comprise a first surface that is substantially parallel to the top surface of the raised source / drain 140 and the upper spacer portion 125b is the first surface. And a second surface substantially perpendicular to and inclined at an angle. The ratio of the thickness of the upper spacer portion 125b to the thickness of the lower spacer portion 125a may be about 1.0: 1.1 to 1.0: 3.0. The lower spacer portion 125a may suppress the raised source / drain 140 from growing in the lateral direction. Thus, active control of the raised source / drain 140 is laterally grown while selectively growing silicon substantially perpendicular to the substrate 100 to obtain an elevated source / drain 140 of desired thickness, The regions can be prevented from being electrically connected to each other.

Since the space between the adjacent upper spacers 125b is relatively large, a process margin of a plug (not shown) electrically connected to the raised source / drain 140 may be secured. That is, since the space of the upper portion of the source / drain 140 which is raised by the first surface of the lower spacer portion 125a and the second surface of the upper spacer 125b is secured, the source / drain 140 raised by the subsequent process is raised. ), It is possible to secure margins due to misalignment. The gate mask 120 and the gate spacer 125 electrically insulate the gate electrodes 115.

First and second contact regions 130 and 135 are formed in the substrate between the word lines. The first and second contact regions 130 and 135 may be formed by implanting ions into the substrate between the gate structures using the gate mask 120 and the gate spacer 125 as a mask. Elevated source / drain 140 is formed on first and second contact regions 130 and 135.

Gate structures are formed on the field region 105 and the peripheral circuit region formed on the side of the word line filling the gate trench. The gate structures are substantially the same or substantially similar to the word line except that they are not recessed. The gate structures may also include recessed gate electrodes. The spacers formed on the sides of the gate structure formed on the peripheral circuit region are substantially the same as or substantially similar to the gate spacers 125.

3 is a cross-sectional view of a semiconductor device, according to example embodiments, cut in the word line direction.

Referring to FIG. 3, the substrate 100 includes an active region and a field region 105. Elevated source / drain 140 is formed on field region 105. Although not shown, a first contact region 130 or a second contact region 135 is formed under the raised source / drain 140. The spacing between the raised sources / drains 140 is formed maintaining a predetermined distance from which the raised sources / drains 140 will not be electrically connected to each other. This is because the source / drain 140 in which the gate spacers (Figs. 2 and 125) are raised is suppressed from growing laterally.

4 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present invention.

Referring to FIG. 4, an isolation layer is formed on the substrate 100 by using an isolation process such as a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process. An active region and a field region 105 are defined in the substrate 100.

A buffer oxide film (not shown) is formed on the substrate 100. The buffer oxide layer may serve to relieve stress generated between a subsequently formed hard mask layer (not shown) and the substrate 100. For example, the buffer oxide layer may be formed using silicon oxide. Also. The buffer oxide layer may be formed using a chemical vapor deposition (CVD) process or a thermal oxidation process.

A hard mask layer (not shown) is formed on the buffer oxide film. The hard mask may be formed using a material having an etch selectivity with respect to the substrate 100 and the buffer oxide layer. For example, the hard mask may be formed using a nitride such as silicon nitride or an oxynitride such as silicon oxynitride. The hard mask may be formed using a chemical vapor deposition process, an atomic layer deposition (ALD) process, or the like.

A photoresist film (not shown) is formed on the hard mask, and then the photoresist film is exposed and developed to form a photoresist pattern (not shown) for patterning the hard mask.

The hard mask is partially etched using the photoresist pattern as an etching mask to form the hard mask on the buffer oxide film. The hard mask exposes a region in which the gate structure is to be buried below the buffer oxide layer. The photoresist pattern may be removed from the hard mask using an ashing process and / or a stripping process.

The exposed substrate 100 is etched using the hard mask as an etch mask to form a trench in which the gate structure is buried. A gate insulating layer 110 is formed on the inner wall of the trench. For example, a thin gate insulating layer 110 is formed on the substrate 100 by thermal oxidation or chemical vapor deposition (CVD). In this case, the gate insulating film 110 is formed only in the active region defined by the field region 105. Referring to FIG. 4, the gate insulating layer 110 is partially formed on the active region of the substrate 100, but may be formed only on the inner wall of the trench. The gate insulating layer 110 may be formed using an oxide such as silicon oxide or a metal oxide having high dielectric constant (high-k). For example, the gate insulating layer 240 may be formed using titanium oxide, zirconium oxide, hafnium oxide, aluminum oxide, or the like. In addition, the gate insulating layer 110 may be formed using a thermal oxidation process, a chemical vapor deposition process, an atomic layer deposition process, or the like.

Referring to FIG. 5, a first conductive film (not shown), a second conductive film (not shown), and a gate insulating film 110 may be buried in the peripheral circuit region and the field region 105 to fill the gate trench. A gate mask layer (not shown) is formed sequentially.

The first conductive layer may be formed using a conductive material such as polysilicon, a metal, or a conductive metal nitride doped with impurities. The first conductive layer may be formed using a low pressure chemical vapor deposition (LPCVD) process, a chemical vapor deposition process, a sputtering process, a plasma enhanced chemical vapor deposition process, a pulse laser deposition process, an atomic layer deposition process, or the like. When the first conductive layer is formed of doped polysilicon, a polysilicon layer is first formed on the gate insulating layer 110 and then impurity diffusion, ion implantation, or in-situ doping process is performed in the polysilicon layer. The first conductive film may be formed by doping impurities.

A second conductive film (not shown) is formed on the first conductive film. The second conductive layer may be formed using metal silicide or metal. For example, the second conductive layer may be formed using tungsten silicide, titanium silicide, cobalt silicide, tungsten, titanium, aluminum, or the like. The second conductive layer may be formed using a chemical vapor deposition process, a sputtering process, a plasma enhanced chemical vapor deposition process, a pulse laser deposition process, an atomic layer deposition process, or the like. In example embodiments, the second conductive layer may have a multilayer structure including a metal silicide layer and a metal layer.

After applying a first photoresist film (not shown) on the gate mask layer, the first photoresist film is exposed and developed to form a first photoresist pattern (not shown). Subsequently, the gate mask layer, the first conductive layer, and the second conductive layer are patterned using the first photoresist pattern as an etching mask to form a gate electrode 115, a silicide layer 117, and a gate on the substrate 100. Word lines including the mask 120 are formed.

Referring to FIG. 6, after an insulating film (not shown) made of nitride such as silicon nitride is formed on the substrate 100 on which the gate structures are formed, the insulating film is anisotropically etched to provide a preliminary gate on each side of the gate structures. The spacer 123 is formed. The thickness of the preliminary gate spacer 123 may be about 10 mm to 1000 mm.

Subsequently, the impurity is implanted into the substrate 100 exposed between the word lines 133 using the preliminary gate spacer 123 as an ion implantation mask by an ion implantation process, and then a heat treatment process is performed. The first contact region 130 and the second contact region 135, which are source / drain regions, may be formed in the substrate 100. In embodiments according to the present invention, the ion implantation process may be a low concentration impurity contact formation process. For example, the first contact region 130 and the second contact region 135 may be formed by implanting impurity ions such as boron, phosphorus, arsenic, indium, or antimony.

An elevated source / drain 140 is formed on the first and second contact regions 130 and 135. Selective epitaxy, for example, by continuously combining dichlorosilane or silicon compound gas supplied to dangling bonds with silicon in the first and second contact regions 130, 135. Earl silicon layer is grown to form raised source / drain 140. In one embodiment according to the present invention, the raw material gas used for the selective epitaxial growth may be performed by introducing a gas containing silicon atoms or germanium atoms respectively or simultaneously. For example, the silicon compound gas may be a silicon source gas, a germanium source gas, a silicon germanium source gas, or a silicon carbide source. The silicon source gas may be a silane gas, disilane, and the germanium source gas may be a GeH ₄ gas. In addition, the silicon germanium source gas may include the silicon source gas and the germanium source gas.

The elevated source / drain 140 grows and contacts the side of the preliminary gate spacer 123. When the preliminary gate spacer 123 is in contact with the raised source / drain 140, the preliminary gate spacer 123 is raised while the raised source / drain 123 grows in a direction perpendicular to the substrate 100. Controlled growth of the source / drain 123 in the transverse direction.

An elevated source / drain 140 is formed over the first and second contact regions 130 and 135 and then impurities, for example, boron, phosphorus, arsenic, indium, are formed in the elevated source / drain region 140. Alternatively, impurity ions such as antimony can be implanted. The impurity implantation may proceed in-situ. The implanted impurities may diffuse to the raised source / drain 140 and the first and second contact regions 130 and 135 under the raised source / drain 140. Therefore, the first and second contact regions 130 and 135 may include a low concentration of impurity regions and a high concentration of impurity regions.

Referring to FIG. 7, a portion of the preliminary gate spacer 123 is etched to form the gate spacer 125. In embodiments according to the present invention, the etching may be isotropic etching. Or dry etching using plasma. For example, capacitively coupled plasma (CCP), inductively coupled plasma (ICP), reactive ion plasma (RIE) or electron cyclotron plasma (ECR) It may be an etching process using.

Gate spacer 125 may include silicon nitride and / or oxide. The gate spacer 125 has a step so that the thickness of the upper portion is thinner than the lower portion. For example, the gate spacer 125 may be formed on the lower space region 125a and the lower spacer portion 125a that contact the raised source / drain 140 region based on the raised source / drain 140. Spacer portion 125b. In one embodiment according to the present invention, the lower spacer portion 125a may include a first surface substantially parallel to the top surface of the raised source / drain 140, and the upper spacer portion 125b may be the first surface. It may include a second surface substantially perpendicular to the surface or inclined at an angle. For example, the thickness of the upper spacer portion 125b may be about 10 mm to 990 mm thinner than the thickness of the lower spacer portion 125a. Alternatively, the ratio of the thickness of the upper spacer portion 125b to the thickness of the lower spacer portion 125a may be about 1.0: 1.1 to 1.0: 3.0. The lower spacer portion 125a may suppress the raised source / drain 140 from growing in the lateral direction.

Due to the difference in thickness between the upper spacer portion 125b and the lower spacer portion 125a, the thickness of the self aligned contact (SAC) generated in a subsequent process may be thicker. This reduces the chance of miss alignment.

In another embodiment according to the present invention, the preliminary gate spacers 123 are formed, the isotropic etching is performed to form the gate spacers 125, and then, the ion implantation process and the selective epitaxial growth process are performed. Source / drain 140 may also be formed.

Although described with reference to the preferred embodiments of the present invention as described above, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be appreciated that it can be changed.

By preventing the growth of silicon in the lateral direction and blocking the interconnection between the silicon patterns, the reliability of the semiconductor device can be improved, the margin for forming the contact plug can be secured, and even if a misalignment occurs. The reliability of the semiconductor device may be improved by preventing the source / drain from being electrically connected to the gate electrode.

2 is a cross-sectional view of a semiconductor device, according to example embodiments, taken along a bit line direction.

3 is a cross-sectional view of a semiconductor device, taken along a word line direction, according to example embodiments.

100: substrate 105: field area

110 gate insulating film 115 gate electrode

120: gate mask 125: gate spacer

130: first contact region 135: second contact region

140: elevated source / drain

Claims

Board;

A gate spacer including a gate structure formed on the substrate and a lower spacer portion formed on a side of the gate structure, the lower spacer portion having a first surface parallel to the substrate and an upper spacer portion having a second surface inclined with the first surface. Word lines; And

And a raised source / drain region formed on a substrate between said word lines.

The semiconductor device of claim 1, wherein a height of the raised source / drain region is equal to a height of the lower spacer portion, and the raised source / drain is parallel to the first surface.

The semiconductor device of claim 2, wherein the lower portion of the gate structure is a structure embedded in a recess formed on a substrate.

The semiconductor device of claim 3, wherein a difference between a thickness of the lower spacer portion and a thickness of the upper spacer is about 10 μs to 990 μs.

The semiconductor device of claim 3, wherein a ratio of the thickness of the lower spacer portion to the thickness of the upper spacer is about 1.0: 1.1 to 1.0: 3.0.

Preparing a substrate;

Forming a gate structure on the substrate, the gate structure including a gate electrode and a mask formed on the gate electrode;

Forming a preliminary gate spacer on a side of the gate structure;

Forming a contact region on a substrate between the gate structures;

Forming a raised source / drain on the contact region; And

Etching the preliminary gate spacer to form a gate spacer including a lower gate spacer portion having a first surface parallel to the raised source / drain and an upper spacer portion having a second surface inclined with the first surface The manufacturing method of the semiconductor element.

The method of claim 6, wherein the etching of the preliminary gate spacers is an isotropic etching process.

The method of claim 7, wherein forming the raised source / drain comprises selectively epitaxially growing a gas containing silicon atoms or germanium atoms, respectively, or simultaneously. .

The method of claim 7, wherein the forming of the gate structure comprises forming a recess in the substrate and filling the gate electrode.