KR20090035914A - Method for forming copper line - Google Patents
Method for forming copper line Download PDFInfo
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- KR20090035914A KR20090035914A KR1020070100949A KR20070100949A KR20090035914A KR 20090035914 A KR20090035914 A KR 20090035914A KR 1020070100949 A KR1020070100949 A KR 1020070100949A KR 20070100949 A KR20070100949 A KR 20070100949A KR 20090035914 A KR20090035914 A KR 20090035914A
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- copper
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 86
- 239000010949 copper Substances 0.000 title claims abstract description 72
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229920003986 novolac Polymers 0.000 claims abstract description 7
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 22
- 230000007257 malfunction Effects 0.000 description 6
- 239000002245 particle Substances 0.000 description 6
- 239000002002 slurry Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 nitrogen ions Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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Abstract
Description
본 발명은 구리 배선 공정에 관한 것으로, 특히 반도체 기판상 구리 배선막에 대한 구리 CMP 공정시 슬러리(slurry)나 옥사이드 파티클(oxide particle)에 의한 구리 배선 표면의 스크래치(scratch)로 인한 구리 잔존물(Cu remain) 발생을 방지시켜 반도체 소자의 오동작 발생률을 낮출 수 있도록 하는 구리 배선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a copper wiring process, and in particular, copper residues due to scratches on the surface of copper wiring by slurry or oxide particles in the copper CMP process on a copper wiring film on a semiconductor substrate. The present invention relates to a copper wiring method which prevents the occurrence thereof and thereby lowers the occurrence rate of malfunction of the semiconductor device.
최근 들어, 트랜지스터 소자 뿐만 아니라 금속 배선의 미세화 및 다층화 요구에 따라 반도체 디바이스(device)의 사이즈(size)는 점점 더 감소되는 추세에 있으며, 이러한 사이즈의 감소로 인한 콘텍홀(contact hole)의 고종횡비(high aspect ratio)에 따라 기존의 알루미늄, 텅스텐을 이용한 금속배선 형성의 경우, 알루미늄 및 텅스텐의 낮은 매립특성 및 높은 저항에 의한 시간 지연의 문제가 발생하게 되는 문제점이 있다. In recent years, the size of semiconductor devices has been gradually reduced in accordance with the demand for miniaturization and multilayering of not only transistor devices but also metal wirings, and high aspect ratio of contact holes due to the reduction in size According to the high aspect ratio, there is a problem in that the formation of metal wires using aluminum and tungsten has a problem of time lag due to low embedding characteristics and high resistance of aluminum and tungsten.
이에 따라 현재는 탄탈륨(Ta) 및 탄탈륨 나이트라이드(TaN)를 확산 방지막으 로 하여 구리 시드(Seed)를 증착 시킨 후, 구리 전착(Electrochemical Plate)법을 통해서 제조되는 구리배선(copper line)을 금속배선(metal line)으로 사용하는 듀얼 다마신(dual damascene) 공법이 고집적 반도체 소자를 위한 금속배선 방법으로 사용되고 있다.As a result, a copper seed is deposited using a copper electrode plate method after depositing a copper seed using tantalum (Ta) and tantalum nitride (TaN) as a diffusion barrier. The dual damascene method, which is used as a metal line, is used as a metal wiring method for highly integrated semiconductor devices.
도 1은 종래 듀얼 다마신 방법을 이용한 구리 배선 공정 모식도를 도시한 것으로, 상기 도 1에서와 같이 먼저 반도체 기판 상에 비아와 트랜치를 형성하여 듀얼 다마신 패턴을 형성시킨 후, 탄탈륨(Ta)으로 구리 배리어(barrier)막을 형성시킨다. 이어 구리 시드(seed)막을 형성하고, 전기 화학 도금 방식(ECP)을 이용하여 절연막(IMD)(100)내 구리 배선막(Cu)(102)을 상기 비아홀 및 트랜치 내에 증착 시켜 구리 배선을 형성시킨 후, CMP(chemical mechanical polishing) 공정을 통해 배선을 완성하게 된다.FIG. 1 illustrates a schematic diagram of a copper wiring process using a conventional dual damascene method. As shown in FIG. 1, vias and trenches are first formed on a semiconductor substrate to form a dual damascene pattern, followed by tantalum (Ta). A copper barrier film is formed. Next, a copper seed film was formed, and a copper wiring film (Cu) 102 in the insulating film (IMD) 100 was deposited in the via hole and the trench by using an electrochemical plating method (ECP) to form a copper wiring. After that, the wiring is completed through a chemical mechanical polishing (CMP) process.
그러나, 상기한 종래 구리 배선에서는 슬러리(slurry)나 옥사이드 파티클에 의해 상기 도 1에서 보여지는 바와 같이 스크래치(104)가 발생하게 되는데, 구리 배선(102) 위의 약한 스크래치의 경우 디바이스에 영향을 미치지 않지만, 옥사이드에까지 영향을 미치는 깊은 스크래치의 경우에는 후속 레이어(layer)에 단차를 형성시켜 도 2에서 보여지는 바와 같이 구리 잔존물(Cu Remain)(106)이 남게 되며, 이러한 구리 잔존물(106)은 금속 배선간 브리지(bridge)를 만들어 소자가 오동작을 유발시키는 문제점이 있었다.However, in the conventional copper wiring, the
따라서 본 발명은 반도체 소자 제조를 위한 구리 배선 형성 방법에 있어서, 반도체 기판상 구리 배선막 형성 후, 반도체 상부 표면에 대한 구리 CMP 공정시 슬러리나 옥사이드 파티클에 의한 구리 배선 표면의 스크래치로 발생되는 구리 잔존물을 구리 배선 공정 시 반도체 기판 표면에 미리 생성한 나이트라이드막을 이용하여 습식식각으로 제거시킴으로써, 구리 잔존물로 인한 금속 배선간 브리지 현상을 방지시켜 반도체 소자의 오동작을 방지시키는 구리 배선 형성 방법을 제공함에 있다.Accordingly, the present invention relates to a method for forming a copper wiring for manufacturing a semiconductor device, wherein after the formation of a copper wiring film on a semiconductor substrate, a copper residue generated by scratching a copper wiring surface by a slurry or oxide particles during a copper CMP process with respect to a semiconductor upper surface In the copper wiring process, by using a nitride film generated on the surface of the semiconductor substrate by wet etching to prevent the bridge between the metal wiring due to the copper residues to provide a method for forming a copper wiring to prevent malfunction of the semiconductor device. .
상술한 본 발명은 구리 배선 형성 방법으로서, 반도체 기판 상 층간 절연막내 하부 금속 배선 연결을 위한 비아홀을 형성시키는 단계와, 상기 비아홀내 감광성 물질을 채운 후 상기 반도체 기판 상부면에 질소 이온주입을 통해 나이트라이드막을 형성시키는 단계와, 상기 비아홀 상부에 트랜치를 식각형성시킨 후, 상기 트랜치와 비아홀 내 구리 베리어막을 형성시키는 단계와, 상기 트랜치와 비아홀내 구리를 증착시켜 구리 배선을 형성시키는 단계와, 상기 반도체 기판 표면에 대한 CMP를 수행한 후, 습식식각을 통해 상기 나이트라이드막을 제거시키는 단계를 포함하는 것을 특징으로 한다.The above-described method of forming a copper wiring includes forming a via hole for connecting a lower metal wiring in an interlayer insulating film on a semiconductor substrate, filling the photosensitive material in the via hole, and then performing nitrogen ions implantation on the upper surface of the semiconductor substrate. Forming a ride film, etching a trench over the via hole, forming a copper barrier film in the trench and the via hole, and depositing copper in the trench and the via hole to form a copper wiring; After performing the CMP on the surface of the substrate, it characterized in that it comprises the step of removing the nitride film by wet etching.
본 발명에서는 반도체 소자 제조를 위한 구리 배선 형성 방법에 있어서, 반도체 기판상 구리 배선막 형성 후, 반도체 상부 표면에 대한 구리 CMP 공정시 슬러리나 옥사이드 파티클에 의한 구리 배선 표면의 스크래치로 발생되는 구리 잔존물을 구리 배선 공정 시 반도체 기판 표면에 미리 생성한 나이트라이드막을 이용하여 습식식각으로 제거시킴으로써, 구리 잔존물로 인한 반도체 소자의 오동작을 방지시켜 반도체 생산 수율을 높일 수 있는 이점이 있다.In the present invention, in the copper wiring forming method for manufacturing a semiconductor device, after forming a copper wiring film on a semiconductor substrate, the copper residue generated by the scratch of the copper wiring surface by the slurry or oxide particles during the copper CMP process to the upper surface of the semiconductor By removing by wet etching using a nitride film previously generated on the surface of the semiconductor substrate during the copper wiring process, there is an advantage that the semiconductor production yield can be improved by preventing malfunction of the semiconductor device due to copper residues.
이하, 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the present invention. In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.
본 발명의 구체적인 핵심 기술요지를 살펴보면, 반도체 기판상 구리 배선막 형성 후, 반도체 상부 표면에 대한 구리 CMP 공정시 슬러리나 옥사이드 파티클에 의한 구리 배선 표면의 스크래치로 발생되는 구리 잔존물을 구리 배선 공정 시 반도체 기판 표면에 미리 생성한 나이트라이드막을 이용하여 습식식각으로 제거시키는 기술을 통해 본 발명에서 이루고자 하는 바를 쉽게 달성할 수 있다.Looking at the specific core technology of the present invention, after forming a copper wiring film on the semiconductor substrate, the copper residue generated by the scratch of the copper wiring surface by the slurry or oxide particles during the copper CMP process on the upper surface of the semiconductor semiconductor during the copper wiring process It is easy to achieve the purpose of the present invention through the technique of wet etching using a nitride film generated on the substrate surface in advance.
도 3a 내지 도 3e는 본 발명의 실시 예에 따른 구리 배선 공정의 모식도를 도시한 것으로, 이하 상기 도 3a 내지 도 3e를 참조하여 구리 CMP 공정 시 구리 배선상 스크래치에 의해 발생하는 구리 잔존물을 제거시키는 본 발명의 구리 배선 공정을 상세히 설명하기로 한다.3A to 3E are schematic views of a copper wiring process according to an embodiment of the present invention. Hereinafter, referring to FIGS. 3A to 3E, copper residues generated by scratches on copper wiring during a copper CMP process are removed. The copper wiring process of the present invention will be described in detail.
먼저 위 도 3a에서와 같이 반도체 기판내 절연막(IMD)(300)상 비아홀을 형성시킨 후, 상기 비아홀 내 감광성 물질인 노볼락(novolak)(302) 수지를 갭필(gap fill)시킨다.First, via holes are formed on the insulating film (IMD) 300 in the semiconductor substrate as shown in FIG. 3A, and then a gap fill of the
이어, 도 3b에서와 같이 비아홀내 노볼락(302) 수지 갭필 공정을 수행한 후, 반도체 기판 전체 표면에 대해 질소(N) 이온주입(implantation) 공정을 수행하여 반도체 기판 표면에 100∼200Å정도의 나이트라이드막(nitride)(304)을 형성시킨다. Subsequently, after performing the
이어, 도 3c에서와 같이 상기 비아홀 상부에 구리 배선 형성을 위한 트랜치(trench)(306)를 식각 형성시킨 후, 비아홀내 갭필된 노볼락(302) 수지를 제거시킨다.Subsequently, as shown in FIG. 3C, a
그런 후, 도 3d에서와 같이 상기 트랜치와 비아홀 내 탄탈륨 나이트라이드(TaN) 또는 탄탈륨(Ta) 등을 증착시켜 구리 배리어막(barrier layer)(308)을 형성시킨 후, 위와 같이 구리 배리어막(308)이 형성된 트랜치와 비아홀 내부에 EMP 방식으로 구리 배선막(310)을 형성시킨다. 이어, 위와 같이 구리 배선막(310)이 형성된 반도체 기판 상부면에 대해 구리 CMP 공정을 수행하여 반도체 기판 표면상 구 리 배선막(310)을 평탄화시키게 되는데, 이때 위 도 3d에서 보여지는 바와 같이 트랜치 상부의 나이트라이드막(304)에 스크래치가 발생하게 되어 구리 잔존물(Cu remain)(312)이 남게 된다.Thereafter, as shown in FIG. 3D, a
위와 같이 구리 CMP 공정 후, 반도체 기판 상부면에 잔존되는 구리 잔존물(312)은 금속 배선간 브리지(bridge)를 형성하여 반도체 소자의 오동작을 일으키는 문제점이 있었음은 전술한 바와 같다.As described above, after the copper CMP process, the
이에 따라, 본 발명에서는 도 3e에서와 같이, 반도체 기판 상부면에 대해 습식식각(wet etch)을 수행하여, 구리 CMP 공정 후, 반도체 기판 상부면에 남겨진 구리 잔존물(312) 및 나이트라이드막(304)을 제거시켜 균일한 절연막만이 남도록 하는 것이다.Accordingly, in the present invention, as shown in Figure 3e, by performing a wet etch (wet etch) on the upper surface of the semiconductor substrate, after the copper CMP process, the
상기한 바와 같이 본 발명에서는 반도체 소자 제조를 위한 구리 배선 형성 방법에 있어서, 반도체 기판상 구리 배선막 형성 후, 반도체 상부 표면에 대한 구리 CMP 공정시 슬러리나 옥사이드 파티클에 의한 구리 배선 표면의 스크래치로 발생되는 구리 잔존물을 구리 배선 공정 시 반도체 기판 표면에 미리 생성한 나이트라이드막을 이용하여 습식식각으로 제거시킴으로써, 구리 잔존물로 인한 금속 배선간 브리지 현상을 방지시켜 반도체 소자의 오동작을 방지시킬 수 있다.As described above, in the present invention, in the copper wiring forming method for manufacturing a semiconductor device, after the copper wiring film is formed on the semiconductor substrate, the copper wiring surface is generated by the slurry or oxide particles during the copper CMP process on the upper surface of the semiconductor. By removing the residual copper residue by wet etching using a nitride film previously generated on the surface of the semiconductor substrate during the copper wiring process, it is possible to prevent the bridge between the metal wiring due to the copper residue to prevent malfunction of the semiconductor device.
한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.
도 1은 종래 구리 배선막상 스크래치에 의해 발생된 구리 잔존물 예시도,1 is an illustration of a copper residue generated by scratch on a conventional copper wiring film,
도 2는 종래 구리 배선막상 구리 잔존물로 인한 금속 배선간 브리지 발생 예시도,2 is a diagram illustrating a generation of bridges between metal wires due to copper residues on a conventional copper wiring film;
도 3a 내지 도 3e는 본 발명의 실시 예에 따른 구리 CMP후 발생되는 구리 잔존물을 제거시키는 구리배선 공정 모식도.3A to 3E are schematic diagrams of a copper wiring process for removing copper residues generated after copper CMP according to an embodiment of the present invention.
<도면의 주요 부호에 대한 간략한 설명><Brief description of the major symbols in the drawings>
300 : 절연막 302 : 노볼락300: insulating film 302: novolac
304 : 나이트라이드막 306 : 트랜치304: nitride film 306: trench
308 : 구리 배리어막 310 : 구리 배선막308: copper barrier film 310: copper wiring film
312 : 구리 잔존물312 copper residue
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| KR20180006254A (en) * | 2016-07-08 | 2018-01-17 | 삼성전자주식회사 | Interconnect structure formed with a high aspect ratio single damascene copper line on a non-damascene via |
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| KR100541153B1 (en) * | 2003-07-18 | 2006-01-11 | 매그나칩 반도체 유한회사 | Method of forming metal line in semiconductor device |
| KR100529654B1 (en) * | 2003-12-31 | 2005-11-17 | 동부아남반도체 주식회사 | Method for fabricating the contact hole for dual damascene interconnection in semiconductor device |
| KR100545221B1 (en) * | 2003-12-31 | 2006-01-24 | 동부아남반도체 주식회사 | Method for fabricating the dual damascene interconnection in semiconductor device |
| KR20070087814A (en) * | 2005-12-16 | 2007-08-29 | 동부일렉트로닉스 주식회사 | Method for forming copper metal line in semiconductor device |
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| KR20180006254A (en) * | 2016-07-08 | 2018-01-17 | 삼성전자주식회사 | Interconnect structure formed with a high aspect ratio single damascene copper line on a non-damascene via |
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