KR20090021752A - Power module package - Google Patents

Power module package Download PDF

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Publication number
KR20090021752A
KR20090021752A KR1020070086541A KR20070086541A KR20090021752A KR 20090021752 A KR20090021752 A KR 20090021752A KR 1020070086541 A KR1020070086541 A KR 1020070086541A KR 20070086541 A KR20070086541 A KR 20070086541A KR 20090021752 A KR20090021752 A KR 20090021752A
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South Korea
Prior art keywords
wiring pattern
power module
module package
semiconductor chip
lead frame
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KR1020070086541A
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Korean (ko)
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KR101391926B1 (en
Inventor
백승한
이근혁
임승원
김명복
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페어차일드코리아반도체 주식회사
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Priority to KR1020070086541A priority Critical patent/KR101391926B1/en
Publication of KR20090021752A publication Critical patent/KR20090021752A/en
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Publication of KR101391926B1 publication Critical patent/KR101391926B1/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A power module package is provided to efficiently discharge the heat by arranging the other end of the lead frame connected to the external terminal on the wiring pattern. A power module package(100) comprises one or more semiconductor chip(150a) for the power controls adhered on a substrate(110); and a low power semiconductor chip(150b) for controlling the semiconductor chips for the power controls. A wiring pattern(130) is formed on the surface of substrate. The first lead frame(170a) is arranged between the wiring pattern and the semiconductor chip for the power control. One end of the first lead frame is connected to the external terminal and the other end of the first lead frame is arranged on the wiring pattern. The other end of the first lead frame is extended in order to be more protruded than the side of the semiconductor chip for the power control on the wiring pattern.

Description

파워 모듈 패키지{Power module package}Power module package

본 발명은 전력 모듈의 패키지에 관한 것으로서, 더욱 상세하게는, 인쇄회로기판을 포함하는 스마트 전력 모듈의 패키지에 관한 것이다.The present invention relates to a package of a power module, and more particularly, to a package of a smart power module including a printed circuit board.

최근 서보 드라이버, 인버터, 전력 레귤레이터 및 컨버터와 같은 전력용 전자 산업이 발전함에 따라, 무게가 가볍고, 크기가 작으면서도 성능이 우수한 전력용 소자에 대한 요구가 증대되고 있다. 이와 같은 추세에 따라, 최근에는 다양한 전력용 반도체 칩들을 하나의 패키지에 집적시킬 뿐만 아니라, 전력용 반도체 칩들을 제어하기 위한 IC 칩과 같은 저전력 반도체 칩들도 하나의 패키지에 수용하는 스마트 또는 인텔리전트 전력 모듈에 대한 연구가 활발하게 이루어지고 있다.Recently, with the development of the power electronics industry such as servo drivers, inverters, power regulators and converters, there is an increasing demand for power devices that are light in weight, small in size, and excellent in performance. In accordance with this trend, smart or intelligent power modules have recently integrated various power semiconductor chips into one package, as well as low power semiconductor chips such as IC chips for controlling power semiconductor chips in one package. There is an active research on.

도 1 및 도 2는 종래의 스마트 전력 모듈 패키지(10)를 도시하는 평면도 및 단면도이다.1 and 2 are a plan view and a cross-sectional view showing a conventional smart power module package 10.

도 1 및 도 2를 참조하면, 스마트 전력 모듈 패키지(10)는 기판(11) 상에 부착된 하나 이상의 전력 제어용 반도체 칩(15a)과 이를 제어하기 위한 저전력 반도체 칩(15b)을 포함한다. 배선 패턴(13)은 기판(11)의 표면에 형성되며, 예를 들어 구리 배선층으로 이루어진 금속층 패턴일 수 있다. 배선 패턴(13)과 기판(11)은 절 연층(12)에 의해 전기적으로 절연되어 격리된다. 배선 패턴(13) 상의 인접하는 복수개의 전력 제어용 반도체 칩(15a) 간에는 제1 와이어 본딩(16a)에 의해 전기적으로 연결된다. 그리고 전력 제어용 반도체 칩(15a)과 배선 패턴(13)은 제2 와이어 본딩(16b)에 의해 전기적으로 연결될 수 있다. 또한 전력 제어용 반도체 칩(15a)은 리드 프레임(17)에 의해 외부 단자와 전기적으로 연결된다. 리드 프레임(17)의 일단은 외부 단자와 연결되며 타단은 배선 패턴(13)을 통하여 전력 제어용 반도체 칩(15a)과 전기적으로 연결된다. 그런데, 전력 제어용 반도체 칩(15a)은 동작시 큰 전류를 요구하므로, 낮은 저항의 전기적 경로를 제공하며 발생되는 고열을 외부로 효율적으로 방출할 수 있는 전력 모듈 패키지(10) 구조에 대한 연구가 진행되고 있다. 1 and 2, the smart power module package 10 includes at least one power control semiconductor chip 15a attached to the substrate 11 and a low power semiconductor chip 15b for controlling the same. The wiring pattern 13 is formed on the surface of the substrate 11 and may be, for example, a metal layer pattern made of a copper wiring layer. The wiring pattern 13 and the substrate 11 are electrically insulated and isolated by the insulating layer 12. The plurality of adjacent power control semiconductor chips 15a on the wiring pattern 13 are electrically connected by the first wire bonding 16a. In addition, the power control semiconductor chip 15a and the wiring pattern 13 may be electrically connected by the second wire bonding 16b. In addition, the power control semiconductor chip 15a is electrically connected to an external terminal by the lead frame 17. One end of the lead frame 17 is connected to an external terminal, and the other end thereof is electrically connected to the power control semiconductor chip 15a through the wiring pattern 13. However, since the power control semiconductor chip 15a requires a large current during operation, a study on the structure of the power module package 10 that provides a low resistance electrical path and efficiently emits high heat generated to the outside is in progress. It is becoming.

본 발명이 해결하고자 하는 기술적 과제는 낮은 저항의 전기적 경로를 가지며 또한 발생되는 열을 효율적으로 외부로 방출할 수 있는 전력 모듈 패키지를 제공하는 데 있다. SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a power module package having a low resistance electrical path and capable of efficiently dissipating generated heat to the outside.

상기 기술적 과제를 달성하기 위한 본 발명의 일실시예에 따른 전력 모듈 패키지는 기판; 상기 기판 상에 배치된 배선 패턴; 상기 배선 패턴 상에 배치되고 상기 배선 패턴들과 전기적으로 연결되는 반도체 칩; 및 일단이 외부 단자와 연결되며 타단이 상기 배선 패턴과 상기 반도체 칩 사이를 지나서 상기 배선 패턴 상에 배치되는 리드 프레임;을 포함한다. 상기 반도체 칩은 전력 제어용 반도체 칩을 포함할 수 있다. 상기 리드 프레임의 높이 방향의 두께는 상기 배선 패턴의 높이 방향의 두께보다 더 큰 것이 바람직하다. 상기 배선 패턴은 구리 또는 구리 합금을 포함하여 구성될 수 있다. 상기 리드 프레임은 솔더링 또는 도전성 에폭시에 의해 상기 배선 패턴에 본딩되는 것이 바람직하다. 한편, 상기 반도체 칩은 솔더링 또는 도전성 에폭시에 의해 상기 리드 프레임에 본딩되는 것이 바람직하다. 상기 배선 패턴과 상기 기판을 전기적으로 격리시키기 위하여 상기 배선 패턴과 상기 기판 사이에 배치되는 절연층을 더 포함할 수 있다. 상기 반도체 칩은 상기 배선 패턴과 와이어에 의해 전기적으로 연결될 수 있다. 추가적으로, 상기 기판 상의 인접하는 복수개의 상기 반도체 칩을 서로 전기적으로 연결하는 굵은 와이어를 더 포함할 수 있다. A power module package according to an embodiment of the present invention for achieving the technical problem is a substrate; A wiring pattern disposed on the substrate; A semiconductor chip disposed on the wiring pattern and electrically connected to the wiring patterns; And a lead frame having one end connected to an external terminal and the other end disposed between the wiring pattern and the semiconductor chip on the wiring pattern. The semiconductor chip may include a power control semiconductor chip. The thickness in the height direction of the lead frame is preferably larger than the thickness in the height direction of the wiring pattern. The wiring pattern may include copper or a copper alloy. The lead frame is preferably bonded to the wiring pattern by soldering or conductive epoxy. On the other hand, the semiconductor chip is preferably bonded to the lead frame by soldering or conductive epoxy. The display device may further include an insulating layer disposed between the wiring pattern and the substrate to electrically isolate the wiring pattern and the substrate. The semiconductor chip may be electrically connected to the wiring pattern by a wire. Additionally, the semiconductor device may further include a thick wire electrically connecting the plurality of adjacent semiconductor chips on the substrate to each other.

상기 기술적 과제를 달성하기 위한 본 발명의 다른 실시예에 따른 전력 모듈 패키지는 상기 기판 상의 인접하는 복수개의 상기 반도체 칩을 서로 전기적으로 연결하는 리본 와이어 또는 금속 클립을 더 포함할 수있다. According to another aspect of the present invention, a power module package may further include a ribbon wire or a metal clip that electrically connects a plurality of adjacent semiconductor chips on the substrate.

본 발명에 따른 전력 모듈 패키지는 외부 단자와 연결되는 리드 프레임의 타단이 배선 패턴과 반도체 칩 사이를 지나서 배선 패턴 상에 배치되므로, 전기적 저항을 개선시킬 수 있으며 또한 기판 방향으로의 효율적인 열배출을 개선시킬 수 있다. In the power module package according to the present invention, since the other end of the lead frame connected to the external terminal is disposed on the wiring pattern between the wiring pattern and the semiconductor chip, the electrical resistance can be improved and the heat dissipation toward the substrate can be improved. You can.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 실시예들은 당해 기술 분야에서 통상의 지식을 가진 자에게 본 발명을 더욱 완전하게 설명하기 위하여 제공되는 것이며, 하기 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 하기 실시예에 한정되는 것은 아니다. 이하의 설명에서 어떤 층이 다른 층의 위에 존재한다고 기술될 때, 이는 다른 층의 바로 위에 존재할 수도 있고, 그 사이에 제3의 층이 게재될 수도 있다. 또한, 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장된 것이며, 도면상에서 동일 부호는 동일한 요소를 지칭한다. 본 명세서에서 사용된 바와 같이, 용어 "및/또는"은 해당 열거된 항목 중 어느 하나 및 하나 이상의 모든 조합을 포함한다.The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following examples can be modified in various other forms, and the scope of the present invention is It is not limited to an Example. In the following description, when a layer is described as being on top of another layer, it may be present directly on top of another layer, with a third layer interposed therebetween. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity, the same reference numerals in the drawings refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

본 명세서에서 제 1, 제 2 등의 용어가 다양한 부재, 부품, 영역, 층들 및/또는 부분들을 설명하기 위하여 사용되지만, 이들 부재, 부품, 영역, 층들 및/또는 부분들은 이들 용어에 의해 한정되어서는 안됨은 자명하다. 이들 용어는 하나의 부재, 부품, 영역, 층 또는 부분을 다른 영역, 층 또는 부분과 구별하기 위하여만 사용된다. 따라서, 이하 상술할 제 1 부재, 부품, 영역, 층 또는 부분은 본 발명의 가르침으로부터 벗어나지 않고서도 제 2 부재, 부품, 영역, 층 또는 부분을 지칭할 수 있다.Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers, and / or parts, these members, parts, regions, layers, and / or parts are defined by these terms. It is obvious that not. These terms are only used to distinguish one member, part, region, layer or portion from another region, layer or portion. Thus, the first member, part, region, layer or portion, which will be discussed below, may refer to the second member, component, region, layer or portion without departing from the teachings of the present invention.

도 3 및 도 4는 본 발명의 일실시예에 따른 전력 모듈 패키지(100)를 도시하는 평면도 및 단면도이다.3 and 4 are a plan view and a cross-sectional view showing a power module package 100 according to an embodiment of the present invention.

도 3 및 도 4를 참조하면, 전력 모듈 패키지(100)는 기판(110) 상에 부착된 하나 이상의 전력 제어용 반도체 칩(150a)과 이를 제어하기 위한 저전력 반도체 칩(150b)을 포함한다. 배선 패턴(130)은 기판(110)의 표면에 형성되며, 예를 들어 구리 또는 구리합금을 포함하여 구성된 금속층 패턴일 수 있다. 이 경우 구리 배선층은 우수한 전기전도성을 제공하며, 구리 배선층 상에 산화방지막으로 니켈층이 더 형성될 수 있다. 그리고 니켈층은 구리 배선층에 대한 피복성이 우수하지 못하여 니켈층 역시 산화되는 문제점이 있으므로 니켈층 상에 다시 금층을 적층하기도 한다. 그러나 배선 패턴(130)은 이러한 구성에 한정되지 않으며 우수한 전기전도도를 가지는 금속 또는 금속합금을 포함하여 구성될 수 있다. 예를 들어 배선 패턴(130)은 알루미늄 또는 알루미늄 합금을 포함하여 구성될 수 있다. 기판(110)은 바람직하게는 인쇄회로기판(PCB)일 수 있다. 배선 패턴(130)과 기판(110)을 전기적으로 절연시키기 위하여 그 사이에 절연층(120)이 더 형성될 수 있다. 상기 절연층(120)은 Al2O3와 같은 세라믹 또는 실리콘질화물층일 수 있다. 3 and 4, the power module package 100 includes at least one power control semiconductor chip 150a attached to the substrate 110 and a low power semiconductor chip 150b for controlling the same. The wiring pattern 130 is formed on the surface of the substrate 110 and may be, for example, a metal layer pattern including copper or a copper alloy. In this case, the copper wiring layer provides excellent electrical conductivity, and a nickel layer may be further formed as an anti-oxidation film on the copper wiring layer. In addition, since the nickel layer does not have excellent coating property on the copper wiring layer, the nickel layer is also oxidized, and thus the gold layer may be further stacked on the nickel layer. However, the wiring pattern 130 is not limited to this configuration and may include a metal or metal alloy having excellent electrical conductivity. For example, the wiring pattern 130 may include aluminum or an aluminum alloy. The substrate 110 may be preferably a printed circuit board (PCB). An insulating layer 120 may be further formed therebetween to electrically insulate the wiring pattern 130 and the substrate 110. The insulating layer 120 may be a ceramic or silicon nitride layer such as Al 2 O 3 .

배선 패턴(130) 상에 전력 제어용 반도체 칩(150a) 및/또는 전력 제어용 반도체 칩(150a)을 구동하는 저전력 반도체 칩(150b)이 배치된다. 기판(110) 상의 인접하는 복수개의 전력 제어용 반도체 칩(150a) 간에는 제1 와이어(160a)에 의해 전기적으로 연결된다. 전력 제어용 반도체 칩(150a)은 배선 패턴(130)과 제2 와이어(160b)에 의해 전기적으로 연결될 수 있다. 제1 와이어(160a) 및/또는 제2 와이어(160b)는 굵은 와이어 및/또는 얇은 와이어일 수 있으며, 스티치 본딩 또는 볼 본딩에 의해 연결될 수 있고, 알루미늄, 구리 또는 금을 포함하여 구성될 수 있다. The low power semiconductor chip 150b for driving the power control semiconductor chip 150a and / or the power control semiconductor chip 150a is disposed on the wiring pattern 130. The plurality of adjacent power control semiconductor chips 150a on the substrate 110 are electrically connected by the first wire 160a. The power control semiconductor chip 150a may be electrically connected to the wiring pattern 130 by the second wire 160b. The first wire 160a and / or the second wire 160b may be thick wires and / or thin wires, may be connected by stitch bonding or ball bonding, and may include aluminum, copper, or gold. .

배선 패턴(130)과 전력 제어용 반도체 칩(150a) 사이에는 제1 리드 프레임(170a)이 배치된다. 제1 리드 프레임(170a)의 일단은 외부 단자(미도시)와 연결되며 제1 리드 프레임(170a)의 타단은 배선 패턴(130)과 전력 제어용 반도체 칩(150a) 사이를 지나서 배선 패턴(130) 상에 배치된다. 즉, 제1 리드 프레임(170a)의 타단은 배선 패턴(130) 상에서 전력 제어용 반도체 칩(150a)의 측면보다 더 돌출되도록 신장되는 것이 바람직하다. 제1 리드 프레임(170a)의 높이 방향의 두께(T1)는 배선 패턴(130)의 높이 방향의 두께(T2)보다 더 큰 것이 바람직하다. 제1 리드 프레임(170a)은 금속 또는 금속합금을 포함하여 구성될 수 있으며 상기 외부 단자와 동일한 재질로 구성될 수 있다. 제1 리드 프레임(170a)은 솔더링 또는 도전성 에폭시(140a)에 의해 배선 패턴(130)에 본딩될 수 있으며, 전력 제어용 반도체 칩(150a)은 솔더링 또는 도전성 에폭시(140b)에 의해 제1 리드 프레임(170a)에 본딩될 수 있다. 종래에는 제1 리드 프레임(170a)이 전력 제어용 반도체 칩(150a)의 하단에 배치되지 않고 배선 패턴(130) 상에 배치되어 전기적 저항 측면에서 불리하였으며 또한 전력 제어용 반도체 칩(150a)에서 발생하는 열을 방출하는 측면에서도 불리하였다. 본 발명에서처럼 제1 리드 프레임(170a)이 배선 패턴(130)과 전력 제어용 반도체 칩(150a) 사이에도 배치되고, 또한 두꺼운 금속 재질로 구성되어 전기적 저항을 개선할 수 있으며 원활한 열방출도 가능하게 한다. 한편, 도 3의 평면도를 참조하면 기판(110) 상에 배치되는 제1 리드 프레임(170a) 및 제3 리드 프레임(170c)은 제2 리드 프레임(170b)을 중심으로 대칭적으로 배치되는 것이 바람직하다. 그리고 제1 리드 프레임(170a), 제2 리드 프레임(170b) 및 제3 리드 프레임(170c)은 높이 방향의 두께가 동일한 것이 바람직하다. The first lead frame 170a is disposed between the wiring pattern 130 and the power control semiconductor chip 150a. One end of the first lead frame 170a is connected to an external terminal (not shown), and the other end of the first lead frame 170a passes between the wiring pattern 130 and the power control semiconductor chip 150a to form the wiring pattern 130. Is disposed on. That is, the other end of the first lead frame 170a may be extended to protrude more than the side surface of the power control semiconductor chip 150a on the wiring pattern 130. The thickness T1 in the height direction of the first lead frame 170a is preferably larger than the thickness T2 in the height direction of the wiring pattern 130. The first lead frame 170a may include a metal or a metal alloy and may be made of the same material as the external terminal. The first lead frame 170a may be bonded to the wiring pattern 130 by soldering or conductive epoxy 140a, and the power control semiconductor chip 150a may be bonded to the first lead frame by soldering or conductive epoxy 140b. May be bonded to 170a). Conventionally, the first lead frame 170a is not disposed at the bottom of the power control semiconductor chip 150a, but is disposed on the wiring pattern 130 to be disadvantageous in terms of electrical resistance, and heat generated from the power control semiconductor chip 150a is also known. It was also disadvantageous in terms of emitting As in the present invention, the first lead frame 170a is also disposed between the wiring pattern 130 and the power control semiconductor chip 150a, and is made of a thick metal material to improve electrical resistance and to facilitate heat dissipation. . Meanwhile, referring to the plan view of FIG. 3, the first lead frame 170a and the third lead frame 170c disposed on the substrate 110 may be symmetrically disposed about the second lead frame 170b. Do. The first lead frame 170a, the second lead frame 170b, and the third lead frame 170c preferably have the same thickness in the height direction.

기판(110) 상에 적층된 배선 패턴(130) 및 전력 제어용 반도체 칩(150a)을 둘러싸서 보호하는 몰딩부(180)가 형성될 수 있는데 몰딩부(180)는 에폭시 계열 복합물(epoxy based compound)을 포함하여 구성될 수 있다. 기판(110)의 면 중에서 배선 패턴(130)이 적층되는 면과 반대방향의 면은 외부에 노출될 수 있다. 한편, 기판(110)의 저면 상에 열방출을 위한 방열판(미도시)과 접촉하는 기저 금속층(미도시)을 더 포함할 수 있다. A molding unit 180 may be formed to surround and protect the wiring pattern 130 and the power control semiconductor chip 150a stacked on the substrate 110. The molding unit 180 may be an epoxy based compound. It may be configured to include. The surface of the substrate 110 opposite to the surface on which the wiring pattern 130 is stacked may be exposed to the outside. On the other hand, the bottom of the substrate 110 may further include a base metal layer (not shown) in contact with the heat sink (not shown) for heat dissipation.

도 5 및 도 6은 본 발명의 다른 실시예들에 따른 전력 모듈 패키지를 도시하는 평면도들이다.5 and 6 are plan views illustrating a power module package according to other embodiments of the present invention.

먼저 도 5를 참조하면, 기판 상의 인접하는 복수개의 전력 제어용 반도체 칩(150a) 간에는 리본 와이어(190)에 의해 전기적으로 연결된다. 리본 와이어(190)는 바람직하게는 사각형 모양이 바람직하며 전력 제어용 반도체 칩(150a)과 제1영역(190b)에서 본딩될 수 있다. 제1영역(190b) 사이에는 제2영역(190a)이 연결되어 전기적으로 연결될 수 있다. 그 외의 다른 구성에 대한 설명은 도 3 및 도 4를 참조하여 설명한 본 발명의 일실시예의 경우와 동일하므로 여기에서는 생략한다. First, referring to FIG. 5, a plurality of adjacent power control semiconductor chips 150a on a substrate are electrically connected by a ribbon wire 190. The ribbon wire 190 is preferably rectangular in shape and may be bonded in the power control semiconductor chip 150a and the first region 190b. The second region 190a may be connected and electrically connected between the first regions 190b. Description of other configurations is the same as in the case of the embodiment of the present invention described with reference to FIGS. 3 and 4 and will be omitted here.

한편, 도 6을 참조하면, 기판 상의 인접하는 복수개의 전력 제어용 반도체 칩(150a) 간에는 금속 클립(200)에 의해 전기적으로 연결된다. 금속 클립(200)은 바람직하게는 사각형 모양이 바람직하며 전력 제어용 반도체 칩(150a)과 제1영역(200b)에서 본딩될 수 있다. 제1영역(200b) 사이에는 제2영역(200a)이 연결되어 전기적으로 연결될 수 있다. 그 외의 다른 구성에 대한 설명은 도 3 및 도 4를 참조하여 설명한 본 발명의 일실시예의 경우와 동일하므로 여기에서는 생략한다. Meanwhile, referring to FIG. 6, the plurality of adjacent power control semiconductor chips 150a on the substrate are electrically connected by the metal clip 200. The metal clip 200 is preferably rectangular in shape and may be bonded in the power control semiconductor chip 150a and the first region 200b. The second region 200a may be electrically connected between the first regions 200b. Description of other configurations is the same as in the case of the embodiment of the present invention described with reference to FIGS. 3 and 4 and will be omitted here.

도 1 및 도 2는 종래의 스마트 전력 모듈 패키지(10)를 도시하는 평면도 및 단면도이다.1 and 2 are a plan view and a cross-sectional view showing a conventional smart power module package 10.

도 3 및 도 4는 본 발명의 일실시예에 따른 전력 모듈 패키지(100)를 도시하는 평면도 및 단면도이다.3 and 4 are a plan view and a cross-sectional view showing a power module package 100 according to an embodiment of the present invention.

도 5 및 도 6은 본 발명의 다른 실시예들에 따른 전력 모듈 패키지를 도시하는 평면도들이다.5 and 6 are plan views illustrating a power module package according to other embodiments of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

110: 기판 120: 절연층110: substrate 120: insulating layer

130: 배선 패턴 150a: 전력 제어용 반도체 칩130: wiring pattern 150a: semiconductor chip for power control

170a : 리드 프레임170a: lead frame

Claims (20)

기판;Board; 상기 기판 상에 배치된 배선 패턴;A wiring pattern disposed on the substrate; 상기 배선 패턴 상에 배치되고 상기 배선 패턴들과 전기적으로 연결되는 반도체 칩; 및A semiconductor chip disposed on the wiring pattern and electrically connected to the wiring patterns; And 일단이 외부 단자와 연결되며 타단이 상기 배선 패턴과 상기 반도체 칩 사이를 지나서 상기 배선 패턴 상에 배치되는 리드 프레임;을 포함하는 파워 모듈 패키지.And a lead frame having one end connected to an external terminal and the other end passing between the wiring pattern and the semiconductor chip and disposed on the wiring pattern. 제1항에 있어서, 상기 반도체 칩은 전력 제어용 반도체 칩을 포함하는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein the semiconductor chip comprises a power control semiconductor chip. 제1항에 있어서, 상기 리드 프레임의 높이 방향의 두께는 상기 배선 패턴의 높이 방향의 두께보다 더 큰 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein a thickness in the height direction of the lead frame is greater than a thickness in the height direction of the wiring pattern. 제1항에 있어서, 상기 배선 패턴은 구리 또는 구리 합금을 포함하여 구성되는 배선 패턴인 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein the wiring pattern is a wiring pattern including copper or a copper alloy. 제1항에 있어서, 상기 배선 패턴은 알루미늄 또는 알루미늄 합금을 포함하여 구성되는 배선 패턴인 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein the wiring pattern is a wiring pattern including aluminum or an aluminum alloy. 제1항에 있어서, 상기 리드 프레임은 솔더링 또는 도전성 에폭시에 의해 상기 배선 패턴에 본딩되는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein the lead frame is bonded to the wiring pattern by soldering or conductive epoxy. 제1항에 있어서, 상기 반도체 칩은 솔더링 또는 도전성 에폭시에 의해 상기 리드 프레임에 본딩되는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein the semiconductor chip is bonded to the lead frame by soldering or conductive epoxy. 제1항에 있어서, 상기 배선 패턴과 상기 기판을 전기적으로 격리시키기 위하여 상기 배선 패턴과 상기 기판 사이에 배치되는 절연층을 더 포함하는 파워 모듈 패키지. The power module package of claim 1, further comprising an insulating layer disposed between the wiring pattern and the substrate to electrically isolate the wiring pattern and the substrate. 제1항에 있어서, 상기 반도체 칩은 상기 배선 패턴과 와이어에 의해 전기적으로 연결되는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein the semiconductor chip is electrically connected to the wiring pattern by a wire. 제1항에 있어서, 상기 기판 상의 인접하는 복수개의 상기 반도체 칩을 서로 전기적으로 연결하는 와이어를 더 포함하는 파워 모듈 패키지.The power module package of claim 1, further comprising wires electrically connecting the plurality of adjacent semiconductor chips on the substrate to each other. 제1항에 있어서, 상기 기판 상의 인접하는 복수개의 상기 반도체 칩을 서로 전기적으로 연결하는 리본 와이어 또는 금속 클립을 더 포함하는 파워 모듈 패키 지.The power module package of claim 1, further comprising a ribbon wire or a metal clip electrically connecting the plurality of adjacent semiconductor chips on the substrate to each other. 제1항에 있어서, 상기 리드 프레임은 금속 또는 금속합금을 포함하여 구성되는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, wherein the lead frame comprises a metal or a metal alloy. 제12항에 있어서, 상기 리드 프레임과 상기 외부 단자는 동일한 재질로 구성되는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 12, wherein the lead frame and the external terminal are made of the same material. 제1항에 있어서, 상기 기판 상에 적층된 상기 배선 패턴 및 상기 반도체 칩을 둘러싸서 보호하는 몰딩부를 더 포함하는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 1, further comprising a molding part surrounding and protecting the wiring pattern and the semiconductor chip stacked on the substrate. 제14항에 있어서, 상기 몰딩부는 에폭시계 복합물을 포함하여 구성되는 파워 모듈 패키지.The power module package of claim 14, wherein the molding part comprises an epoxy-based composite. 제14항에 있어서, 상기 기판의 면 중에서 상기 배선 패턴이 적층되는 면과 반대방향의 면은 외부에 노출되는 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 14, wherein a surface in a direction opposite to a surface of the substrate on which the wiring pattern is stacked is exposed to the outside. 절연성 기판;Insulating substrates; 상기 절연성 기판 상에 배치된 배선 패턴;A wiring pattern disposed on the insulating substrate; 상기 배선 패턴 상에 배치되고 상기 배선 패턴들과 전기적으로 연결되는 전력 제어용 반도체 칩 및/또는 상기 전력 제어용 반도체 칩을 구동하는 저전력 반도체 칩; 및A low power semiconductor chip disposed on the wiring pattern and driving the power control semiconductor chip and / or the power control semiconductor chip electrically connected to the wiring patterns; And 일단이 외부 단자와 연결되며 타단이 상기 배선 패턴과 상기 전력 제어용 반도체 칩 사이를 지나서 상기 배선 패턴 상에 배치되는 리드 프레임;을 포함하는 파워 모듈 패키지.And a lead frame having one end connected to an external terminal and the other end passing between the wiring pattern and the power control semiconductor chip and disposed on the wiring pattern. 제17항에 있어서, 상기 리드 프레임의 높이 방향의 두께는 상기 배선 패턴의 높이 방향의 두께보다 더 큰 것을 특징으로 하는 파워 모듈 패키지.The power module package of claim 17, wherein a thickness in the height direction of the lead frame is larger than a thickness in the height direction of the wiring pattern. 제17에 있어서, 상기 절연성 기판 상의 인접하는 복수개의 상기 전력 제어용 반도체 칩을 서로 전기적으로 연결하는 와이어를 더 포함하는 파워 모듈 패키지.The power module package of claim 17, further comprising wires electrically connecting the plurality of adjacent power control semiconductor chips on the insulating substrate to each other. 제17항에 있어서, 상기 절연성 기판 상의 인접하는 복수개의 상기 전력 제어용 반도체 칩을 서로 전기적으로 연결하는 리본 와이어 또는 금속 클립을 더 포함하는 파워 모듈 패키지.18. The power module package of claim 17, further comprising a ribbon wire or metal clip electrically connecting the plurality of adjacent power control semiconductor chips on the insulating substrate to each other.
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CN103094222A (en) * 2011-10-27 2013-05-08 三星电机株式会社 Semiconductor Package And Method For Manufacturing The Same And Semiconductor Package Module Having The Same
KR101629470B1 (en) * 2015-06-29 2016-06-14 주식회사 에코세미텍 Power semiconductor module assembly process and power semiconductor module using the same

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JP3096536B2 (en) * 1993-03-25 2000-10-10 三洋電機株式会社 Hybrid integrated circuit
JP2002076197A (en) * 2000-08-24 2002-03-15 Toshiba Corp Board for semiconductor device and semiconductor device
TWI257164B (en) * 2005-04-01 2006-06-21 Cyntec Co Ltd Package structure having mixed circuit and complex substrate

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Publication number Priority date Publication date Assignee Title
CN103094222A (en) * 2011-10-27 2013-05-08 三星电机株式会社 Semiconductor Package And Method For Manufacturing The Same And Semiconductor Package Module Having The Same
KR101354894B1 (en) * 2011-10-27 2014-01-23 삼성전기주식회사 Semiconductor package and method for manufacturing the same and semiconductor package module having the same
US8786064B2 (en) 2011-10-27 2014-07-22 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method for manufacturing the same and semiconductor package module having the same
KR101629470B1 (en) * 2015-06-29 2016-06-14 주식회사 에코세미텍 Power semiconductor module assembly process and power semiconductor module using the same

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