KR20090001052A - A overlay mark of a semiconductor device and method for forming the same - Google Patents

A overlay mark of a semiconductor device and method for forming the same Download PDF

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Publication number
KR20090001052A
KR20090001052A KR1020070065122A KR20070065122A KR20090001052A KR 20090001052 A KR20090001052 A KR 20090001052A KR 1020070065122 A KR1020070065122 A KR 1020070065122A KR 20070065122 A KR20070065122 A KR 20070065122A KR 20090001052 A KR20090001052 A KR 20090001052A
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South Korea
Prior art keywords
conductor
semiconductor device
forming
planar structure
contact
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KR1020070065122A
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Korean (ko)
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KR100979356B1 (en
Inventor
서재욱
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주식회사 하이닉스반도체
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Priority to KR1020070065122A priority Critical patent/KR100979356B1/en
Publication of KR20090001052A publication Critical patent/KR20090001052A/en
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Publication of KR100979356B1 publication Critical patent/KR100979356B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An overlay mark of the semiconductor device and a method for forming the same are provided to predict the overlay of cell on a real time basis by detecting the number of deformity by the voltage contrast detection principle of the electron beam defect inspection. A cross section of the conductor(11) is the straight line. The conductor is provided to one side of the semiconductor substrate. A plurality of contact plugs(17) are formed on the other side corresponding to the cross section of the conductor. The plurality of contact plugs are arranged with the planar structure of being crossed of triangle. The corner of the planar structure of triangle is located on the conductor. The plurality of contact plugs are distanced from the corner with the regular interval. The plurality of contact plugs are arranged to be crossed over each other.

Description

A overlay mark of a semiconductor device and method for forming the same

1 is a plan view showing an overlap mark of a typical semiconductor device.

2 is a cross-sectional view and a plan view showing the principles of the present invention.

3 to 7 are plan and cross-sectional views showing overlapping marks of the semiconductor device according to the present invention.

The present invention relates to a superimposition mark of a semiconductor device and a method of forming the same. In particular, the superimposition mark of a semiconductor device is superimposed based on an electrical operation of an actual semiconductor device using a voltage contrast detection principle of an electron beam defect inspection device. The present invention provides a superimposition mark of a semiconductor device and a method of forming the same so that the drawing can be measured.

In general, the method of measuring the degree of overlap between layers of a semiconductor device is a box-in-box by superimposing a box pattern made in a base layer during wafer patterning with a small box pattern formed in a layer in progress (hereinafter referred to as a "current layer"). After forming the overlap mark, the degree of misalignment between the center coordinates of each box pattern was coordinated and measured.

With this mechanism, conventional overlap marks form a mask in the form of a box in a box, bar in bar, box in bar, bar in box, or a combination thereof. The degree of overlap was measured using this.

1 is a plan view showing a general superimposed mark used in the prior art.

However, in the semiconductor manufacturing process of implementing a large-capacity fine pattern, a pattern deterioration phenomenon in which pattern characteristics are deteriorated according to the pattern shape and size in the overlap marks used in the past is applied as a CMP process for leveling a step or an etch back process for forming a plug is applied. This occurred.

As a result, when measuring the overlapping level, the measurement equipment recognizes the overlapping mark image, which causes an error and makes it difficult to measure the exact degree of alignment.

If this occurs severely, the overlapping measurement cannot represent the degree of alignment between the actual main cell patterns, so in the critical layer where the misalignment range must be managed very small, the measurement error component directly affects the overlap between layers. This may cause deterioration or fail of the device.

In addition, since the measurement is performed in place of the degree of overlap of the actual cells, there is the overlap and mismatching of the actual cells. Since the overlapping level measured by the overlapping mark is mismatched even when the overlapping degree is good, the cells may be misaligned. In the fab line, the cell may be decapped to measure the overlapping degree of the actual cell. It is frequently used to measure and calibrate manually. This is a very difficult task and there is a disadvantage that the overlapping cannot be confirmed in real time during the exposure process using the photo mask.

In addition, the effect of the actual overlapping value on the device operation is unknown. The prior art does not know the degree of adversely affecting cell operation even if the superimposition value is properly measured. It is not known whether or not it affects the actual cell operation until the lot is fab out and the electrical characteristics are checked.

In addition, there is a process in which the overlap mark is difficult to measure because the degree of etching of the overlap mark is different from that of the cell during the etching process according to a method such as CMP, wet or dry. Since all the processes are performed based on the cell circuits, the overlap marks present in the scribe line may be excessively etched or not sufficiently etched, and problems of accurate overlapping measurement may be difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide an overlapping mark of a semiconductor device and a method of forming the same, which detects the number of defects and estimates the degree of overlap of real cells in real time by a voltage contrast detection technique of a commercially available electron beam defect inspection apparatus.

The overlap mark of the semiconductor device according to the present invention,

A conductor having a straight section on one side of the semiconductor substrate is provided.

A plurality of contact plugs arranged in a triangular planar structure alternately provided to the other side corresponding to a cross section of the conductor,

Wherein the plurality of contact plugs are vertex portions that are equiangular in the triangular planar structure is located on the conductor side,

The plurality of contact plugs are formed to be alternately arranged to be separated from each other by a predetermined unit from the vertex portion of the triangular planar structure,

The semiconductor substrate is characterized in that the lower insulating layer formed with one of a device isolation film, a word line, a bit line, a capacitor, a metal wiring, a fuse, and a combination thereof are formed.

In addition, in order to achieve the above object, the method of forming an overlap mark of a semiconductor device according to the present invention,

Patterning a conductor having a straight cross section on the semiconductor substrate;

Forming an interlayer insulating film over the entire surface;

Etching the interlayer insulating film to form a plurality of contact holes arranged in a triangular planar structure alternately to the other side corresponding to a straight cross section of the conductor;

Forming a contact plug to fill the contact hole;

The plurality of contact holes are formed by positioning the vertex portion of the triangular planar structure on the conductor side,

The plurality of contact holes are formed by staggering each other to be separated by a predetermined unit from the vertex portion of the triangular planar structure,

The semiconductor substrate is characterized in that the lower insulating layer formed with one of a device isolation film, a word line, a bit line, a capacitor, a metal wiring, a fuse, and a combination thereof are formed.

Meanwhile, referring to FIG. 2, the principle of the present invention will be described.

When contact holes are formed in the insulating layer on the semiconductor substrate, voltage contrast is generated between the open contact holes (left side of FIG. 2) and the unopened contact holes (right side of FIG. 2) due to the difference in the degree of charging during electron beam irradiation. Done.

At this time, the contact hole on the left side connected to the lower conductive layer is opened and electrons are not charged and flows downward, so that the + charge is not charged, but the electron is occupied on the right side of the contact hole where the contact hole is not opened. And since the + charge is charged, an image difference occurs due to the voltage contrast on the left and right sides.

Here, the image due to the voltage contrast is shown brightly in the contact hole portion on the left side where no electrons are occupied, and black in the contact hole portion on the right side where the electrons are occupied.

As a result, as shown in the SEM image, a portion where the contact hole is not connected to the conductor, that is, a portion where the contact hole is not fully opened, is formed by detecting a black image.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 to 7 illustrate a superimposed mark and a method of forming the semiconductor device according to the present invention, which are formed using the same process as the cell.

FIG. 3 is a plan view illustrating overlap marks of semiconductor devices formed by measuring contact points by staggering contact holes when the target conductors to be measured exist, and an enlarged view of part ⓐ of FIG. 3. It is.

Referring to FIG. 3, a conductor 11 having a straight section on one side is provided, and a plurality of contact plugs 17 are alternately formed on the other side corresponding to the cross section of the conductor 11.

At this time, the plurality of contact plugs 17 are arranged in a planar structure of triangles (particularly an isosceles triangle) staggered from each other by being spaced apart by a predetermined unit from one side of the conductor 11 on one side, and a vertex part (particularly an isosceles of a triangle) The points where the parts meet, that is, the corners of the conformal part, are arranged to be adjacent to the conductor 11.

Here, the predetermined unit is formed away from the conductor 11 side, such as 1 nm unit or 1 μm unit.

4 to 7 are enlarged plan views of ⓑ of FIG. 3, and lower portions of FIGS. 4 to 6 show cross-sectional views taken along cut lines -ⓧ, ⓨ-ⓨ and ⓩ-ⓩ of the plan views, respectively.

A method of forming an overlap mark of a semiconductor device will now be described with reference to FIGS. 4 to 7.

First, the conductor 11 is patterned on a semiconductor substrate. The semiconductor substrate may be formed by forming a lower insulating layer having a predetermined structure formed thereon. In this case, the predetermined structure is one in which an isolation layer, a word line, a bit line, a capacitor, a metal wiring, a fuse, and a combination thereof are formed.

An interlayer insulating film 13 is formed over the entire surface, and a contact hole 15 for forming an overlap mark is formed.

Here, the process of forming the contact hole 15 is as follows.

First, a photosensitive film is coated on the interlayer insulating film 13.

A photosensitive film pattern is formed by an exposure and development process using an exposure mask capable of forming the planar structure of FIG. 3.

Next, the interlayer insulating layer 13 is etched using the photoresist pattern as a mask to form the contact hole 15.

Then, the contact plug 17 filling the contact hole 15 is formed.

In this case, the process of forming the contact plug 17 is formed by forming a contact plug conductor filling the contact hole 15 on the entire surface and etching the exposed interlayer insulating film 13. Here, the etching process of the contact plug conductor is carried out using a front surface etching process such as an etch back or a CMP process.

4 shows that no contact plug 17 is connected to the conductor 11 so that an image difference due to voltage contrast does not occur, so that no defect is detected during defect inspection.

5 shows that one contact plug 17 is connected to the conductor 11 so that an image difference due to voltage contrast is generated, so that one defect is detected during defect inspection.

FIG. 6 shows that three contact plugs 17 are connected to a conductor so that an image difference due to voltage contrast is generated, so that three defects are detected during defect inspection.

FIG. 7 is a plan view illustrating a phenomenon in which the number of the contact plugs 17 overlapping the conductors 11 varies according to the CD size of the contact plug 17. The upper side shows a normal CD size, and the center is a CD. The case where the size is increased 1 nm is shown, and the lower side shows the case where the CD size is formed 2 nm larger.

At this time, when the CD size of the contact plug 17 is normal, no defect is detected. When the CD size of the contact plug 17 is 1 nm larger, one defect is detected, and the CD size is 2 nm larger. In this case, three defects are detected.

As described above, the overlapping mark of the semiconductor device and the method of forming the semiconductor device according to the present invention include a plurality of contacts alternately arranged in a triangular planar structure such that a conductor having a straight cross section on one side and a vertex portion on the other side are adjacent to each other. Providing a superimposition mark with a plug provides an effect of easily detecting the number of defects in real time using voltage contrast according to the number of contact plugs and conductors being connected. In addition, the same process as the cell provides the effect of improving the accuracy.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

A conductor having a straight section on one side of the semiconductor substrate is provided. The overlap mark of the semiconductor device, characterized in that a plurality of contact plugs are arranged in a triangular planar structure alternately to the other side corresponding to the cross section of the conductor. The method of claim 1, The plurality of contact plugs are overlap marks of the semiconductor device, characterized in that the vertex portion that is conformal in the triangular planar structure is located on the conductor side. The method of claim 1, The plurality of contact plugs are overlap marks of a semiconductor device, characterized in that formed to be staggered with each other so as to be separated by a predetermined unit from the vertex portion of the triangular plane structure. The method of claim 1, The semiconductor substrate is an overlap mark of a semiconductor device, characterized in that the lower insulating layer formed of one of the device isolation film, word line, bit line, capacitor, metal wiring, fuse and a combination thereof is formed. Patterning a conductor having a straight cross section on the semiconductor substrate; Forming an interlayer insulating film over the entire surface; Etching the interlayer insulating film to form a plurality of contact holes arranged in a triangular planar structure alternately to the other side corresponding to a straight cross section of the conductor; And forming a contact plug to fill the contact hole. The method of claim 5, wherein And the plurality of contact holes are formed by placing a vertex portion of the triangular planar structure on a conductor side. The method of claim 5, wherein And the plurality of contact holes are alternately arranged to be separated from each other by a predetermined unit from the vertex portion of the triangular planar structure. The method of claim 5, wherein The semiconductor substrate is a method of forming an overlap mark of a semiconductor device, characterized in that the lower insulating layer formed of one of a device isolation film, a word line, a bit line, a capacitor, a metal wiring, a fuse, and a combination thereof.
KR1020070065122A 2007-06-29 2007-06-29 A overlay mark of a semiconductor device and method for forming the same KR100979356B1 (en)

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KR1020070065122A KR100979356B1 (en) 2007-06-29 2007-06-29 A overlay mark of a semiconductor device and method for forming the same

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Application Number Priority Date Filing Date Title
KR1020070065122A KR100979356B1 (en) 2007-06-29 2007-06-29 A overlay mark of a semiconductor device and method for forming the same

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KR100979356B1 KR100979356B1 (en) 2010-08-31

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019115391A1 (en) * 2017-12-11 2019-06-20 Asml Netherlands B.V. Voltage contrast metrology mark

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162102A (en) * 1995-12-07 1997-06-20 Mitsubishi Electric Corp Alignment mark detecting method
US6236222B1 (en) 1997-11-19 2001-05-22 Philips Electronics North America Corp. Method and apparatus for detecting misalignments in interconnect structures
KR100518219B1 (en) 1999-11-02 2005-10-04 주식회사 하이닉스반도체 alignment key of semiconductor device
KR100499160B1 (en) 2003-01-15 2005-07-01 삼성전자주식회사 Method for wafer inspection and apparatus for the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019115391A1 (en) * 2017-12-11 2019-06-20 Asml Netherlands B.V. Voltage contrast metrology mark
CN111448519A (en) * 2017-12-11 2020-07-24 Asml荷兰有限公司 Voltage contrast measurement mark

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