KR20090000327A - Method of manufacturing a contact hole in semiconductor device - Google Patents

Method of manufacturing a contact hole in semiconductor device Download PDF

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Publication number
KR20090000327A
KR20090000327A KR1020070064311A KR20070064311A KR20090000327A KR 20090000327 A KR20090000327 A KR 20090000327A KR 1020070064311 A KR1020070064311 A KR 1020070064311A KR 20070064311 A KR20070064311 A KR 20070064311A KR 20090000327 A KR20090000327 A KR 20090000327A
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KR
South Korea
Prior art keywords
forming
interlayer insulating
contact hole
spacer
insulating layer
Prior art date
Application number
KR1020070064311A
Other languages
Korean (ko)
Inventor
김완수
Original Assignee
주식회사 하이닉스반도체
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Publication date
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Priority to KR1020070064311A priority Critical patent/KR20090000327A/en
Publication of KR20090000327A publication Critical patent/KR20090000327A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method of forming a contact hole in a semiconductor device, and in particular, providing a semiconductor substrate having an interlayer insulating film including a contact hole, forming an insulating film for a spacer on a surface of the interlayer insulating film including the contact hole, Forming an spacer layer on the sidewalls and the sidewalls of the interlayer insulating layer to form an etch stop layer to surround the spacer insulating layer on the interlayer insulating layer, thereby forming a spacer on the interlayer insulating layer, thereby forming a bridge margin between contact holes. It can be secured.

Description

Method of manufacturing a contact hole in a semiconductor device

1A through 1H are cross-sectional views sequentially illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 junction region

104: SAC nitride film 106: interlayer insulating film

108: hard mask 110: contact hole

112: insulating film for spacer 112a: spacer

114: etching prevention film 116: conductive film

116a: contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of improving bridge margins between contact holes.

A semiconductor device having a multi-layered metal wiring forms contact plugs by filling contact holes for electrical conduction between upper and lower devices. In order to form contact holes in a semiconductor device, accurate and strict mask alignment in a manufacturing process is required. Required.

A contact plug forming process of a general semiconductor device will be briefly described. First, an interlayer insulating film is deposited on a semiconductor substrate on which a predetermined structure such as a gate is formed, and then a contact region for exposing the junction region is formed by etching the interlayer insulating layer over the junction region formed on the semiconductor substrate. A polysilicon film is deposited on the interlayer insulating film including the contact hole and then planarized to form a contact plug filling the contact hole.

Recently, as the device is highly integrated, not only the CD (Critical Dimension) of the contact hole but also the width of the interlayer insulating layer for isolation between the contact holes is reduced, so that adjacent contact holes are connected to each other to generate a bridge. However, when the width of the interlayer insulating film between contact holes is small as described above, it is difficult to secure a bridge margin.

In order to solve the above problems, a method of securing spacer margins between contact holes by forming spacers on the sidewalls of the interlayer insulating film has emerged. However, in the etching process for forming the spacer, the insulating film for spacers at the contact hole inlet is etched. During the subsequent cleaning process, the interlayer insulating film is additionally etched and lost in the portion where the spacer insulating film is removed during the subsequent cleaning process, thereby reducing the bridge margin between contact holes. do.

According to an embodiment of the present invention, a semiconductor device capable of improving a bridge margin between contact holes by forming a spacer on an interlayer insulating layer by performing an etching process after forming an etch stop layer to surround the spacer insulating layer on the interlayer insulating layer. The present invention provides a method for forming a contact hole.

According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method including: providing a semiconductor substrate having an interlayer insulating film including a contact hole, forming an insulating film for a spacer on a surface of the interlayer insulating film including a contact hole, and interlayer Forming an etch stop layer to surround the spacer insulating layer on the insulating layer; and forming a spacer on the sidewalls and the upper side of the interlayer insulating layer.

In the above, the spacer insulating film is formed in a liner shape using a material having an etching selectivity different from that of the interlayer insulating film. The insulating film for spacers is formed to a thickness of 20 to 50 kPa using a nitride film.

The forming of the etch stop layer includes forming an etch stop layer having an overhang shape while surrounding the insulating layer for spacers on the interlayer insulating layer, and removing the overhang shape. The etch stop layer is formed using an insulating film having poor embedding characteristics. As an insulating film having poor buried characteristics, an USG (Undoped Silicate Glass) film is used. The etch stop layer is formed to a thickness of 300 to 800 kPa. The overhang shape is removed by an etching process using a 100: 1 ratio of BOE (Buffered Oxide Etchant) solution.

The SAC nitride film is further formed on the semiconductor substrate before the interlayer insulating film is formed. In forming the contact hole, the semiconductor substrate is etched to a thickness of less than 50 kHz from the surface downward while removing the SAC nitride film.

When forming the spacer, part or all of the etch stop layer is removed. After the spacer is formed, a step of performing a cleaning process and a step of forming a contact plug in the contact hole are further performed. The remaining etch stop layer is removed during the cleaning process. Before forming the contact hole, the step of forming a hard mask on the interlayer insulating film is further performed.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, and those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

1A through 1H are cross-sectional views sequentially illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a self-aligned contact (SAC) nitride film 102 may be formed on a semiconductor substrate 100 on which a semiconductor device (not shown) such as a transistor or a flash memory cell and a junction region 102 are formed. A first interlayer insulating film (not shown) is formed. The SAC nitride film is formed to prevent the gate and the semiconductor substrate 100 from being etched during subsequent contact hole formation. The first interlayer insulating film is formed of a material having an etching selectivity different from that of the SAC nitride film 102, and may be applicable to any oxide-based material. Preferably, the first interlayer insulating film may be formed of an HDP (High Density Plasma) oxide film, and formed to a thickness of 5000 kPa to 10000 kPa. Thereafter, a predetermined region of the first interlayer insulating layer is etched by an etching process using a mask (not shown) to form a source contact hole (not shown) that exposes a portion of the source region (not shown) formed in the semiconductor substrate 100. Then, after the cleaning process, polysilicon or a metal film is deposited to fill the source contact hole, and then planarized to form a source contact plug (not shown) in contact with the source region.

Next, a second interlayer insulating film (not shown) is formed on the entire structure including the source contact plug. The second interlayer insulating film can be applied as long as it is an oxide-based material. For example, HDP (High Density Plasma) oxide, Spin On Glass (SOG), Boron-Phosphorus Silicate Glass (BPSG), and Plasma Enhanced Tetra Ortho (PE-TEOS). It may be formed of any one selected from Silicate Glass (USG), Undoped Silicate Glass (USG), Phosphorus Silicate Glass (PSG), and Inter Poly Oxide (IPO). Preferably, the interlayer insulating film may be formed of an HDP oxide film or a PE-TEOS film and formed to a thickness of 1000 to 4000 kPa. In this case, the interlayer insulating film 106 of the present invention consists of a laminated film of the first and second interlayer insulating films.

Meanwhile, a hard mask 108 may be further formed on the interlayer insulating layer 106 to prevent the interlayer insulating layer 106 from being etched during subsequent contact hole formation, and may be formed of an amorphous carbon layer. have. At this time, the hard mask 108 is formed to a thickness of 2000 ~ 3000Å.

In the above description, the process of forming the source contact plug is a process applied to a flash memory device, and can be omitted in the manufacturing process of DRAM or other general semiconductor devices. That is, the subsequent process may be performed while only the first interlayer insulating layer is formed on the semiconductor substrate 100.

Referring to FIG. 1B, the hard mask 108, the interlayer insulating layer 106, and the SAC nitride layer 104 in the region corresponding to the junction region 102 are etched by an etching process using a mask (not shown). A photoresist pattern may be used as the mask, and in this case, the photoresist may be formed on the hard mask 108 by patterning the photoresist after exposure and development. As a result, a contact hole 110 is formed in the interlayer insulating layer 106 to expose the junction region 102. The junction region 102 becomes a drain region in the case of a flash memory device. At this time, when forming the contact hole 110, the semiconductor substrate 100 is controlled to be etched to a thickness lower than 50 μs from the surface to the bottom while removing the SAC nitride film 104.

Meanwhile, when forming the contact hole 110, the mask and the hard mask 108 may also be etched and removed, and if remaining, the mask may be removed through an etching process.

Referring to FIG. 1C, a liner-type spacer insulating layer 112 is formed along the surface of the interlayer insulating layer 106 including the contact hole 110. The spacer insulating layer 112 may be formed of a material having an etching selectivity different from that of the interlayer insulating layer 106, and may be preferably formed of a nitride layer, for example, a silicon nitride layer (SixNy). At this time, the spacer nitride film 112 is formed to a thickness of 20 to 50 kPa.

Referring to FIG. 1D, an etch stop layer 114 is formed to have an overhang shape while surrounding the spacer insulating layer 112 over the interlayer insulating layer 106 patterned by the contact hole 110. The etch stop layer 114 is formed to prevent the spacer insulating layer 112 formed on the interlayer insulating layer 106 from being etched during the etching process for forming the spacer, and is formed of an insulating layer having poor embedding characteristics. Preferably, the etch stop layer 114 is formed of a USG (Undoped Silicate Glass) film.

As such, when the etch stop layer 114 is formed of a USG film having poor buried characteristics, the upper portion of the contact hole 110 is faster than the bottom of the semiconductor substrate 100, so that the overhang may occur as the deposition of the USG film proceeds. Occurs and the inlet between the contact holes 110 is blocked.

Referring to FIG. 1E, an etching process for removing an overhang shape is performed. The etching process may be performed by a dry etch or wet etch process, and may be performed by using a BOE (Buffered Oxide Etchant) solution in a ratio of 100: 1 in the wet etching process. As a result, while the overhang shape is removed, the height of the etch stop layer 114 is also lowered. In this way, the overhang shape is removed so that the etching process for subsequent spacer formation can be performed smoothly.

Referring to FIG. 1F, a spacer etching process is performed. The spacer etching process may be performed by a dry etching process, preferably an etchback process. During the spacer etching process, the horizontal portion of the spacer insulating layer 112 is removed, and only the vertical portion formed thicker than the horizontal portion remains to form the spacer 112a on the sidewall of the interlayer insulating layer 106. At this time, the spacer insulating layer 112 on the bottom surface of the contact hole 110 is etched, thereby exposing the junction region 102.

Meanwhile, during the spacer etching process, the etch stop layer 114 may also be etched and removed, and the spacer insulating layer 112 formed on the interlayer insulating layer 106 covered by the etch stop layer 114 may be protected and not removed. 112a). Therefore, the spacer 112a is formed not only on the sidewalls of the interlayer insulating film 106 but also on the top.

When the etch stop layer 114 remains after the spacer etch process, the etch stop layer 114 may be removed through a subsequent cleaning process.

As described above, when the etch stop layer 114 is formed to surround the spacer insulating layer 112 on the interlayer insulating layer 106, the spacer insulating layer 112 formed on the interlayer insulating layer 106 during the spacer etching process is etched. It is possible to secure the bridge margin between the contact holes by preventing it.

In addition, the cleaning process may be further performed before depositing a conductive material for forming the contact plug in the contact hole 110. At this time, the washing step can be carried out using a BOE solution. However, when the etch stop film 114 is formed to surround the spacer 112a on the interlayer insulating film 106, the interlayer insulating film 106 may be prevented from being lost by the etchant during the cleaning process. The bridge margin between holes can be further secured.

Referring to FIG. 1G, a conductive material is deposited on the semiconductor substrate 100 including the contact hole 110 to fill the contact hole 110 to form a conductive film 116. The conductive film 116 may be formed of a polysilicon film, a metal film, or a laminated film thereof, and preferably, a polysilicon film.

Referring to FIG. 1H, the conductive layer 116 is etched until the surface of the spacer 112a is exposed. Here, the etching process may be performed by a planarization etching process, for example, chemical mechanical polishing (CMP) process. As a result, the conductive film 116 remains only in the contact hole 110 to form the contact plug 116a.

As such, since the bridge margin between contact holes is improved, the bridge between adjacent contact plugs 116a may be improved when the contact plugs 116a are formed, thereby improving process yield and device reliability.

The method for forming a contact hole according to an embodiment of the present invention is applicable when forming a drain contact hole such as a DRAM or a flash memory device.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

According to the present invention, by forming an etch stop layer to surround the spacer insulating layer on the interlayer insulating layer and then performing a spacer etching process, a spacer may be formed on the interlayer insulating layer to improve bridge margins between contact holes.

According to the present invention, by forming a spacer on the interlayer insulating layer, the interlayer insulating layer is prevented from being lost by the etchant during the subsequent cleaning process before forming the contact plug, thereby further securing the inter-contact hole margin.

In addition, by improving the bridge margin between contact holes, the present invention can prevent the bridge between adjacent contact plugs in subsequent contact plug formation, thereby improving process yield and device reliability.

Claims (15)

Providing a semiconductor substrate having an interlayer insulating film including a contact hole; Forming an insulating film for a spacer on a surface of the interlayer insulating film including the contact hole; Forming an etch stop layer to surround the spacer insulating layer on the interlayer insulating layer; And Forming a spacer on sidewalls and an upper portion of the interlayer insulating layer; The method of claim 1, The insulating layer for spacers is formed in a liner shape using a material having an etching selectivity different from the interlayer insulating film. The method of claim 1, And the insulating film for spacers is formed of a nitride film. The method of claim 1, The insulating layer for spacers is a contact hole forming method of a semiconductor device formed to a thickness of 20 to 50Å. The method of claim 1, wherein the forming of the etch stop layer comprises Forming an etch stop layer having an overhang shape while surrounding the spacer insulating layer over the interlayer insulating layer; And And removing the overhang shape. The method according to claim 1 or 5, The method of forming a contact hole in the semiconductor device is formed by using an insulating film having a poor buried property. The method of claim 6, The method of claim 1, wherein the insulating layer having poor buried characteristics is a USG (Undoped Silicate Glass) film. The method of claim 1, The etch stop layer is a contact hole forming method of a semiconductor device formed to a thickness of 300 to 800Å. The method of claim 1, The overhang shape is a contact hole forming method of a semiconductor device is removed by an etching process using a buffered oxide solution (BOE) of 100: 1 ratio. The method of claim 1, And forming a SAC nitride film on the semiconductor substrate before forming the interlayer insulating film. The method of claim 10, The method of claim 1, wherein the semiconductor substrate is etched to a thickness lower than 50 μs from the surface thereof while removing the SAC nitride layer. The method of claim 1, wherein when forming the spacer, The method of claim 1, wherein a part or all of the etch stop layer is removed. The method of claim 1, wherein after the spacer is formed, Performing a cleaning process; And And forming a contact plug in the contact hole. The method of claim 13, The method of claim 1, wherein the etch stop layer remaining in the cleaning process is removed. The method of claim 1, wherein before forming the contact hole, And forming a hard mask on the interlayer insulating film.
KR1020070064311A 2007-06-28 2007-06-28 Method of manufacturing a contact hole in semiconductor device KR20090000327A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379001B2 (en) 2013-03-05 2016-06-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379001B2 (en) 2013-03-05 2016-06-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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