KR20080114370A - Core voltage rising prevention circuit of semiconductor memory apparatus - Google Patents

Core voltage rising prevention circuit of semiconductor memory apparatus Download PDF

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Publication number
KR20080114370A
KR20080114370A KR1020070063856A KR20070063856A KR20080114370A KR 20080114370 A KR20080114370 A KR 20080114370A KR 1020070063856 A KR1020070063856 A KR 1020070063856A KR 20070063856 A KR20070063856 A KR 20070063856A KR 20080114370 A KR20080114370 A KR 20080114370A
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South Korea
Prior art keywords
voltage
signal
core voltage
release
control signal
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KR1020070063856A
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Korean (ko)
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최영경
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주식회사 하이닉스반도체
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Priority to KR1020070063856A priority Critical patent/KR20080114370A/en
Publication of KR20080114370A publication Critical patent/KR20080114370A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

A circuit for preventing core voltage rising of a semiconductor memory device is provided to stabilize a core voltage by enough securing a time to perform a release operation. A circuit for preventing core voltage rising of a semiconductor memory device comprises a release control signal generator(300), an enable signal generator, and a core voltage controller(200). The release control signal generator generates a release control signal after receiving a test signal. The enable signal generator generates a release enable signal in response to the release control signal after receiving a sense amp enable signal(100). The core voltage controller controls a core voltage by comparing a reference core voltage with the core voltage after receiving the release enable signal.

Description

Core Voltage Rising Prevention Circuit of Semiconductor Memory Apparatus

1 is a circuit diagram of a driving circuit for generating a bit line amplification voltage rto according to the prior art;

2 is a timing diagram of a core voltage rising prevention circuit according to the related art;

3 is a timing diagram of a core voltage increase preventing circuit according to an exemplary embodiment of the present invention;

4 is a circuit diagram of an enable signal generation unit shown in FIG. 3;

5 is a circuit diagram of a release control signal generation unit shown in FIG. 3;

6 is a circuit diagram of the core voltage controller shown in FIG. 3;

7 is a timing diagram of a core voltage increase preventing circuit according to an exemplary embodiment of the present invention;

8 is a block diagram of a core voltage rising preventing circuit according to another exemplary embodiment of the present disclosure;

9 is a circuit diagram of the reference core voltage control unit shown in FIG. 8, and

FIG. 10 is a circuit diagram of the reference voltage control signal generator shown in FIG. 8.

<Description of the symbols for the main parts of the drawings>

100: enable signal generator 200/500: core voltage controller

300: release control signal generator 600: reference voltage control signal generator

The present invention relates to a semiconductor memory device, and more particularly, to a core voltage increase prevention circuit.

Among the internal voltages used in the DRAM (Dynamic Random Access Memory) in the semiconductor memory device, the core voltage Vcore is a voltage used to amplify cell data in the DRAM. Having a more stable potential is a very important issue because DRAM performance is determined by changes in core voltage (Vocre) during DRAM operation.

When the data is read according to the low voltage of the DRAM, the speed at the 'high' level of the pair of bit lines to which the data of the cell is transmitted is slowed down, and the bit line is initially cored to compensate for this. It operates with the power supply voltage VDD instead of the voltage Vcore, and after that, it operates with a core voltage. This approach is called overdriving.

1 is a circuit diagram illustrating a driving circuit of a bit line amplification voltage rto according to the related art.

Referring to FIG. 1, the driving circuit of the bit line amplification voltage rto includes first and second NMOS transistors N1 and N2. The first NMOS transistor N1 includes a gate configured to receive the first sense amplifier enable signal sap0, a source connected to a power supply voltage VDD terminal, and a drain connected to a bit line amplification voltage rto terminal. The second NMOS transistor N2 includes a gate for receiving the second sense amplifier enable signal sap1, a source for receiving a core voltage Vcore, and a drain connected to the bit line amplifying voltage rto. . Here, the bit line amplification voltage rto is a voltage for amplifying the bit line to a 'high' level.

Specifically, when reading data from a cell, the first sense amplifier enable signal sap0 is first enabled at a 'high' level, and is disabled at a 'low' level after a predetermined time, and the second sense Enable the amplifier enable signal sap1 to the 'high' level. Here, the bit line is driven to the power supply voltage VDD while the first sense amplifier enable signal sap0 is at the 'high' level, and while the second sense amplifier enable signal sap1 is at the 'high' level. It is driven by the core voltage (Vcore).

However, when the power supply voltage VDD is higher than the core voltage Vcore, the driving circuit of the bit line amplification voltage rto causes the first sense amplifier enable signal sap0 to enter a 'high' level during overdriving. When enabled, the power supply voltage VDD is used as the bit line amplification voltage rto. At this time, the bit line amplification voltage rto is increased above the core voltage Vcore. After the first sense amplifier enable signal sap0 is disabled to the 'low' level and the second sense amplifier enable signal sap1 is enabled to the 'high' level, the bit line amplification voltage rto Drive circuit uses the core voltage Vcore as the bit line amplification voltage rto. At this time, since the bit line amplification voltage rto is higher than the core voltage Vcore, a current is applied to the bit line amplification voltage rto in the core voltage Vcore direction, thereby causing a problem in that the core voltage Vcore is increased. . In order to prevent the increase of the core voltage Vcore, when the level of the core voltage Vcore increases, the potential level of the core voltage Vcore is discharged by discharging a current from the core voltage Vcore to the ground voltage Vss. A core voltage rising prevention circuit that lowers the voltage is used.

In the conventional core voltage rising prevention circuit, when the first sense amplifier enable signal sap0 is enabled at the 'high' level, the overdriving operation is started, and the overdriving operation is completed at the timing at which the first sense amplifier enable signal sap0 is enabled. To generate a release enable signal Rls_EN having a constant pulse width. If the core voltage rising prevention circuit is enabled when the release enable signal Rls_EN is at the 'high' level, the core voltage Vcore is released in response to the output signal by comparing a core voltage value with a reference core voltage. Let's do it.

2 is a timing diagram of a core voltage rising prevention circuit of a semiconductor memory device according to the related art.

Referring to FIG. 2, for example, when the first sense amplifier enable signal sap0 is enabled at a 'high' level, overdriving is started, and the first sense amplifier enable signal sap0 is' The release enable signal Rls_EN is enabled at the 'high' level at the timing of disabling from the 'high' level to the 'low' level. The release enable signal Rls_EN is maintained at a 'high' level by a predetermined width and then disabled to a 'low' level.

The core voltage increase prevention circuit of a semiconductor memory device according to the related art is a core voltage Vcore at a bit line amplification voltage rto through overdriving during word line WL active when the core voltage is externally applied. Current continues to flow into the core, the core voltage Vcore is still increased and current consumption is increased. Here, when the core voltage Vcore lower than the target core voltage Vcore is externally applied, for example, the target core voltage Vcore of the DRAM is 1.5V, and the core voltage Vcore of 1.4V is externally applied. When applied, the core voltage is higher than 1.4V due to the current flowing from the power supply voltage VDD stage due to overdriving. In this case, the core voltage rising prevention circuit discharges a current from the core voltage to the ground voltage VSS terminal, thereby lowering the core voltage Vcore, but the timing of the release enable signal Rls_EN lacks a timing margin, thereby causing a core voltage Vcore. Since only V can be released to 1.5V, the core voltage (Vcore) is disabled to the 'low' level before dropping to 1.4V.

The core voltage increase prevention circuit of the semiconductor memory device according to the present invention has an object of ensuring a stable core voltage by ensuring a sufficient time to perform the release operation.

The core voltage increase preventing circuit of the semiconductor memory device according to the present invention has another object to ensure a stable core voltage by varying the reference core voltage according to the level of the core voltage.

The core voltage increase prevention circuit of the semiconductor memory device according to an exemplary embodiment of the present invention receives a release control signal generation unit for receiving a test signal and generating a release control signal, a sense amplifier enable signal, and responds to the release control signal. And an enable signal generator configured to generate a release enable signal, and a core voltage controller configured to receive the release enable signal, compare a reference core voltage and a core voltage, and control the core voltage according to the result.

In addition, the core voltage increase prevention circuit of the semiconductor memory device according to another exemplary embodiment of the present invention may include a reference voltage control signal generator configured to receive a test signal and generate a reference voltage control signal, and receive a reference core voltage. A variable reference voltage generator for generating a variable reference voltage having a variable potential level and a release enable signal, comparing the variable reference voltage with a core voltage, and controlling the core voltage according to the result. It includes a control unit.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a block diagram of a core voltage rising prevention circuit of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the core voltage rising prevention circuit includes an enable signal generator 100, a core voltage controller 200, and a release control signal generator 300. The core voltage rising prevention circuit is configured to receive a first sense amplifier enable signal sap0 and to generate a release enable signal Rls_EN in response to the release control signal Rls_CTRL, and the The core voltage controller 200 which receives a release enable signal Rls_EN, compares the reference core voltage Vrefc with the core voltage Vcore, and determines whether the core voltage Vcore is increased to release the core voltage controller 200, and a test signal. And a release control signal generator 300 for generating a release control signal Rls_CTRL in response to TM.

Conventional core voltage increase prevention circuit is composed of the enable generator 100 and the core voltage controller 200 to release the core voltage (Vcore), the margin of the release enable signal (Rls_EN) is lacking desired Although it was not possible to release the core voltage Vcore to a target level, in the present invention, the release control signal generation unit 300 is further provided to thereby release the release control signal generated by the test signal TM or fuse cutting. Rls_CTRL may continuously enable the release enable signal Rls_EN to secure a timing margin for releasing to a desired target core voltage Vcore.

4 is a circuit diagram of an enable signal generator 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the enable generator 100 includes a pulse generator 110 and a signal combiner 120.

Conventionally, the timing margin of the release enable signal Rls_EN was not enough to release the core voltage Vcore to the target level. However, in the present invention, the release control signal Rls_CRTL continuously releases the release enable signal Rls_EN. By enabling it, you can secure a margin to release the core voltage (Vcore) to the target level.

The pulse generator 110 receives the sense amplifier enable signal sap0 and generates the sense amplifier enable pulse signal sap0_DETP.

The signal combiner 120 includes a first NOR gate NR1 and a first inverter IV1. The first NOR gate NR1 receives the pulse sense amplifier enable pulse signal sap0_DETP and the release control signal Rls_CTRL, and the first inverter IV1 outputs the output of the first NOR gate NR1. It receives the input and outputs the release enable signal Rls_EN.

FIG. 5 is a circuit diagram of the release control signal generator shown in FIG. 3.

Referring to FIG. 5, the release control signal generator 300 generates a release control signal Rls_CRTL for securing a timing margin of the release enable signal Rls_EN in response to the test signal TM.

The release control signal generator 300 includes a first PMOS transistor P1 and a first fuse F1. The first PMOS transistor P1 includes a gate receiving the test signal TM, a source connected to an output node of the release control signal Rls_CTRL, and a drain connected to the first fuse F1. The first fuse F1 is connected between a ground voltage VSS terminal and the first PMOS transistor P1.

In the test mode, when the test signal TM is at the 'high' level, the release control signal generator 300 turns on the first PMOS transistor P1 to lower the potential level at the output node of the release control signal Rls_CTRL. The release control signal Rls_CTRL at the low level is output. When the test signal is at the 'low' level, the first PMOS transistor P1 is turned off, and the potential level of the output node of the release control signal Rls_CTRL is increased to release the release control signal Rls_CTRL having a 'high' level. Outputs

In the normal operation, the test signal TM is connected to the ground voltage VSS terminal and has a default value of 'low' level. The first PMOS transistor P1 is turned on to output the release control signal Rls_CTRL having a 'low' level. In order to enable the release control signal Rls_CTRL to a 'high' level, the first fuse F1 is cut to prevent the power supply voltage VDD from being discharged to the ground voltage VSS terminal. Therefore, when the first fuse F1 is cut, the release control signal Rls_CTRL having a 'high' level may be generated.

6 is a circuit diagram of the core voltage controller 200 according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the core voltage controller 200 includes a differential amplifier 210, a voltage divider 220, and a driver 230. The differential amplifier 210 includes second and third PMOS transistors P2 and P3 having a current mirror structure, third and fourth NMOS transistors N3 and N4 having a differential input structure, and the differential amplifying unit ( And a fifth NMOS transistor N5 that enables 210. The second PMOS transistor P2 includes a gate connected to the gate of the third PMOS transistor P3, a source connected to the power supply voltage VDD, and a drain connected to the first node S1. The third PMOS transistor P3 includes a gate and a drain that are commonly connected to each other, and a source connected to a power supply voltage VDD. The third NMOS transistor N3 may include a gate configured to receive a reference core voltage Vrefc, that is, a target core voltage Vcore, a drain connected to the first node S1, and a source connected to the second node S2. Include. The fourth NMOS transistor N4 includes a gate configured to receive a core distribution voltage Vcore / 2, a drain connected to the drain of the third PMOS transistor P3, and a source connected to the second node S2. . The fifth NMOS transistor N5 includes a gate receiving the release enable signal Rls_EN, a drain connected to the second node S2, and a source connected to the ground voltage VSS terminal. The output signal of the first node S1 is applied to the driver 230 as a driver signal Rls_DRV for driving the driver 230.

After the overdriving operation is completed, the differential amplifier 210 performs a differential amplification operation when the release enable signal Rls_EN is enabled. The potential level of the driver signal Rls_DRV is determined by comparing the core distribution voltage Vcore / 2 with the reference core voltage Vrefc. For example, when the core distribution voltage Vcore / 2 is lower than the reference core voltage Vrefc, the potential level of the driver signal Rls_DRV is lowered and the core distribution voltage Vcore / 2 is the reference. When the voltage is higher than the core voltage Vrefc, the potential level of the driver signal Rls_DRV increases.

The voltage divider 220 includes fourth and fifth PMOS transistors P4 and P5. The fourth PMOS transistor P4 includes a gate connected to the drain, a drain connected to the third node S3, and a source connected to the core voltage Vcore. The fifth PMOS transistor P5 includes a gate connected to the drain, a drain connected to the ground voltage VSS terminal, and a source connected to the third node S3. The output signal of the third node S3 is applied to the differential amplifier 210 as a core split voltage Vcore / 2 obtained by dividing the core voltage Vcore into two.

The voltage divider 220 divides the voltage by using two MOS transistors, which are voltage divider elements, as the core voltage Vcore, but another voltage divider capacitor or resistor may be used.

The driver unit 230 includes a gate receiving the driver signal Rls_DRV, a source connected to a core voltage Vcore terminal, and a drain connected to a ground voltage VSS terminal.

The driver 230 controls the release amount of the core voltage Vcore according to the degree of turn-on of the sixth PMOS transistor P6 that receives the driver signal Rls_DRV.

7 is a timing diagram of a core voltage rising prevention circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 7, when one of a plurality of banks is enabled in the first sense amplifier enable signal sap0 to a 'high' level and an overdriving operation is started, the sense amplifier enable pulse signal Enable (sap0_DETP) to the 'high' level. The release enable signal Rls_EN is enabled at the 'high' level at the timing when the sense amplifier enable pulse signal sap0_DETP is enabled at the 'high' level. Disabling the sense amplifier enable pulse signal sap0_DETP to a low level at a timing at which the first sense amplifier enable signal sap0 is disabled at a low level, and enabling the sense amplifier enable pulse signal. (sap0_DETP) disables the release enable signal Rls_EN to a 'low' level. Thereafter, when the release control signal Rls_CTRL is enabled at the 'high' level, the release enable signal Rls_EN becomes a 'high' level, and the release control signal Rls_CTRL maintains the 'high' level. Keep a state of 'high' level while continuing. The release enable signal Rls_EN is applied to an input terminal of the differential amplifier 210.

Therefore, during the test operation, the core voltage rising prevention circuit continuously enables the release enable signal Rls_EN to the 'high' level while the release control signal Rls_CTRL is at the 'high' level, thereby causing the core voltage Vcore. You can release to the desired value.

8 is a block diagram of a core voltage rising prevention circuit according to another exemplary embodiment of the present invention.

Referring to FIG. 8, the core voltage rising prevention circuit includes a variable reference voltage generator 400, a core voltage controller 500, and a reference voltage control signal generator 600.

The core voltage rising prevention circuit may be configured to determine a potential level of the reference core voltage Vrefc because a problem caused by insufficient timing margin of the release enable signal Rls_EN, that is, the core voltage Vcore does not reach the target level. The variable reference voltage Ref_a is generated by controlling with a control signal CTRL, the variable reference voltage Ref_a is compared with the divided core voltage Vcore, and the core voltage is adjusted by adjusting the release amount according to the potential level. Allow Vcore to reach the target level.

The variable reference voltage generator 400 may receive a reference core voltage Vrefc and control a potential of the core voltage Vcore in response to the first to third reference voltage control signals CTRL <0: 2>. A male variable reference voltage Ref_a is generated.

The core voltage controller 500 differs only in the signal input to the core voltage controller 200 and the differential amplifier 210. The core controller 500 controls the core voltage Vcore by receiving the variable reference voltage Ref_a and comparing it with the bisected core voltage Vcore.

The reference voltage control signal generator 600 receives the first to third test signals TM and generates the first to third reference voltage control signals CTRL <0: 2>. Here, the reference voltage control signal generator 600 receives a plurality of test signals TM and generates a plurality of reference voltage control signals CTRL, but in the present invention, three test signals TM <0: 2> are generated. It is used to generate the three reference voltage control signals (CTRL <0: 2>).

FIG. 9 is a circuit diagram of the variable reference voltage generator shown in FIG. 8.

Referring to FIG. 9, the variable reference voltage generator 400 includes a comparator 410, a driver 420, a divider 430, and a reference voltage generator 440. The comparison unit 410 has a differential amplifying structure, and includes sixth and seventh PMOS transistors P6 and P7 having a current mirror structure, seventh and eighth NMOS transistors N7 and N8 having a differential input structure, and the comparison. A ninth NMOS transistor N9 for enabling the unit 410 is included. The sixth PMOS transistor P6 includes a source connected to the power supply voltage VDD terminal, a drain connected to the fourth node S4, and a gate. The seventh PMOS transistor P7 includes a gate connected to the gate of the sixth PMOS transistor P6, a drain commonly connected to the gate, and a source connected to the power supply voltage VDD. The seventh NMOS transistor N7 includes a gate configured to receive a reference core voltage Vrefc, a drain connected to the fourth node S4, and a source connected to the fifth node S5. The eighth NMOS transistor N8 includes a gate configured to receive a distribution voltage VDD / 2, a drain connected to the drain of the seventh PMOS transistor P7, and a source connected to the fifth node S5. The ninth NMOS transistor N9 includes a gate configured to receive a reference core voltage Vrefc, a drain connected to the fifth node S5, and a source connected to the ground voltage VSS terminal.

The comparison unit 410 compares the reference core voltage Vrefc and the distribution voltage VB to generate a comparison signal VA having a potential level flowing in the fourth node S4.

The driver 420 includes an eighth PMOS transistor P8. The seventh NMOS transistor N7 includes a gate configured to receive the comparison signal VA, a source connected to a power supply voltage VDD, and a drain connected to a sixth node S6.

The driver 420 receives the comparison signal VA and outputs a reference division voltage Vrefc_D to the sixth node S6.

The distribution unit 430 includes ninth and tenth PMOS transistors P9 and P10. The ninth PMOS transistor P9 includes a drain and a gate commonly connected to each other, and a source connected to the sixth node S6. The tenth PMOS transistor P10 includes a gate connected to a drain, a drain connected to the ground voltage VSS terminal, and a source connected to the drain of the ninth PMOS transistor P9. The distribution voltage VDD / 2 is output from a node to which the drain of the ninth PMOS transistor P9 and the source of the tenth PMOS transistor P10 are connected.

The divider 430 bisects the reference divider voltage Vref_D and applies the divider voltage to the input terminal of the comparator 410.

The reference voltage generator 440 may include first to fourth resistors R1 to R4, second to fourth inverters IV2 to IV4 connected in series from the sixth node S6 to the ground voltage VSS terminal, And first to third passgates TP1 to TP3. The first passgate TP1 receives a first reference divider voltage Vcore_D1 generated at an input terminal of a connection node a of the first resistor R1 and the second resistor R2, and receives a first control terminal. The inverted first reference voltage control signal CTRL <0> is input, and the second control terminal receives the first reference voltage control signal CTRL <0> and outputs the variable reference voltage Ref_a. The second passgate TP2 receives a second reference divider voltage Vcore_D2 generated at an input terminal of the connection node b of the second resistor R2 and the third resistor R3, and receives a first control terminal. The inverted second reference voltage control signal CTRL <1> is input, and a second control terminal receives the second reference voltage control signal CTRL <1> and outputs the variable reference voltage Ref_a. . The third pass gate TP3 receives a third reference division voltage Vcore_D3 generated at an input terminal of the connection node C of the third resistor R3 and the fourth resistor R4, and receives a first control terminal. The inverted third reference voltage control signal CTRL <2> is input, and the second control terminal receives the third control signal CTRLB <2> and outputs the variable reference voltage Ref_a.

FIG. 10 illustrates the reference voltage control signal generator shown in FIG. 8.

Referring to FIG. 10, since the reference voltage control signal generator 600 includes a plurality of the reference voltage control signal generator 600 having the same configuration, for example, the reference voltage control signal CTRL <0>. I will only explain how to create).

The reference voltage control signal generator 600 includes an eleventh PMOS transistor P11 and a second fuse F2. In the test mode, the eleventh PMOS transistor P11 may include a gate that receives the first test signal TM <0>, a source connected to the power supply voltage VDD, and a drain connected to the second fuse F2. Include. The first reference voltage control signal CTRL <0> is output from a node connected to a source voltage VDD terminal and a source of the tenth PMOS transistor P10.

In the test mode, when the first test signal TM <0> is at the 'high' level, the eleventh PMOS transistor P11 is turned off so that the power supply voltage VDD becomes the first reference voltage control signal CTRL < 0>) to output the first reference voltage control signal CTRL <0> at the 'high' level. When the first test signal TM <0> is at the 'low' level, the eleventh PMOS transistor P11 is turned on so that the power supply voltage VDD is discharged to the ground voltage VSS so that the 'low' level The first reference voltage control signal CTRL <0> is output.

In the normal operation, the test signal TM <0> is connected to the ground voltage VSS having a default value of 'low' level. In the normal operation, the eleventh PMOS transistor P11 is turned on so that the first reference voltage control signal CTRL <0> has a low level, which is a default value. In order to switch the first reference voltage control signal CTRL <0> to the 'high' level, cutting the fuse F1 prevents the power voltage VDD from being discharged to the ground voltage VSS. 1 The reference voltage control signal CTRL <0> may be switched to the 'high' level.

The reference voltage generator 440 generates the variable reference voltage Ref_a applied to the differential amplifier 510 of the core voltage controller 500. Assuming that the first to fourth resistance values are the same, the potential level of the variable reference voltage Ref_a is determined according to whether the first to third passgates TP1 to TP3 are activated.

In the test mode, when the first test signal TM <0> is at the 'high' level and the second and third test signals TM <1: 2> are at the 'low' level, the first passgate TP1 may be used. Is activated to have a potential level of 3/4 of the reference division voltage Vrefc_D output from the sixth node S6, that is, a first reference division voltage Vcore_D1 having a potential level 1.5 times that of the reference core voltage Vrefc. ) Is output as the variable reference voltage Ref_a.

When the second test signal TM <1> is at the 'high' level and the first and third test signals TM <0> and TM <2> are at the 'low' level, the second passgate ( TP2 is activated to output the second reference divided voltage Vrefc_D1 having the potential level equal to the reference core voltage Vrefc as the variable reference voltage Ref_a.

When the third test signal TM <2> is at the 'high' level and the first and second test signals TM <0: 1> are at the 'low' level, the third passgate TP3 is When activated, the third core distribution voltage Vrefc_D3 having a potential level 0.5 times the reference core voltage Vrefc is output as the variable reference voltage Ref_a.

In the normal operation, when the second fuse F2 is cut, the first reference voltage control signal CTRL <0> becomes 'high' level to activate the first passgate TP1. The first reference division voltage Vrefc_D1 having a potential level of 3/4 of the reference division voltage Vrefc_D, that is, 1.5 times the potential level of the reference core voltage Vrefc, is output as the variable reference voltage Ref_a. .

When the third fuse F3 is cut during the normal operation, the control signal CTRL <1> becomes 'high' level, thereby activating the second passgate TP2, and thus the potential of the reference core voltage Vrefc. The second reference division voltage Vrefc_D2 equal to the level is output as the variable reference voltage Ref_a.

When the fourth fuse F4 is cut during the normal operation, the control signal CTRL <2> becomes 'high' level, thereby activating the third passgate TP3, so that 0.5 of the reference core voltage Vrefc is achieved. A third reference division voltage Vrefc_D3 having a double potential level is output as the variable reference voltage Ref_a.

The variable reference voltage Ref_a is applied to the core voltage controller 500. The variable reference voltage Ref_a generates the driver signal Rls_DRV having a predetermined potential level compared to the core distribution voltage Vcore / 2. The driver signal Rls_DRV is input to the driver 430 to release the core voltage Vcore.

Here, the reference voltage generator 440 according to the present invention uses a resistor as a voltage distribution element, but is included in the present invention as long as it is not only a resistor but also a voltage distribution member such as a MOS transistor and a capacitor.

The core voltage rising prevention circuit of the semiconductor memory device adjusts the potential level of the variable reference voltage Ref_a input to the differential amplifier provided in the core voltage controller 500, thereby failing to reach the target level. You can control the value of). When the core voltage Vcore is increased due to overdriving of the power supply voltage VDD, the potential level of the variable reference voltage Ref_a is decreased, and when the core voltage Vcore is lowered, the variable reference voltage Ref_a The core voltage Vcore can be stabilized by increasing the potential level of. In addition, when the applied core voltage Vcore is higher than the reference core voltage Vrefc after the core voltage Vcore is applied externally, the potential level of the variable reference voltage Ref_a is decreased to reduce the core voltage Vcore. It can stabilize.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The core voltage increase preventing circuit of the semiconductor memory device according to the present invention has an effect of stabilizing the core voltage by sufficiently securing the time for performing the release operation.

In addition, the core voltage increase prevention circuit of the semiconductor memory device according to the present invention has the effect of stabilizing the core voltage by varying the reference voltage according to the level of the core voltage to control the release amount of the core voltage.

Claims (10)

A release control signal generator for receiving a test signal and generating a release control signal; An enable signal generator which receives a sense amplifier enable signal and generates a release enable signal in response to the release control signal; And a core voltage controller configured to receive the release enable signal, compare a core voltage with a core voltage, and control the core voltage according to the result. The method of claim 1, The release control signal generator, And disabling the release control signal when the test signal is enabled, and disabling the release control signal when the test signal is disabled. The method of claim 1, The enable signal generator, A pulse generator configured to receive the sense amplifier enable signal and generate a sense amplifier enable pulse signal; And a signal combination unit configured to receive the sense amplifier enable pulse signal and generate the release enable signal in response to the release control signal. The method of claim 3, wherein The signal combination unit, And if the release control signal is enabled, enable the release enable signal. The method of claim 1, The core voltage control unit, A differential amplifier which receives the release enable signal and compares the reference core voltage with the core voltage to generate a driver signal; And a driver unit controlling a core voltage in response to the driver signal. A reference voltage control signal generator configured to receive a test signal and generate a reference voltage control signal; A variable reference voltage generator configured to receive a reference core voltage and generate a variable reference voltage whose potential level varies in response to the reference voltage control signal; And a core voltage controller configured to receive a release enable signal, compare the variable reference voltage with a core voltage, and control the core voltage according to the result. The method of claim 6, The reference voltage control signal generator, And generating the reference voltage control signal in response to the test signal and whether the fuse is cut. The method of claim 6, The variable reference voltage generator, A comparator configured to receive the reference core voltage and generate a comparison signal by comparing with the divided voltage; A driving unit receiving the comparison signal and outputting a reference distribution signal; A division unit for dividing the reference division voltage to generate the division voltage and applying the division voltage to the comparison unit; And a variable reference voltage generator configured to output the reference divided voltage as a variable reference voltage in response to the reference voltage control signal. The method of claim 8, The variable reference voltage generator, And a plurality of pass gates receiving signals output from the connection nodes of the plurality of resistance elements connected in series and outputting the variable delay signals in response to the reference voltage control signal. Prevention circuit. The method of claim 6, The core voltage control unit, A differential amplifier configured to receive the release enable signal and to generate a driver signal by comparing the variable reference voltage and the core voltage; And a driver unit controlling a core voltage in response to the driver signal.
KR1020070063856A 2007-06-27 2007-06-27 Core voltage rising prevention circuit of semiconductor memory apparatus KR20080114370A (en)

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