KR20080086693A

KR20080086693A - Method for measuring overlay of semiconductor device

Info

Publication number: KR20080086693A
Application number: KR1020070028695A
Authority: KR
Inventors: 박정수
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-03-23
Filing date: 2007-03-23
Publication date: 2008-09-26

Abstract

The present invention relates to a method for measuring overlay of a semiconductor device, and by measuring the overlay using AFM, the accuracy of overlay data is improved when applied to a device with high integration, and when applied to overlay correction, the reliability of the overlay correction Is improved, and a technique for improving the characteristics of the device by preventing misalignment with a layer formed in a subsequent process is disclosed.

Description

Overlay measurement method for semiconductor devices {METHOD FOR MEASURING OVERLAY OF SEMICONDUCTOR DEVICE}

1A and 1B are photographic views illustrating overlay vernier of semiconductor devices.

Figure 2 is a graph showing the overlay measurement results according to the prior art.

3A to 3C are cross-sectional views illustrating an overlay vernier manufacturing method and an overlay measuring method of a semiconductor device according to the present invention.

4 is a graph showing an overlay measurement result according to the present invention.

200, 400: Mother 210, 410: Son

300: semiconductor substrate 310: etched layer pattern

320: photosensitive film pattern 360: AFM top needle

The present invention relates to a method for measuring overlay of a semiconductor device, and by measuring the overlay using AFM, the accuracy of overlay data is improved when applied to a device with high integration, and when applied to overlay correction, The technique of improving the characteristics of the device by improving the fastness and preventing misalignment with the layer formed in a subsequent process is disclosed.

In general, the manufacturing process of a semiconductor device is to form a specific pattern on the wafer. In particular, in the lithography process using a pattern transfer mechanism such as a light source and a mask, the semiconductor device can be realized only when the alignment between the pattern formed in the previous process and the pattern formed in the subsequent process is precisely performed.

In the lithography process, overlay vernier is used to confirm the degree of alignment between the patterns of the before and after process.

The overlay vernier is formed around the chip of the wafer and formed in the scribe lane which is cut and discarded after the wafer process is completed.

Since the manufacturing process of the semiconductor device goes through a multi-step pattern forming process, a mask having a specific pattern is used for each step.

At this time, the overlay vernier is formed in the mask used in each step, the overlay vernier formed in the previous process becomes the mother of the reference key, the overlay vernier formed in the subsequent process becomes the son of the measurement key.

In this case, the degree of overlay between the patterns is determined by measuring the positional relationship between the mother and the son.

In the overlay measurement method of a semiconductor device according to the related art, the scribe lane region of the semiconductor substrate is etched to a predetermined depth to form a trench defining a mother of the overlay vernier.

Next, a photoresist film is formed over the entire trench including the trenches, and an exposure and development process using an exposure mask including a light shielding pattern is performed in the son region to form a photoresist pattern defining the son of the overlay vernier.

1A and 1B are photographs showing a plan view of an overlay vernier and show overlay verniers in the form of a box in box and a frame in frame.

2 is a planar photograph showing the overlay vernier and a graph showing the overlay measurement results according to the prior art.

Referring to FIG. 2, after forming the overlay vernier 200 and the son 210 of the overlay vernier on the semiconductor substrate, the overlay is measured.

At this time, the overlay measurement method uses a laser beam, it is possible to measure the overlay value through a signal (Signal) reflected from the mother and son of the overlay vernier.

In the overlay measurement method of a semiconductor device according to the prior art described above, the overlay measurement method using a laser beam is reduced in the accuracy of the overlay value according to the properties and thickness reflectivity of the semiconductor substrate, and the overlay correction is performed with the overlay data that is less accurate As a result, misalignment may occur in a subsequent process, thereby degrading device characteristics.

In order to solve the problem, by measuring the overlay using the AFM, the accuracy of the overlay data is improved when applied to the device with high integration, when applied to the overlay correction, the reliability of the overlay correction is improved, and subsequent processes It is an object of the present invention to provide an overlay measurement method of a semiconductor device capable of preventing misalignment with a layer formed of the same.

The overlay measurement method of a semiconductor device according to the present invention

Forming an etched layer pattern defining a mother layer on the semiconductor substrate;

Forming a photoresist pattern defining an insulator on the etched layer pattern, wherein the photoresist pattern is formed inside the mother region;

Measuring an overlay value using an atomic force microscope (AFM),

Measuring the overlay value using the AFM may include positioning a top needle of the AFM so as to be spaced apart from the semiconductor substrate provided with the mother and sons by a predetermined distance;

Applying a voltage to generate a potential difference between the semiconductor substrate and the AFM tower needle, and measuring an overlay value while moving the AFM tower needle along a predetermined path;

At least one AFM tower needle is provided,

The aperture of the AFM tower needle is 1 to 100Å,

The AFM tower needle moves in the X-axis and Y-axis directions,

The moving speed of the AFM tower needle is characterized in that 10 to 1000 ㎛ / s.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3A to 3C are cross-sectional views illustrating an overlay vernier forming method and an overlay measuring method of a semiconductor device according to the present invention.

Referring to FIG. 3A, an etched layer (not shown) is formed on the semiconductor substrate 300, and the etched layer (not shown) is etched to form an etched layer pattern 310 defining a mother.

Referring to FIG. 3B, a photosensitive film (not shown) is formed on the entire semiconductor substrate 300 provided with the etched layer pattern 310.

Subsequently, the photosensitive film (not shown) is patterned to form a photosensitive film pattern 320 defining a son by performing an exposure and development process using an exposure mask having a light shielding pattern defining a son.

Here, the photoresist pattern 320 is preferably formed inside the mother.

Referring to FIG. 3C, overlay values are measured using AFM.

In this case, in the overlay measuring method using the AFM, the AFM top needle 360 is positioned to be spaced apart from the semiconductor substrate 300 provided with the mother and son.

Next, a voltage is applied between the semiconductor substrate 300 and the AFM tower needle 360 to generate a potential difference.

Then, the AFM tower needle 360 is moved while moving in the X-axis or Y-axis direction, and the overlay value is measured.

At this time, the moving speed of the AFM tower needle 360 is preferably 10 to 1000 ㎛ / s.

In addition, the AFM tower needle 360 has a diameter of 1 to 100Å, it is preferable to have one or more as shown in (ii) of Figure 3c.

AFM (Atomic Force Microscope) according to the present invention can be used in the air, unlike the electron microscope that can be observed only in vacuum, and can measure up to one tenth of the atomic diameter, which plays an important role in the development of nanotechnology It is equipment.

The AFM uses a probe manufactured by nanotechnology, which includes a cantilever at the end of the substrate and a tower needle having a few atoms size at the end thereof.

When the AFM approaches the surface of the sample to be measured with the tip of the probe tip, the AFM pulls or pushes out an electrostatic force, Van Der Waals Force, Coulolombic Force, and the like. The force acts between the atom on the sample surface and the atom at the tip of the tower. This force causes the cantilever to deflect and keeps this force constant, precisely controlled to store the position of the scanner at each point to be measured. It has the principle of obtaining a three-dimensional image of the sample surface.

4 is a graph illustrating an overlay measurement result of a semiconductor device using AFM according to the present invention.

Referring to FIG. 4, the overlay vernier having the mother 400 and the son 410 is illustrated as a graph of an image obtained by performing a scanning process using an AFM, and the overlay value may be measured using the graph.

Here, the degree of overlay may be determined by measuring the distance between the maximum value and the minimum value of the graph.

In this case, when the overlay is measured, the electrical properties or physical properties of the overlay vernier formed on the semiconductor substrate may be measured together.

In the overlay measurement method of a semiconductor device according to the present invention, by measuring the overlay using AFM, the accuracy of the overlay data is improved when applied to a high integration device, and when applied to overlay correction, the reliability of the overlay correction is improved. In addition, there is an effect that the characteristics of the device is improved by preventing the misalignment with the layer formed in a subsequent process.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims

Forming a photoresist pattern defining an insulator on the etched layer pattern, wherein the photoresist pattern is formed inside the mother region; And

Measuring Overlay Values Using AFM (Atomic Force Microscope)

Overlay measuring method of a semiconductor device comprising a.

The method of claim 1,

Measuring the overlay value using the AFM

Positioning a top of the AFM so as to be spaced apart from the semiconductor substrate provided with the mother and sons by a predetermined distance; And

Applying a voltage to generate a potential difference between the semiconductor substrate and the AFM tower needle and measuring an overlay value while moving the AFM tower needle along a predetermined path;

Overlay measuring method of a semiconductor device characterized in that it further comprises.

The method of claim 2,

The AFM top needle is provided with at least one semiconductor device, characterized in that provided.

The method of claim 2,

The AFM top needle aperture has a diameter of 1 to 100 microseconds.

The method of claim 2,

The AFM tower needle is moved in the X-axis and Y-axis direction overlay measurement method of a semiconductor device.

The method of claim 2,

The moving speed of the AFM tower needle is 10 to 1000 ㎛ / s, the overlay measurement method of a semiconductor device.