KR20080058863A - Metal plug of semiconductor device and method of manufacturing the same - Google Patents
Metal plug of semiconductor device and method of manufacturing the same Download PDFInfo
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- KR20080058863A KR20080058863A KR1020060133037A KR20060133037A KR20080058863A KR 20080058863 A KR20080058863 A KR 20080058863A KR 1020060133037 A KR1020060133037 A KR 1020060133037A KR 20060133037 A KR20060133037 A KR 20060133037A KR 20080058863 A KR20080058863 A KR 20080058863A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 31
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 16
- 239000010937 tungsten Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 27
- 229910052707 ruthenium Inorganic materials 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 10
- 239000002243 precursor Substances 0.000 claims description 3
- 239000000376 reactant Substances 0.000 claims description 3
- CCEKAJIANROZEO-UHFFFAOYSA-N sulfluramid Chemical group CCNS(=O)(=O)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)F CCEKAJIANROZEO-UHFFFAOYSA-N 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 15
- 239000007789 gas Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
도 1은 본 발명의 실시예에 따른 반도체 소자의 금속 플러그를 도시한 단면도.1 is a cross-sectional view showing a metal plug of a semiconductor device according to an embodiment of the present invention.
도 2a 및 도 2d는 본 발명의 실시예에 따른 반도체 소자의 금속 플러그 제조방법을 설명하기 위한 공정별 단면도.2A and 2D are cross-sectional views of processes for explaining a method of manufacturing a metal plug in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200 : 반도체기판 102, 202 : 절연막100, 200:
104, 204 : 콘택홀 106, 206 : 베리어막104, 204:
108, 208 : 금속막108,208: metal film
본 발명은 반도체 소자의 금속 플러그 및 그 제조방법에 관한 것으로, 보다 자세하게는, 금속 배선용 플러그 형성시 볼케이노(volcano) 현상 방지 및 전기적 특성을 개선할 수 있는 반도체 소자의 금속 플러그 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal plug of a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a metal plug of a semiconductor device and a method of manufacturing the same, which can prevent volcano phenomena and improve electrical characteristics when forming a metal wiring plug. will be.
반도체 소자의 전기적 연결 통로를 제공하는 콘택홀의 매립 플러그 물질을 비롯한 금속배선의 재료로서는 전기 전도도가 매우 우수한 알루미늄(Al)이 주로 이용되어 왔다. 그런데, 반도체 소자의 집적도 향상에 기인해서 콘택홀의 너비는 감소하고, 반면, 깊이는 깊어짐에 따라, 알루미늄으로는 미세 크기의 콘택홀을 완전 매립시키는 것이 어렵게 되었다. Aluminum (Al) having excellent electrical conductivity has been mainly used as a material for metal wiring, including a buried plug material of a contact hole providing an electrical connection passage of a semiconductor device. However, due to the increase in the degree of integration of the semiconductor device, the width of the contact hole decreases, whereas as the depth deepens, it is difficult to completely fill the contact hole having a fine size with aluminum.
따라서, 이러한 콘택홀 매립의 문제를 해결하기 위해, 알루미늄 보다 매립 특성이 우수한 텅스텐막으로 콘택홀을 완전 매립시켜, 이것을 금속배선과 하부구조물간의 전기적 연결을 위한 콘택플러그로 이용하는 기술이 제안되었다. Therefore, in order to solve the problem of contact hole embedding, a technique has been proposed in which a contact hole is completely filled with a tungsten film having better embedding properties than aluminum, and used as a contact plug for electrical connection between metal wiring and a substructure.
그런데, 상기 텅스텐은 배선 형태로 건식 식각하기가 용이하지 않기 때문에, 금속배선을 형성하기 위해서는 다마신(Damascene)이라는 새로운 공정 기술이 이용된다. However, since tungsten is not easily dry-etched in the form of wiring, a new process technology called damascene is used to form metal wiring.
상기 다마신 공정은 절연막을 식각하여 절연막 내에 금속배선용 콘택홀을 먼저 형성한 후, 상기 콘택홀 표면에 절연막과 금속막의 확산을 방지하기 위한 베리어막(Diffusion Barrier)으로서 Ti막, 또는, TiN막을 증착하고 나서, 상기 콘택홀을 완전히 매립하도록 텅스텐을 매립시켜 금속배선을 형성하는 방법이다. In the damascene process, an insulating film is etched to form a metal wiring contact hole in the insulating film first, and then a Ti film or a TiN film is deposited as a barrier film to prevent diffusion of the insulating film and the metal film on the contact hole surface. Then, tungsten is embedded to completely fill the contact hole, thereby forming a metal wiring.
한편, 상기 베리어막으로서 상기 Ti막과 TiN막을 모두 사용해서 Ti막/TiN막의 구조를 적용하는 방법이 제안된 바 있다.On the other hand, a method of applying the structure of the Ti film / TiN film using both the Ti film and the TiN film as the barrier film has been proposed.
그러나, 자세하게 도시하고 설명하지는 않았지만, Ti막과 TiN막을 모두 사용하여 Ti/TiN막을 베리어막으로 사용하는 종래의 방법은, 상기 Ti/TiN막이 스퍼터 방식으로 증착됨으로 인해 깊이가 깊고 폭이 좁은 고단차의 금속 배선용 플러그와 같은 콘택홀에서는 층덮힘 불량이 발생할 가능성이 높다.However, although not shown and described in detail, the conventional method of using a Ti / TiN film as a barrier film by using both a Ti film and a TiN film, has a deep and narrow high step due to the deposition of the Ti / TiN film by sputtering. Contact holes, such as metal wiring plugs, are more likely to cause layer coverage.
이로 인해, 후속의 텅스텐을 증착할때 증착 소오스 가스인 WF6의 F가 TiN의 하부층인 Ti와 반응하여 볼케이노(volcano) 현상을 유발하게 되어, 상기와 같은 볼케이노 현상에 의해 금속배선의 단락 및 접합누설전류가 증가된다.As a result, when the subsequent tungsten is deposited, F of the deposition source gas, WF6, reacts with Ti, which is the lower layer of TiN, to cause volcano, and thus, short-circuit and junction leakage of the metal wiring may be caused by the volcano. The current is increased.
결과적으로, 주지한 문제점들로 인하여 반도체 소자의 신뢰성 및 전기적 특성을 감소시킨다.As a result, known problems reduce the reliability and electrical properties of the semiconductor device.
따라서, 본 발명은 층덮힘 불량 및 볼케이노 현상을 방지할 수 있는 반도체 소자의 금속 플러그 및 그 제조방법을 제공한다.Accordingly, the present invention provides a metal plug of a semiconductor device and a method of manufacturing the same that can prevent a layer covering defect and a volcano phenomenon.
또한, 본 발명은 층덮힘 불량 및 볼케이노 현상을 방지함으로써, 금속배선의 단락 및 접합누설전류의 증가를 방지할 수 있는 반도체 소자의 금속 플러그 및 그 제조방법을 제공한다.In addition, the present invention provides a metal plug of a semiconductor device and a method of manufacturing the same, which can prevent a layer covering defect and a volcano phenomenon, thereby preventing short circuit of the metal wiring and increase in junction leakage current.
게다가, 본 발명은 반도체 소자의 신뢰성 및 전기적 특성의 감소를 방지할 수 있는 반도체 소자의 금속 플러그 및 그 제조방법을 제공한다.In addition, the present invention provides a metal plug of a semiconductor device and a method of manufacturing the same, which can prevent a decrease in reliability and electrical characteristics of the semiconductor device.
일 실시예에 있어서, 반도체 소자의 금속 플러그는 하부구조물이 형성된 반도체기판; 상기 반도체기판 상에 형성되며, 콘택홀을 구비한 절연막; 상기 콘택홀 표면 상에 형성된 베리어막; 및 상기 베리어막 상에 콘택홀을 매립하도록 형성된 금속막;을 포함하고, 상기 베리어막은 루테늄(Ru)으로 이루어진다.In an embodiment, the metal plug of the semiconductor device may include a semiconductor substrate on which a substructure is formed; An insulating film formed on the semiconductor substrate and having contact holes; A barrier film formed on a surface of the contact hole; And a metal film formed to fill a contact hole on the barrier film, wherein the barrier film is made of ruthenium (Ru).
상기 금속막은 텅스텐막으로 이루어진다.The metal film is made of a tungsten film.
다른 실시예에 있어서, 반도체 소자의 금속 플러그 제조방법은 하부구조물이 형성된 반도체기판 상에 콘택홀이 구비된 절연막을 형성하는 단계; 상기 콘택홀 표면 상에 루테늄막을 증착하는 단계; 상기 루테늄막 상에 상기 콘택홀을 매립하도록 텅스텐막을 형성하는 단계; 및 상기 텅스텐막 및 루테늄막을 CMP하는 단계; 를 포함한다.In another embodiment, a method of manufacturing a metal plug of a semiconductor device may include forming an insulating film having contact holes on a semiconductor substrate on which a lower structure is formed; Depositing a ruthenium film on the contact hole surface; Forming a tungsten film to fill the contact hole on the ruthenium film; And CMP the tungsten film and the ruthenium film; It includes.
상기 루테늄막은 PEALD(plasma enhaced atomic layer deposition) 공정으로 형성한다.The ruthenium film is formed by a plasma enhaced atomic layer deposition (PEALD) process.
상기 PEALD 공정은 전구체로 Ru(EtCp)2를 이용하고, 반응물로는 NH3 플라즈마를 이용하여 수행한다.The PEALD process uses Ru (EtCp) 2 as a precursor and NH 3 plasma as a reactant.
상기 PEALD 공정은 300∼500W의 전압, 300∼320℃의 온도 및 Ar(carrier) 가스로 150sccm, NH3 가스로 50∼100sccm로 수행한다.The PEALD process is performed at a voltage of 300-500 W, a temperature of 300-320 ° C., 150 sccm with Ar (carrier) gas, and 50-100 sccm with NH 3 gas.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은, 절연막을 식각하여 콘택홀을 형성한 후, 상기 콘택홀을 포함한 절연막 상에 PEALD(plasma enhanced atomic layer deposition) 방식을 이용하여 루테늄막으로 베리어막을 형성하고, 이어서, 상기 루테늄막 상에 상기 콘택홀을 매립하도록 텅스텐막을 형성한 다음, 상기 텅스텐막 및 루테늄막을 CMP하여 금속배선을 형성한다.According to the present invention, after forming the contact hole by etching the insulating film, a barrier film is formed of a ruthenium film using a plasma enhanced atomic layer deposition (PEALD) method on the insulating film including the contact hole, and then on the ruthenium film A tungsten film is formed to fill the contact hole, and then the tungsten film and the ruthenium film are CMP to form metal wiring.
이렇게 하면, 베리어막을 하나의 단일막으로 이루어진 루테늄막을 사용함으로써, 금속 배선용 플러그를 형성하기 위한 베리어막을 Ti/TiN막으로 이용하는 종 래의 반도체 소자의 금속 플러그와 달리, 금속 배선용 플러그의 베리어막을 형성하는 공정의 단순화를 얻을 수 있다.In this way, by using a ruthenium film composed of a single film as a barrier film, unlike the metal plug of a conventional semiconductor element using a barrier film for forming a metal wiring plug as a Ti / TiN film, a barrier film for a metal wiring plug is formed. Simplification of the process can be obtained.
또한, 스퍼터(sputter) 방식으로 증착하여 형성하는 Ti/TiN막으로 이루어진 종래의 베리어막과 달리, 상기 베리어막을 PEALD 방식을 이용하여 루테늄막을 증착함으로써, 깊고 좁은 고단차의 금속 배선용 플러그와 같은 콘택홀에서 발생하는 층덮힘 불량을 방지할 수 있다.In addition, unlike conventional barrier films made of a Ti / TiN film formed by sputtering, a ruthenium film is deposited by using a PEALD method, thereby contact holes such as plugs for deep and narrow high-level metal wiring. It is possible to prevent layer covering defects occurring in the.
게다가, 상기와 같이 PEALD 방식으로 루테늄막을 증착하여 층덮힘 불량을 방지함으로써, 후속의 텅스텐막을 증착할때의 반응가스와 Ti/TiN막의 Ti간의 반응으로 발생하는 볼케이노(volcano) 현상 및 Rs(Resistance sheet)를 감소시킬 수 있다.In addition, by depositing a ruthenium film in the PEALD method as described above to prevent the layer covering failure, the volcano phenomenon and Rs (Resistance sheet) generated by the reaction between the reaction gas and Ti / TiN film Ti during the subsequent deposition of tungsten film ) Can be reduced.
도 1은 본 발명의 실시예에 따른 반도체 소자의 금속 플러그를 도시한 단면도이다.1 is a cross-sectional view illustrating a metal plug of a semiconductor device according to an embodiment of the present invention.
도 1에 도시된 바와 같이, 반도체기판(100) 상에 콘택홀(104)을 갖는 절연막(102)이 형성된다. 상기 반도체기판(100)은, 하부 구조물, 예컨대, 트랜지스터, 비트라인 및 캐패시터가 형성되어진 것으로 이해될 수 있다. 상기 콘택홀(104) 표면 상에는 베리어막(106)이 형성되고, 상기 베리어막(106) 상에는 상기 콘택홀(104)을 매립하도록 텅스텐막(108)이 형성된다. 상기 베리어막(106)은 루테늄(Ru)으로 이루어진다.As shown in FIG. 1, an
본 발명은 상기 베리어막(106)을 단일막인 루테늄막만 형성함으로써, Ti, TiN 및 Ti/TiN막으로 베리어막을 사용하는 종래의 그것과는 달리 베리어막을 형성 하는 공정을 단순화시킬 수 있다. The present invention can simplify the process of forming the barrier film, unlike the conventional method using the barrier film as the Ti, TiN and Ti / TiN films by forming only the ruthenium film as the single film.
또한, 본 발명은 베리어막 물질을 Ti 및 TiN 보다 저항이 낮은 루테늄을 이용함으로써 낮은 콘택저항를 얻을 수 있다.In addition, according to the present invention, low contact resistance can be obtained by using ruthenium having a lower resistance than that of Ti and TiN.
도 2a 및 도 2d는 본 발명의 실시예에 따른 반도체 소자의 금속 플러그 제조방법을 설명하기 위한 공정별 단면도이다.2A and 2D are cross-sectional views illustrating processes of manufacturing a metal plug of a semiconductor device according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 하부구조물이 형성된 반도체기판(200) 상에 절연막(202)을 형성하고, 상기 절연막(202)을 식각하여 콘택홀(204)을 형성한다.Referring to FIG. 2A, an
도 2b를 참조하면, 상기 콘택홀(204) 표면 상에 베리어막(206)을 증착한다. 상기 베리어막(206)은 루테늄막으로 증착하도록 한다. 여기서, 상기 루테늄막은 PEALD(plasma enhaced atomic layer deposition) 공정으로 형성하도록 하며, 상기 PEALD 공정의 전구체로는 Ru(EtCp)2를 이용하고 반응물로는 NH3 플라즈마를 이용하여 수행하도록 한다.Referring to FIG. 2B, a
또한, 상기 PEALD 공정은 300∼500W의 전압, 300∼320℃의 온도 및 Ar(carrier) 가스로 150sccm, NH3 가스로 50∼100sccm로 수행하도록 한다.In addition, the PEALD process is carried out at a voltage of 300 to 500W, a temperature of 300 to 320 ℃ and 150sccm with Ar (carrier) gas, 50-100sccm with NH3 gas.
도 2c를 참조하면, 상기 루테늄막이 증착된 콘택홀(204)상에, 상기 콘택홀(204)를 매립하도록 금속막(208)을 형성한다. 여기서, 상기 금속막(208)은 텅스텐으로 형성하도록 한다.Referring to FIG. 2C, a
도 2d를 참조하면, 상기 금속막(208) 및 베리어막(206)막을 화학적기계연마하여 평탄화한다.Referring to FIG. 2D, the
이와 같이, 본 발명은 베리어막을 루테늄막을 사용하여 단일막만으로 구성함 으로써, 그에 따른 베리어막을 형성하는 공정의 단순화를 얻을 수 있다.As described above, the present invention can simplify the process of forming the barrier film by configuring the barrier film as a single film using a ruthenium film.
또한, 본 발명은 종래의 스퍼터(sputter) 방식으로 증착되는 Ti/TiN막과 달리, PEALD 방식을 이용하여 루테늄막을 증착함으로써 깊고 좁은 고단차의 금속 배선용 플러그와 같은 콘택홀에서 발생하는 층덮힘 불량을 방지할 수 있다.In addition, the present invention, unlike the conventional Ti / TiN film deposited by the sputter method, by depositing a ruthenium film using a PEALD method to eliminate the layer covering defects generated in contact holes such as deep and narrow high-level metal wiring plugs You can prevent it.
게다가, 본 발명은 상기와 같이 PEALD 방식으로 루테늄막을 증착하여 층덮힘 불량을 방지함으로써, Ti/TiN막의 Ti과 증착가스간의 반응으로 발생하는 볼케이노(volcano) 현상 및 Rs(Resistance sheet)를 감소시킬 수 있다.In addition, the present invention is to prevent the layer covering failure by depositing a ruthenium film in the PEALD method as described above, it is possible to reduce the volcano phenomenon and resistance sheet (Rs) caused by the reaction between Ti and the deposition gas of the Ti / TiN film have.
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
이상에서와 같이, 본 발명은 베리어막을 단일막으로 이루어진 루테늄막을 사용함으로써 베리어막 형성 공정의 단순화를 얻을 수 있다. 또한, 본 발명은 PEALD 방식을 이용하여 루테늄막을 증착함으로써 층덮힘 불량을 방지할 수 있다. 게다가, 본 발명은 상기와 같이 층덮힘 불량을 방지함으로써, 볼케이노(volcano) 현상 및 Rs(Resistance sheet)를 감소시킬 수 있다. 아울러, 본 발명은 상기와 같이 볼케이노 현상 및 Rs를 감소시킬 수 있음으로써, 반도체 소자의 신뢰성 및 전기적 특성을 향상시킬 수 있다.As described above, in the present invention, a barrier film forming process can be simplified by using a ruthenium film having a barrier film as a single film. In addition, the present invention can prevent a layer covering defect by depositing a ruthenium film using a PEALD method. In addition, the present invention can reduce the volcano phenomenon and the resistance sheet (Rs) by preventing the layer covering defect as described above. In addition, the present invention can reduce the volcano phenomenon and Rs as described above, thereby improving the reliability and electrical characteristics of the semiconductor device.
Claims (6)
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| KR1020060133037A KR20080058863A (en) | 2006-12-22 | 2006-12-22 | Metal plug of semiconductor device and method of manufacturing the same |
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