KR20070001752A - Method for fabricating bit line in semiconductor device - Google Patents

Method for fabricating bit line in semiconductor device Download PDF

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KR20070001752A
KR20070001752A KR1020050057385A KR20050057385A KR20070001752A KR 20070001752 A KR20070001752 A KR 20070001752A KR 1020050057385 A KR1020050057385 A KR 1020050057385A KR 20050057385 A KR20050057385 A KR 20050057385A KR 20070001752 A KR20070001752 A KR 20070001752A
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bit line
film
tungsten
forming
interlayer insulating
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KR1020050057385A
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Korean (ko)
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임성원
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주식회사 하이닉스반도체
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Publication of KR20070001752A publication Critical patent/KR20070001752A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a bit line of a semiconductor device is provided to improve electrical stability by preventing the loss of a tungsten film due to a cleaning process using a tungsten silicide layer. First and second interlayer dielectrics(211,230) are formed on a semiconductor substrate(200). A bit line contact hole(235) is formed on the resultant structure by etching selectively the second interlayer dielectric. A tungsten film(240) is formed thereon. A tungsten silicide layer(250) for filling the bit line contact hole is formed on the tungsten film. A hard mask nitride layer is formed on the tungsten silicide layer. A bit line is formed on the resultant structure by etching sequentially the hard mask nitride layer and the tungsten silicide layer.

Description

반도체 소자의 비트라인 형성 방법{Method for fabricating bit line in semiconductor device}Method for fabricating bit line in semiconductor device

도 1은 종래기술에 따른 반도체소자의 비트라인 형성 방법 및 그 문제점을 설명하기 위해 나타내 보인 셈(SEM)사진이다.FIG. 1 is a SEM photograph illustrating a method of forming a bit line of a semiconductor device and a problem thereof according to the related art.

도 2 내지 도 4는 본 발명에 따른 반도체소자의 비트라인 형성 방법을 설명하기 위해 나타내 보인 단면도들이다.2 to 4 are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the present invention.

-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing

200 : 반도체 기판 210 :게이트스택200 semiconductor substrate 210 gate stack

211 : 제1 층간절연막 220 : 랜딩플러그콘택211: first interlayer insulating film 220: landing plug contact

230 : 제2 층간절연막 235 : 비트라인콘택홀230: second interlayer insulating film 235: bit line contact hole

240 : 텅스텐막 250 : 텅스텐실리사이드막240: tungsten film 250: tungsten silicide film

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 세정공정으로부터 텅스텐막이 손실되는 것을 방지하여 전기적으로 안정적인 소자를 형성하기 위한 반도체 소자의 비트라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a bit line of a semiconductor device for forming an electrically stable device by preventing the loss of a tungsten film from a cleaning process.

일반적으로 반도체소자의 메모리(memory) 셀(cell)에서 1비트 단위의 데이터를 저장할 수 있는 단위기억소자를 구성하는 요소 중, 데이터를 입출력 할 수 있는 통로를 비트라인(bit line)이라고 한다.In general, a path for inputting / outputting data is called a bit line among elements constituting a unit memory device capable of storing data of 1 bit unit in a memory cell of a semiconductor device.

도 1은 종래기술에 따른 반도체소자의 비트라인 형성 방법 및 그 문제점을 설명하기 위해 나타내보인 셈(SEM)사진이다.1 is a SEM photograph illustrating a method of forming a bit line of a semiconductor device and a problem thereof according to the related art.

도 1을 참조하면, 반도체 기판(미도시) 상에 형성된 제1 층간절연막(100) 위에 제2 층간절연막(110)을 형성한다. 다음에 제2 층간절연막(110)의 일부를 식각하여 비트라인콘택홀(115)을 형성하고, 비트라인콘택홀(115) 및 제2 층간절연막(110) 위에 비트라인스택 형성물질(미도시)을 형성한다. 다음에 제2 층간절연막(110) 및 비트라인스택 형성물질을 식각하여 비트라인콘택(120)을 포함하는 비트라인(140)을 형성한다. 비트라인(140)은, 텅스텐막(131)과 하드마스크질화막(133) 및 반사방지막(135)이 순차 적층되어 이루어진다. 도면에서 나타내지는 않았지만, 제1 층간절연막(100) 내에는 게이트스택(미도시) 및 랜딩플러그콘택(미도시)가 형성되있다. Referring to FIG. 1, a second interlayer insulating film 110 is formed on a first interlayer insulating film 100 formed on a semiconductor substrate (not shown). Next, a portion of the second interlayer insulating layer 110 is etched to form a bit line contact hole 115, and a bit line stack forming material (not shown) is formed on the bit line contact hole 115 and the second interlayer insulating layer 110. To form. Next, the second interlayer insulating layer 110 and the bit line stack forming material are etched to form a bit line 140 including the bit line contact 120. The bit line 140 is formed by sequentially stacking a tungsten film 131, a hard mask nitride film 133, and an antireflection film 135. Although not shown, a gate stack (not shown) and a landing plug contact (not shown) are formed in the first interlayer insulating film 100.

이와 같이 비트라인을 형성한 후, 반도체 메소리소자 , 특히 디램(DRAM)소자의 경우 다음에 비트라인스택(140)이 덮히도록 제2 층간절연막(110) 위에 제3 층간절연막(미도시)을 형성하고, 스토리지노드콘택홀 형성용 마스크막(미도시)을 형성한 다. 다음에 이를 식각마스크로 제3 절연막을 식각하여 스토리지노드콘택홀(미도시)을 형성한다. 다음에 제3 절연막 및 스토리지노드콘택홀 위에 폴리실리콘막을 형성하여 스토리지노드콘택홀을 매립하고, 에치백 공정을 수행하여 제3 절연막 위에 있는 폴리실리콘막을 제거한다. 그러면 스토리지노드콘택이 형성된다. 다음에 스토리지노드콘택 형성공정으로 인한 공정상의 잔여물을 제거하기 위한 세정공정을 수행한다.After forming the bit line as described above, a third interlayer insulating film (not shown) is formed on the second interlayer insulating film 110 so as to cover the bit line stack 140 in the case of a semiconductor sounding device, particularly a DRAM device. And a mask film (not shown) for forming a storage node contact hole. Next, the third insulating layer is etched using an etching mask to form a storage node contact hole (not shown). Next, a polysilicon layer is formed on the third insulating layer and the storage node contact hole to fill the storage node contact hole, and an etch back process is performed to remove the polysilicon layer on the third insulating layer. The storage node contact is then formed. Next, a cleaning process for removing process residues caused by the storage node contact forming process is performed.

세정공정은, RON세정액, 즉 수산화암모늄(NH4OH)과 과산화수소(H2O2) 및 물(H2O)이 1:4:20의 비율로 혼합된 N세정용액과 황산(H2SO4)과 과산화수소(H2O2)가 50:1의 비율로 혼합된 R세정용액 및 불화암모늄(NH4F)과 불산(HF)이 300:1로 혼합된 O세정액을 사용하여 수행하며, 이에 따라 스토리지노드콘택홀을 형성하기 위한 공정상의 잔여물을 제거할 수 있다. The washing process includes N cleaning solution and sulfuric acid (H 2 SO 4 ) in which RON washing solution, that is, ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), and water (H 2 O) is mixed at a ratio of 1: 4: 20. It is carried out using a R washing solution in which hydrogen peroxide (H 2 O 2 ) is mixed at a ratio of 50: 1 and an O washing solution in which ammonium fluoride (NH 4 F) and hydrofluoric acid (HF) are mixed at 300: 1. Process residues for forming storage node contact holes may be removed.

이와 같이 종래기술에 따른 반도체소자의 비트라인스택 형성 방법은, 스토리노드콘택홀 형성 후 RON세정액을 사용하는 세정공정에서, 비트라인스택인 하드마스크 질화막(133)의 나쁜 스텝커버리지(step coverage)로 인해 RON세정액이 하드마스크 질화막(133)을 침투경로로 텅스텐막(131)에 침투한다는 문제가 있다. RON세정액은, 텅스텐막(131)을 제거하는 성분을 포함하고 있기 때문에 텅스텐막(313)에 RON세정액이 침투하면, 도면에서 'A'로 표시한 바와 같이 텅스텐막이 제거되고, 이에 따라 비트라인의 저항이 무한대로 증가하게 되어 소자의 전기적인 특성을 저하시킨다는 문제가 있다.As described above, the bit line stack forming method of the semiconductor device according to the related art is a bad step coverage of the hard mask nitride film 133 which is the bit line stack in the cleaning process using the RON cleaning liquid after the formation of the story node contact hole. Therefore, there is a problem that the RON cleaning liquid penetrates the hard mask nitride film 133 into the tungsten film 131 as a penetration path. Since the RON cleaning liquid contains a component that removes the tungsten film 131, when the RON cleaning liquid penetrates the tungsten film 313, the tungsten film is removed as indicated by 'A' in the drawing. There is a problem that the resistance is increased to infinity, which lowers the electrical characteristics of the device.

본 발명이 이루고자 하는 기술적 과제는, 세정공정으로부터 텅스텐막이 손실되는 것을 방지하여 전기적으로 안정적인 소자를 형성하기 위한 반도체 소자의 비트라인 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a bit line of a semiconductor device for forming an electrically stable device by preventing the loss of tungsten film from the cleaning process.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체소자의 비트라인 형성 방법은, 반도체 기판 위의 제1 층간절연막 상에 제2 층간절연막을 형성하는 단계; 상기 제2 층간절연막을 선택 식각하여 비트라인콘택홀을 형성하는 단계; 상기 비트라인콘택홀 및 제2 층간절연막 내에 텅스텐막을 형성하는 단계; 상기 텅스텐막 위에 텅스텐실리사이드막을 형성하여 상기 비트라인콘택홀을 매립하는 단계; 상기 텅스텐실리사이드막 위에 하드마스크 질화막을 형성하는 단계; 상기 하드마스크 질화막과 텅스텐실리사이드막 및 텅스텐막을 순차 식각하여 비트라인을 형성하는 단계를 포함한다.In order to achieve the above technical problem, a method of forming a bit line of a semiconductor device according to the present invention, forming a second interlayer insulating film on the first interlayer insulating film on the semiconductor substrate; Selectively etching the second interlayer insulating layer to form a bit line contact hole; Forming a tungsten film in the bit line contact hole and the second interlayer insulating film; Filling the bit line contact hole by forming a tungsten silicide film on the tungsten film; Forming a hard mask nitride layer on the tungsten silicide layer; And sequentially etching the hard mask nitride film, the tungsten silicide film, and the tungsten film to form a bit line.

상기 텅스텐실리사이드막은, 화학적기상증착 방법으로 형성할 수 있다.The tungsten silicide film may be formed by a chemical vapor deposition method.

이 경우 화학적기상증착 방법은, 30-200sccm의 이염화실란 가스 및 3-10sccm의 육불화텅스텐 가스를 사용하여 수행할 수 있다.In this case, the chemical vapor deposition method may be performed using 30-200 sccm dichlorochloride gas and 3-10 sccm tungsten hexafluoride gas.

또한 상기 화학적기상증착 방법은, 상기 이염화실란 가스를 육불화텅스텐 가스보다 대략 5-10배 공급하여 수행할 수 있다.In addition, the chemical vapor deposition method may be performed by supplying the silane dichloride gas approximately 5-10 times than tungsten hexafluoride gas.

상기 텅스텐실리사이드막은, 20-100Å의 두께로 형성할 수 있다.The tungsten silicide film may be formed to a thickness of 20-100 kPa.

이하 첨부한 도면을 참조하여 본 발명의 실시예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 도면에서 여러층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 명세서 전체를 통하여 유사한 부분에 대해서는 동일한 부호를 붙였다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

도 2 내지 도 4는 본 발명에 따른 반도체소자의 비트라인 형성 방법을 설명하기위해 타나내 보인 단면도들이다.2 to 4 are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the present invention.

먼저 도 2를 참조하면, 반도체 기판(200) 위에 게이트스택(210) 및 랜딩플러그콘택(220)을 갖는 제1 층간절연막(211)을 형성한 다음에 제1 층간절연막(211) 위에 제2 층간절연막(230)을 형성한다. 게이트스택(210)은, 게이트산화막(205)과 게이트도전막(207) 및 게이트하드마스크막(209)이 순차 적층되어 이루어진다. 도면에서 미 설명한 도면부호(215)는 게이트스페이서 이다. 게이트스페이서는, 후속공정으로부터 게이트를 보호한다. 도면에서 나타내지는 않았지만, 반도체 기판(100) 내에는 소스/드레인 불순물 영역(미도시)이 형성되어 있다. First, referring to FIG. 2, a first interlayer insulating film 211 having a gate stack 210 and a landing plug contact 220 is formed on a semiconductor substrate 200, and then a second interlayer is formed on the first interlayer insulating film 211. The insulating film 230 is formed. The gate stack 210 is formed by sequentially stacking a gate oxide film 205, a gate conductive film 207, and a gate hard mask film 209. Reference numeral 215, which is not described in the drawing, is a gate spacer. The gate spacer protects the gate from subsequent steps. Although not shown in the drawing, a source / drain impurity region (not shown) is formed in the semiconductor substrate 100.

다음에 도 3을 참조하면, 제2 층간절연막(230)의 일부를 식각하여 제1 절연막(211) 내에 형성된 랜딩플러그콘택(220) 상부 표면을 노출시키는 비트라인콘택홀(235)을 형성한다. 다음에 노출된 랜딩플러그콘택(220)의 상부 표면이 덮이도록 비트라인콘택홀(235) 및 제2 층간절연막(230) 위에 텅스텐막(240)을 형성한다. Next, referring to FIG. 3, a portion of the second interlayer insulating layer 230 is etched to form a bit line contact hole 235 exposing the upper surface of the landing plug contact 220 formed in the first insulating layer 211. Next, a tungsten film 240 is formed on the bit line contact hole 235 and the second interlayer insulating film 230 to cover the exposed top surface of the landing plug contact 220.

텅스텐막은, 화학적기상증착 방법(CVD; Chemical Vapor Deposition)을 사용하여 형성한다. 보다 상세하게는 비트라인콘택홀(235)이 형성된 구조체를 화학적기상증착 챔버(chamber) 내에 로딩한다. 다음에 육불화텅스텐(WF6) 및 사일렌(SiH4) 가스를 챔버 내에 공급하여 텅스텐 씨드층(seed layer)을 형성한다. 다음에 육불화텅스텐 및 수소(H2)가스를 공급하여 텅스텐 씨드층 위에 원하는 두께의 텅스텐막(240)을 형성한다. 텅스텐막은, 비트라인콘택홀(235)이 모두 매립되지 않는 두께로 형성하며, 상기 미 설명한 도면부호(236)는 장벽금속막이다. The tungsten film is formed using a chemical vapor deposition method (CVD). More specifically, the structure in which the bit line contact hole 235 is formed is loaded into a chemical vapor deposition chamber. Next, tungsten hexafluoride (WF 6 ) and xylene (SiH 4 ) gases are supplied into the chamber to form a tungsten seed layer. Next, tungsten hexafluoride and hydrogen (H 2 ) gas are supplied to form a tungsten film 240 having a desired thickness on the tungsten seed layer. The tungsten film is formed to a thickness where all of the bit line contact holes 235 are not embedded, and the above-described reference numeral 236 is a barrier metal film.

다음에 도 4를 참조하면, 텅스텐막(240) 위에 텅스텐실리사이드막(250)을 형성하여 비트라인콘택홀(235)을 매립한다. 텅스텐실리사이드막(250)을 형성하기 위해서는 텅스텐막(240)이 증착된 화학적기상증착 챔버(chamber) 내에 이염화실란(SiH2Cl2)가스 및 육불화텅스텐(WF6)가스를 공급한다. 예컨대 대략 30-200sccm의 이염화실란 가스와, 대략 3-10sccm의 육불화텅스텐 가스를 공급하여 대략 20-100Å두께의 텅스텐실리사이드막(250)을 형성한다. 이때 텅스텐실리사이드막이 보다 잘 형성되도록 하기 위해 이염화실란 가스를 육불화텅스텐 가스보다 대략 5-10배 이상으로 공급한다.Referring to FIG. 4, a tungsten silicide layer 250 is formed on the tungsten layer 240 to fill the bit line contact hole 235. In order to form the tungsten silicide film 250, a silane dichloride (SiH 2 Cl 2 ) gas and a tungsten hexafluoride (WF 6 ) gas are supplied into a chemical vapor deposition chamber in which the tungsten film 240 is deposited. For example, a tungsten silicide film 250 having a thickness of approximately 20-100 μs is formed by supplying a silane dichloride gas of approximately 30-200 sccm and a tungsten hexafluoride gas of approximately 3-10 sccm. At this time, in order to form the tungsten silicide film better, the silane dichloride gas is supplied at about 5-10 times or more than the tungsten hexafluoride gas.

이와 같은 방법으로 텅스텐막(240) 위에 형성된 텅스텐실리사이드막(250)은, 스토리지노드콘택 형성공정에서의 잔여물을 제거하기 위한 후속공정, 즉 RON세정액을 사용한 후속의 세정공정으로부터 텅스텐막을 보호하기 때문에, 후속의 세정공정, 즉 RON세정액을 사용한 세정공정에서 텅스텐막이 손실되는 것을 막을 수 있다.In this manner, the tungsten silicide film 250 formed on the tungsten film 240 protects the tungsten film from a subsequent process for removing residues from the storage node contact forming process, that is, a subsequent cleaning process using RON cleaning liquid. The loss of the tungsten film can be prevented in the subsequent cleaning step, i.e., the cleaning step using the RON cleaning liquid.

다음에 도면에서 도시하지는 않았지만 텅스텐실리사이드(250)막 위에 하드마스크질화막과 반사방지막(ARC; Anti Reflection)을 형성한다. 다음에 이를 순차 식각하여 비트라인콘택을 포함하는 비트라인을 형성한다.Next, although not shown in the drawings, a hard mask nitride film and an antireflection film (ARC) are formed on the tungsten silicide 250 film. Next, it is sequentially etched to form a bit line including bit line contacts.

이와 같이 비트라인을 형성한 다음에 비트라인이 매립되도록 비트라인 위에 제3 층간절연막(미도시)을 형성하고, 이를 선택 식각하여 제1 절연막(211)내에 형성된 랜딩플러그콘택 상부 표면을 노출시키는 스토리지노드콘택홀(미도시)을 형성 한다. 다음에 제3 층간절연막 및 스토리지노드콘택 위에 폴리실리콘막(미도시)을 형성하여 스토리지노드콘택홀을 매립한다. 다음에 제3 절연막 위에 형성된 폴리실리콘막을 에치백하여 상호 분리된 스토리지노드콘택(미도시)을 형성한다. 다음에 RON세정액을 이용한 세정공정을 수행하여 스토리지노드콘택을 형성하기 위한 공정에서의 잔여물을 제거한다. 이때 텅스텐막 위에는 텅스텐실리사이드막이 형성되어 있기 때문에 RON세정액으로부터 텅스텐막을 보호할 수 있다. 다음에 후속공정을 수행하여 커패시터를 형성한다.After forming the bit line as described above, a third interlayer insulating film (not shown) is formed on the bit line so that the bit line is embedded, and selectively etched to expose the top surface of the landing plug contact formed in the first insulating film 211. A node contact hole (not shown) is formed. Next, a polysilicon film (not shown) is formed on the third interlayer insulating film and the storage node contact to fill the storage node contact hole. Next, the polysilicon film formed on the third insulating film is etched back to form storage node contacts (not shown) separated from each other. Next, a cleaning process using a RON cleaning solution is performed to remove residues from the process for forming the storage node contact. At this time, since the tungsten silicide film is formed on the tungsten film, the tungsten film can be protected from the RON cleaning liquid. Next, a subsequent process is performed to form a capacitor.

상술한 바와 같이, 본 발명에 따른 반도체소자의 비트라인 형성 방법을 적용하면, 텅스텐막 위에 RON세정액과 반응하지 않는 텅스텐실리사이드막을 형성하여 텅스텐막을 보호하였다. 이에 따라 후속의 세정공정으로부터 텅스텐막이 손실되는 것을 방지하여 소자의 전기적인 특성을 향상시킬 수 있다.As described above, according to the method of forming the bit line of the semiconductor device according to the present invention, a tungsten silicide film which does not react with the RON cleaning solution was formed on the tungsten film to protect the tungsten film. This prevents the loss of the tungsten film from subsequent cleaning processes, thereby improving the electrical characteristics of the device.

이상에서 본 발명의 바람직한 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리보호범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량형태 또한 본 발명의 권리보호 범위에 속하는 것이다.Although the preferred embodiment of the present invention has been described in detail above, the scope of protection of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also provided. It belongs to the scope of protection of the invention.

Claims (5)

반도체 기판 위의 제1 층간절연막 상에 제2 층간절연막을 형성하는 단계;Forming a second interlayer insulating film on the first interlayer insulating film over the semiconductor substrate; 상기 제2 층간절연막을 선택 식각하여 비트라인콘택홀을 형성하는 단계;Selectively etching the second interlayer insulating layer to form a bit line contact hole; 상기 비트라인콘택홀 및 제2 층간절연막 내에 텅스텐막을 형성하는 단계;Forming a tungsten film in the bit line contact hole and the second interlayer insulating film; 상기 텅스텐막 위에 텅스텐실리사이드막을 형성하여 상기 비트라인콘택홀을 매립하는 단계;Filling the bit line contact hole by forming a tungsten silicide film on the tungsten film; 상기 텅스텐실리사이드막 위에 하드마스크 질화막을 형성하는 단계;Forming a hard mask nitride layer on the tungsten silicide layer; 상기 하드마스크 질화막과 텅스텐실리사이드막 및 텅스텐막을 순차 식각하여 비트라인을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 비트라인 형성 방법. And etching the hard mask nitride film, the tungsten silicide film, and the tungsten film sequentially to form a bit line. 제1항에 있어서,The method of claim 1, 상기 텅스텐실리사이드막은, 화학적기상증착 방법으로 형성하는 것을 특징으로 하는 반도체소자의 비트라인 형성 방법.The tungsten silicide layer is formed by a chemical vapor deposition method. 제2항에 있어서,The method of claim 2, 상기 화학적기상증착 방법은, 30-200sccm의 이염화실란 가스 및 3-10sccm의 육불화텅스텐 가스를 사용하여 수행하는 것을 특징으로 하는 반도체소자의 비트라인 형성 방법.The chemical vapor deposition method is a bit line forming method of a semiconductor device, characterized in that performed using 30-200sccm dichlorochloride gas and 3-10sccm tungsten hexafluoride gas. 제2항에 있어서,The method of claim 2, 상기 화학적기상증착 방법은, 상기 이염화실란 가스를 육불화텅스텐 가스보다 대략 5-10배 공급하여 수행하는 것을 특징으로 하는 반도체소자의 비트라인 형성 방법.The chemical vapor deposition method is a bit line forming method of a semiconductor device, characterized in that performed by supplying about 5-10 times the tungsten hexafluoride gas. 제1항에 있어서,The method of claim 1, 상기 텅스텐실리사이드막은, 20-100Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 비트라인 형성 방법.And the tungsten silicide film is formed to a thickness of 20-100 kPa.
KR1020050057385A 2005-06-29 2005-06-29 Method for fabricating bit line in semiconductor device KR20070001752A (en)

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