KR20060124904A - Method for manufacturing a fin field effect transistor - Google Patents

Method for manufacturing a fin field effect transistor Download PDF

Info

Publication number
KR20060124904A
KR20060124904A KR1020050046582A KR20050046582A KR20060124904A KR 20060124904 A KR20060124904 A KR 20060124904A KR 1020050046582 A KR1020050046582 A KR 1020050046582A KR 20050046582 A KR20050046582 A KR 20050046582A KR 20060124904 A KR20060124904 A KR 20060124904A
Authority
KR
South Korea
Prior art keywords
substrate
fin
trench
field effect
effect transistor
Prior art date
Application number
KR1020050046582A
Other languages
Korean (ko)
Inventor
이창영
김상영
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020050046582A priority Critical patent/KR20060124904A/en
Publication of KR20060124904A publication Critical patent/KR20060124904A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a fin field effect transistor is provided to isolate a substrate from a fin field effect transistor by a thermal oxide layer by performing a thermal oxide process on a bulk substrate with a fin so that the thermal oxide layer is formed under the fin. A pad oxide layer(11) and a pad nitride layer(12) are formed on a bulk substrate(10). The pad nitride layer, the pad oxide layer and the substrate are etched to form a trench. The substrate protruded by formation of the trench is etched to form a fin(15). An insulation layer which is not oxidized in a thermal oxide process(18) is formed on the inner wall of the trench, made of a nitride layer(16). A thermal oxide layer(19) is formed in the substrate under the trench and in the substrate under the fin so as to isolate the fin from the substrate. A gate electrode covers the fin to fill the trench.

Description

핀 전계효과 트랜지스터의 제조방법{METHOD FOR MANUFACTURING A FIN FIELD EFFECT TRANSISTOR}Method of manufacturing a fin field effect transistor {METHOD FOR MANUFACTURING A FIN FIELD EFFECT TRANSISTOR}

도 1 내지 도 6은 본 발명의 바람직한 실시예에 따른 핀 전계효과 트랜지스터의 제조방법을 도시한 공정단면도.1 to 6 are process cross-sectional views showing a method for manufacturing a fin field effect transistor according to a preferred embodiment of the present invention.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

10 : 벌크 기판 11 : 패드 산화막10 bulk substrate 11 pad oxide film

12 : 패드 질화막 13 : 제1 트렌치12 pad nitride film 13 first trench

14 : 제2 트렌치 15 : 핀(fin)14: second trench 15: fin

16 : 질화막 17 : 전면식각공정16: nitride film 17: front etching process

18 : 열산화공정 19 : 열산화막18: thermal oxidation process 19: thermal oxide film

본 발명은 핀 전계효과 트랜지스터의 제조방법에 관한 것으로, 특히 20 내지 30 나노미터(nm)급 핀 전계효과 트랜지스터(FinFET; Fin-Field Effect Transistor)의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a fin field effect transistor, and more particularly to a method for manufacturing a fin field effect transistor (FinFET) of 20 to 30 nanometers (nm) class.

일반적으로 모스펫(MOSFET), 즉 금속-산화막-반도체 전계효과 트랜지스터는 고성능화와 고집적화의 일환으로 소자 크기의 축소화가 종래부터 진행되어오고 있다. 특히, 50 나노미터(nm) 이하의 극소 채널을 가지는 차세대 트랜지스터를 구현하기 위해서는 드레인 전압에 의해 채널의 전위가 영향을 받는 단채널 효과(short channel effect)를 효과적으로 억제하는 것이 필수적이다.In general, MOSFETs, that is, metal-oxide-semiconductor field effect transistors, have been conventionally reduced in device size as part of high performance and high integration. In particular, in order to implement a next-generation transistor having a microchannel of 50 nm or less, it is essential to effectively suppress a short channel effect in which the potential of the channel is affected by the drain voltage.

이에 따라, 최근에는 전계효과 트랜지스터(FET : Field Effect Transistor)의 게이트 전극 길이를 20 내지 30 나노미터 정도까지 축소하기 위해서 많은 연구가 진행되어 오고 있다. 그러나, 현재까지 발표된 연구 결과로는 상용 제품에 적용될 수준의 특성을 얻지는 못하고 있다. 이는 극히 짧아진 소오스 영역과 드레인 영역간의 거리에 의해 야기되는 단채널 효과를 효과적으로 억제하기 곤란한데서 연유한다.Accordingly, in recent years, much research has been conducted to reduce the gate electrode length of a field effect transistor (FET) to about 20 to 30 nanometers. However, the results of the research published so far do not achieve the level of characteristics applicable to commercial products. This is because it is difficult to effectively suppress the short channel effect caused by the distance between the extremely short source and drain regions.

따라서, 기존의 평면구조의 소자를 그대로 적용하는 것은 안정된 소자의 동작을 획득하는데 어려움이 있다. 이에, 기존의 평면구조를 대신하여 얇은 채널 양편에 게이트를 두어 채널 쪽의 전위를 효과적으로 조절할 수 있는 이중 게이트 전계효과 트랜지스터가 가장 유력한 차세대 소자의 후보로서 연구되고 있다. 이러한 노력의 일환의 하나가 바로 핀 전계효과 트랜지스터(FIN-FET)이다. 핀 전계효과 트랜지스터는 기존의 평면구조의 반도체 기술과 높은 호환성을 가지는 장점이 있다.Therefore, it is difficult to obtain an operation of a stable device to apply the device of the existing planar structure as it is. Accordingly, a double gate field effect transistor capable of effectively controlling the potential at the channel side by gates on both sides of the thin channel instead of the conventional planar structure has been studied as a candidate for the next most likely device. One such effort is the fin field effect transistor (FIN-FET). The fin field effect transistor has an advantage of having high compatibility with a conventional planar semiconductor technology.

일반적으로, 벌크 기판 상에 형성된 핀 전계효과 트랜지스터는 트랜지스터가 동작하지 않을때 드레인(또는, 소스)에서 기판으로 전자가 방출되는 현상이 발생한다. 따라서, 전력 소모가 클 뿐 아니라 동작속도가 느려지는 문제점이 있다. In general, a fin field effect transistor formed on a bulk substrate generates electrons from a drain (or source) to the substrate when the transistor is inoperative. Therefore, there is a problem that not only the power consumption is large but also the operation speed is slow.

이러한 문제점을 해결하기 위하여, 종래에는 기판과 트랜지스터 간의 절연을 제공하는 SOI(Silicon On Insulator) 기판 상에 핀 전계효과 트랜지스터를 형성하였다.In order to solve this problem, a fin field effect transistor is conventionally formed on a silicon on insulator (SOI) substrate that provides insulation between the substrate and the transistor.

그러나, SOI 기판 상에 반도체 소자를 형성하는 경우에는 여러가지 단점이 있다. 먼저, SOI 기판은 벌크 기판에 비해 3배 정도 비싼 단점이 있고, SOI 소자에서 문제가 되는 부유기판 효과와 기판으로의 열 방출문제 등이 있다. 또한, SOI 기판은 벌크 기판에 비해 결함 밀도가 높기 때문에 수율 등의 문제로 인하여 고집적을 요구하는 메모리 기술에는 부적합하다는 단점이 있다.However, there are various disadvantages when forming a semiconductor device on an SOI substrate. First, the SOI substrate has the disadvantage of being about three times more expensive than the bulk substrate, and the floating substrate effect that is a problem in the SOI device and the heat emission to the substrate. In addition, since the SOI substrate has a higher defect density than the bulk substrate, the SOI substrate has a disadvantage of being unsuitable for a memory technology requiring high integration due to problems such as yield.

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 고가의 SOI 기판을 사용하지 않고도 기판과 분리될 수 있는 핀 전계효과 트랜지스터의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a fin field effect transistor that can be separated from a substrate without using an expensive SOI substrate.

상기에서 설명한 목적을 달성하기 위한 일측면에 따른 본 발명은, 벌크 기판 상에 패드 산화막 및 패드 질화막을 형성하는 단계와, 상기 패드 질화막, 상기 패드 산화막 및 상기 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치 형성 으로 인해 돌출된 상기 기판을 식각하여 핀(fin)을 형성하는 단계와, 상기 트렌치의 내측벽에 열산화공정시 산화되지 않는 절연막을 형성하는 단계와, 상기 핀과 상기 기판이 분리되도록 상기 트렌치 저부의 상기 기판 및 상기 핀 저부의 상기 기판에 열산화막을 형성하는 단계와, 상기 트렌치가 매립되도록 상기 핀을 덮는 게이트 전극을 형성하는 단계를 포함하는 핀 전계효과 트랜지스터의 제조방법을 제공한다.According to an aspect of the present invention, a pad oxide film and a pad nitride film are formed on a bulk substrate, and the trench is formed by etching the pad nitride film, the pad oxide film, and the substrate. Forming a fin by etching the substrate protruding due to the trench formation, forming an insulating layer that is not oxidized during a thermal oxidation process on an inner wall of the trench, and separating the fin and the substrate. Forming a thermal oxide film on the substrate of the trench bottom and the substrate of the bottom of the fin, and forming a gate electrode covering the fin so that the trench is buried. do.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

실시예Example

도 1 내지 도 6은 본 발명의 바람직한 실시예에 따른 핀 전계효과 트랜지스터의 제조방법을 도시한 공정단면도이다. 여기서, 도 1 내지 도 6에 도시된 참조부호들 중 서로 동일한 참조부호는 동일한 기능을 수행하는 동일 요소이다. 1 to 6 are process cross-sectional views illustrating a method of manufacturing a fin field effect transistor according to a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 6 are the same elements performing the same function.

먼저, 도 1에 도시된 바와 같이, 소자분리막이 형성될 소자분리 영역(이하, 제1 영역이라 함; A)과 핀 전계효과 트랜지스터가 형성될 핀영역(이하, 제2 영역이라 함; B)으로 정의된 벌크 기판(10)을 제공한다.First, as shown in FIG. 1, an isolation region in which an isolation layer is to be formed (hereinafter referred to as a first region; A) and a fin region in which a fin field effect transistor is to be formed (hereinafter referred to as a second region; B) It provides a bulk substrate 10 defined by.

이어서, 기판(10) 상에 패드 산화막(11)을 형성한다. 이때, 패드 산화막(11)은 산화공정 또는 증착공정을 통해 형성할 수 있다. 여기서, 산화공정은 수증기와 같은 산화기체 내에서 기판을 대략 900 내지 1000℃의 온도에서 가열하는 습식산화방식으로 실시하거나, 순수한 산소를 산화기체로 사용하여 약 1200℃의 온도에서 가열하는 건식산화방식으로 실시한다.Subsequently, a pad oxide film 11 is formed on the substrate 10. In this case, the pad oxide film 11 may be formed through an oxidation process or a deposition process. Here, the oxidation process is performed by a wet oxidation method in which the substrate is heated at a temperature of approximately 900 to 1000 ° C. in an oxidizing gas such as water vapor, or a dry oxidation method in which pure oxygen is used as an oxidizing gas and heated at a temperature of about 1200 ° C. To be carried out.

이어서, 패드 산화막(11) 상에 패드 질화막(12)을 증착한다. 예컨대, 패드 질화막(12)은 플라즈마 화학기상증착법(PECVD : Plasma Enhanced Chemical Vapor Deposition) 또는 저압화학기상증착(LPCVD: Low Pressuer CVD) 방식을 통해 증착한다.Subsequently, a pad nitride film 12 is deposited on the pad oxide film 11. For example, the pad nitride layer 12 may be deposited by a plasma enhanced chemical vapor deposition (PECVD) or a low press CVD (LPCVD) method.

이어서, 도 2에 도시된 바와 같이, 패드 질화막(12), 패드 산화막(11) 및 기판(10)을 식각하여 제1 영역(A)에 제1 트렌치(13)를 형성하고, 제2영역(B)에는 제1 트렌치(13)보다 넓은 폭을 갖는 제2 트렌치(14)를 형성하여 제2 영역(B)에 핀(15)을 형성한다. 예컨대, 핀(15)을 형성하는 방법은 다음과 같다. Subsequently, as illustrated in FIG. 2, the pad nitride film 12, the pad oxide film 11, and the substrate 10 are etched to form a first trench 13 in the first region A, and the second region ( A second trench 14 having a width wider than that of the first trench 13 is formed in B) to form the fin 15 in the second region B. FIG. For example, the method of forming the fin 15 is as follows.

먼저, 패드 질화막(12) 상에 포토레지스트(미도시)를 도포한 후, 포토마스크(미도시)를 이용한 노광 및 현상공정을 실시하여 소정의 제1 포토레지스트 패턴(미도시)을 형성한다. 그리고, 제1 포토레지스트 패턴을 식각 마스크로 이용한 식각공정을 실시하여 제1 및 제2 영역(A, B)에 제1 트렌치(13)를 각각 형성한다. 이어서, 제1 트렌치(13)로 인해 돌출된 제2 영역(B)의 기판(10)을 식각하여 제2 트렌치(14)를 형성한다. 이로써, 제2 영역(B)에 핀(15)이 형성된다.First, a photoresist (not shown) is coated on the pad nitride film 12, and then a predetermined first photoresist pattern (not shown) is formed by performing an exposure and development process using a photomask (not shown). An etching process using the first photoresist pattern as an etching mask is performed to form first trenches 13 in the first and second regions A and B, respectively. Subsequently, the second trench 14 is formed by etching the substrate 10 of the second region B protruding from the first trench 13. As a result, the fin 15 is formed in the second region B. FIG.

이어서, 도 3에 도시된 바와 같이, 제1 및 제2 트렌치(13, 14; 도 2 참조)가 형성된 전체 구조 상부의 단차를 따라 질화막(16)을 증착한다. 질화막(16)은 후속으로 진행될 열산화공정시 핀(15)의 양측벽이 산화되는 것을 방지하기 위하여 증착된다.Next, as shown in FIG. 3, the nitride film 16 is deposited along the stepped portion of the entire structure in which the first and second trenches 13 and 14 (see FIG. 2) are formed. The nitride film 16 is deposited to prevent oxidation of both sidewalls of the fin 15 during the subsequent thermal oxidation process.

이어서, 도 4에 도시된 바와 같이, 전면식각공정(17, etch-back)을 실시하여 패드 질화막(12)의 상부로 노출된 질화막(16)을 식각하면서, 제1 및 제2 트렌치(13, 14; 도 2 참조) 저부의 기판(10)까지 식각한다. 이로써, 제1 및 제2 트렌치(13, 14)의 내측벽에 각각 질화막(16)이 형성된다.Subsequently, as illustrated in FIG. 4, the first and second trenches 13 and 13 may be etched by etching the nitride film 16 exposed to the upper portion of the pad nitride film 12 by performing an etch back. 14; see FIG. 2) to the substrate 10 of the bottom. As a result, nitride films 16 are formed on inner walls of the first and second trenches 13 and 14, respectively.

이어서, 도 5에 도시된 바와 같이, 열산화공정(18)을 실시하여 제1 및 제2 트렌치(13, 14; 도 2 참조) 저부에 노출된 기판(10) 및 핀(15) 저부의 기판(10)에 열산화막(19)을 형성한다. 이때, 핀(15)의 양측벽 및 상부에는 질화막(15) 및 패드 질화막(12)이 잔류하므로 열산화공정(18)시에 핀(15)의 양측벽 및 상부가 산화되는 것이 방지된다. 따라서, 핀(15) 저부의 기판(10)에만 열산화막(19)이 형성된다.Subsequently, as shown in FIG. 5, the substrate 10 exposed through the bottom of the first and second trenches 13 and 14 (see FIG. 2) and the bottom of the fin 15 are subjected to a thermal oxidation process 18. A thermal oxide film 19 is formed at 10. At this time, since the nitride film 15 and the pad nitride film 12 remain on both side walls and the upper portion of the fin 15, the both side walls and the upper portion of the fin 15 are prevented from being oxidized during the thermal oxidation process 18. Therefore, the thermal oxide film 19 is formed only on the substrate 10 at the bottom of the fin 15.

이어서, 도 6에 도시된 바와 같이, 습식식각공정을 실시하여 잔류하는 질화막(16), 패드 질화막(12) 및 패드 산화막(11)을 식각한다. 이로써, 열산화막(19) 상의 핀(15)이 그대로 노출된다.Next, as shown in FIG. 6, the wet etching process is performed to etch the remaining nitride film 16, the pad nitride film 12, and the pad oxide film 11. As a result, the fin 15 on the thermal oxide film 19 is exposed as it is.

이어서, 도면에 도시되지는 않았으나, 제1 트렌치(13, 도 2 참조)가 매립되는 소자분리막을 형성하고, 제2 트렌치(14, 도 2 참조)가 매립되도록 핀(15)을 덮는 게이트 전극을 형성한다.Subsequently, although not shown in the drawing, a gate electrode covering the fin 15 is formed to form an isolation layer in which the first trench 13 (see FIG. 2) is embedded and the second trench 14 (see FIG. 2) is embedded. Form.

이어서, 소스/드레인 이온주입 공정을 실시하여 게이트 전극의 양측으로 노출된 핀(15)에 소스/드레인을 형성한다. 이로써, 벌크 기판(10) 상에 핀 전계효과 트랜지스터가 완성된다.Next, a source / drain ion implantation process is performed to form source / drain in the fins 15 exposed to both sides of the gate electrode. This completes the fin field effect transistor on the bulk substrate 10.

즉, 본 발명의 바람직한 실시예에 따르면 핀이 형성된 벌크 기판에 열산화공정을 실시하여 핀 저부의 기판에만 열산화막을 형성함으로써, 열산화막을 통해 기판과 핀 전계효과 트랜지스터가 분리된다. 따라서, 고가의 SOI 기판을 사용하지 않 고 저가의 벌크 기판을 사용하여 기판과 핀 전계효과 트랜지스터를 서로 분리시킬 수 있게 된다. 이는, 반도체 소자의 제조비용을 감소시킬 뿐만 아니라 SOI 기판을 사용함에 따라 발생하는 여러가지 문제점을 해결할 수 있다.That is, according to a preferred embodiment of the present invention, by performing a thermal oxidation process on the bulk substrate on which the fin is formed to form a thermal oxide film only on the substrate of the bottom of the fin, the substrate and the fin field effect transistor are separated through the thermal oxide film. Therefore, it is possible to separate the substrate and the fin field effect transistor from each other by using an inexpensive bulk substrate without using an expensive SOI substrate. This not only reduces the manufacturing cost of the semiconductor device but also solves various problems caused by using the SOI substrate.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명에 의하면, 핀이 형성된 벌크 기판에 열산화공정을 실시하여 핀 저부의 기판에만 열산화막을 형성함으로써, 열산화막을 통해 기판과 핀 전계효과 트랜지스터가 분리된다. 따라서, 고가의 SOI 기판을 사용하지 않고 저가의 벌크 기판을 사용하여 기판과 핀 전계효과 트랜지스터를 서로 분리시킬 수 있게 된다. 이는, 반도체 소자의 제조비용을 감소시킬 뿐만 아니라 SOI 기판을 사용함에 따라 발생하는 여러가지 문제점을 해결할 수 있다.As described above, according to the present invention, by performing a thermal oxidation process on a bulk substrate on which fins are formed to form a thermal oxide film only on the substrate of the bottom of the fin, the substrate and the fin field effect transistor are separated through the thermal oxide film. Therefore, it is possible to separate the substrate and the fin field effect transistor from each other by using an inexpensive bulk substrate without using an expensive SOI substrate. This not only reduces the manufacturing cost of the semiconductor device but also solves various problems caused by using the SOI substrate.

Claims (2)

벌크 기판 상에 패드 산화막 및 패드 질화막을 형성하는 단계;Forming a pad oxide film and a pad nitride film on the bulk substrate; 상기 패드 질화막, 상기 패드 산화막 및 상기 기판을 식각하여 트렌치를 형성하는 단계;Etching the pad nitride film, the pad oxide film, and the substrate to form a trench; 상기 트렌치 형성으로 인해 돌출된 상기 기판을 식각하여 핀(fin)을 형성하는 단계;Etching the substrate protruding due to the trench formation to form a fin; 상기 트렌치의 내측벽에 열산화공정시 산화되지 않는 절연막을 형성하는 단계;Forming an insulating layer on an inner sidewall of the trench that is not oxidized during a thermal oxidation process; 상기 핀과 상기 기판이 분리되도록 상기 트렌치 저부의 상기 기판 및 상기 핀 저부의 상기 기판에 열산화막을 형성하는 단계; 및Forming a thermal oxide film on the substrate of the trench bottom and the substrate of the fin bottom such that the fin and the substrate are separated; And 상기 트렌치가 매립되도록 상기 핀을 덮는 게이트 전극을 형성하는 단계Forming a gate electrode covering the fin so that the trench is buried 를 포함하는 핀 전계효과 트랜지스터의 제조방법.Method of manufacturing a pin field effect transistor comprising a. 제 1 항에 있어서,The method of claim 1, 상기 절연막은 질화막으로 형성하는 핀 전계효과 트랜지스터의 제조방법.And the insulating film is formed of a nitride film.
KR1020050046582A 2005-06-01 2005-06-01 Method for manufacturing a fin field effect transistor KR20060124904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050046582A KR20060124904A (en) 2005-06-01 2005-06-01 Method for manufacturing a fin field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050046582A KR20060124904A (en) 2005-06-01 2005-06-01 Method for manufacturing a fin field effect transistor

Publications (1)

Publication Number Publication Date
KR20060124904A true KR20060124904A (en) 2006-12-06

Family

ID=37729382

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050046582A KR20060124904A (en) 2005-06-01 2005-06-01 Method for manufacturing a fin field effect transistor

Country Status (1)

Country Link
KR (1) KR20060124904A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683415A (en) * 2007-07-18 2012-09-19 英特尔公司 Isolated tri-gate transistor fabricated on bulk substrate
KR20140146874A (en) * 2013-06-18 2014-12-29 삼성전자주식회사 Semiconductor device and method for fabricating the same
US9276087B2 (en) 2013-05-10 2016-03-01 Samsung Electronics Co., Ltd. Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683415A (en) * 2007-07-18 2012-09-19 英特尔公司 Isolated tri-gate transistor fabricated on bulk substrate
US9276087B2 (en) 2013-05-10 2016-03-01 Samsung Electronics Co., Ltd. Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin
US9431522B2 (en) 2013-05-10 2016-08-30 Samsung Electronics Co., Ltd. Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin
KR20140146874A (en) * 2013-06-18 2014-12-29 삼성전자주식회사 Semiconductor device and method for fabricating the same

Similar Documents

Publication Publication Date Title
US7879659B2 (en) Methods of fabricating semiconductor devices including dual fin structures
KR100739653B1 (en) Fin field effect transistor and method for forming the same
US7285456B2 (en) Method of fabricating a fin field effect transistor having a plurality of protruding channels
KR100827656B1 (en) Transistor having recess channel structure and fin structure, semicoductor device employing the transistor, and method of frabication the semiconductor device
US7867856B2 (en) Method of manufacturing a semiconductor device having fin-field effect transistor
US7939436B2 (en) Method of fabricating a semiconductor device
US9627269B2 (en) Transistor and fabrication method thereof
KR100521377B1 (en) Method for forming fin field effect transistor
US10714469B2 (en) Electrostatic discharge protection structure
CN110783193B (en) Semiconductor structure and forming method thereof
KR100683490B1 (en) Method for manufacturing field effect transistor having vertical channel
US6661044B2 (en) Method of manufacturing MOSEFT and structure thereof
KR20060124904A (en) Method for manufacturing a fin field effect transistor
CN113838934B (en) Semiconductor structure and forming method thereof
KR20060130322A (en) Field effect transistor having vertical channel and method thereof
KR20070001456A (en) Method for manufacturing saddle type transistor
CN108630752B (en) Semiconductor structure and forming method thereof
KR100958809B1 (en) Method for manufacturing a semiconductor device
KR100713937B1 (en) Method of manufacturing semiconductor device with recess gate
KR100713938B1 (en) Method of manufacturing semiconductor device with recess gate
KR100979241B1 (en) Semiconductor device and method of manufacturing the same
KR100689674B1 (en) Method for fabricating of semiconductor device
KR100483564B1 (en) MOSFET and manufacturing method thereof
KR100753051B1 (en) Method for manufacturing saddle type fin transistor
KR0161121B1 (en) Method of forming semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination