KR20060105288A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20060105288A
KR20060105288A KR1020050027949A KR20050027949A KR20060105288A KR 20060105288 A KR20060105288 A KR 20060105288A KR 1020050027949 A KR1020050027949 A KR 1020050027949A KR 20050027949 A KR20050027949 A KR 20050027949A KR 20060105288 A KR20060105288 A KR 20060105288A
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active region
semiconductor device
forming
trench
gate line
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KR1020050027949A
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Korean (ko)
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박승표
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주식회사 하이닉스반도체
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Priority to KR1020050027949A priority Critical patent/KR20060105288A/en
Publication of KR20060105288A publication Critical patent/KR20060105288A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 포화전류를 증가시킬 수 있는 반도체 소자의 제조방법에 관한 것이다. 본 발명은, 반도체 기판 내에 액티브 영역을 한정하는 소자분리막을 형성하는 단계; 상기 액티브 영역 내에 트렌치를 형성하는 단계; 및 상기 트렌치를 포함한 기판 상에 게이트 라인을 형성하는 단계를 포함하며, 상기 액티브 영역과 게이트 라인 간의 접촉면적을 넓혀 포화전류값을 증가시키는 것을 특징으로 한다.The present invention relates to a method for manufacturing a semiconductor device that can increase the saturation current. The present invention provides a method for forming a semiconductor device, comprising: forming an isolation layer in a semiconductor substrate to define an active region; Forming a trench in the active region; And forming a gate line on the substrate including the trench, and increasing a contact area between the active region and the gate line to increase a saturation current value.

Description

반도체 소자의 제조방법{Method for manufacturing semiconductor device}Method for manufacturing semiconductor device

도 1은 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3 및 도 4는 도 2c 및 도 2d의 평면도.3 and 4 are plan views of FIGS. 2C and 2D.

도 5a 및 도 5b는 도 2c 및 도 2d의 액티브 영역의 단축을 자른 단면도. 5A and 5B are cross-sectional views taken along the short axis of the active region of FIGS. 2C and 2D;

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

20: 기판 21: 소자분리막20: substrate 21: device isolation film

22: 감광막 패턴 23: 트렌치22: photoresist pattern 23: trench

24: 게이트 산화막 25: 게이트 도전막24: gate oxide film 25: gate conductive film

26: 하드마스크막 27: 게이트 라인26: hard mask layer 27: gate line

28: 랜딩 플러그 폴리28: landing plug pulley

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는, 포화전류를 증가시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can increase the saturation current.

최근, 반도체 집적기술의 발전에 힘입어 디램과 같은 휘발성 반도체 메모리 소자는 수 기가비트 이상의 정보를 저장할 수 있을 정도로 대용화 됨과 아울러 회로 선폭도 0.12㎛ 이하로 미세화 되는 추세에 있다.Recently, due to the development of semiconductor integrated technology, volatile semiconductor memory devices such as DRAMs are large enough to store more than several gigabits of information and the circuit line width is also reduced to 0.12 μm or less.

도 1은 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도로서, 도시한 바와 같이, 반도체 기판(10) 내에 액티브 영역을 한정하는 소자분리막(11)을 형성하고, 상기 액티브 영역 상에 게이트 라인(12) 및 랜딩플러그 폴리(13)를 형성하였다.FIG. 1 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device. As shown in FIG. 1, an isolation layer 11 defining an active region is formed in a semiconductor substrate 10, and a gate line (eg, a gate line) is formed on the active region. 12) and landing plug poly 13 were formed.

그런데, 소자가 고 집적화 되면서 소자 크기가 축소됨에 따라, 기존의 평면형 액티브로는 액티브 영역과 게이트 라인의 충분한 접촉면적을 확보할 수 없게 되었다. 액티브 영역과 게이트 라인의 접촉면적이 작아지면 드레인 포화전류가 감소하여 리프레시 시간 감소 등의 소자특성이 악화되는 문제가 발생한다. However, as the size of the device decreases as the device is highly integrated, the existing planar active path cannot secure sufficient contact area between the active region and the gate line. If the contact area between the active region and the gate line is small, the drain saturation current decreases, which causes deterioration of device characteristics such as a reduction in refresh time.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 셀 트랜지스터의 포화전류를 증가시킬 수 있는 반도체 소자의 제조방법을 제공함에 있다. Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing the saturation current of a cell transistor.

상기 목적을 달성하기 위한 본 발명은, 반도체 기판 내에 액티브 영역을 한정하는 소자분리막을 형성하는 단계; 상기 액티브 영역 내에 트렌치를 형성하는 단계; 및 상기 트렌치를 포함한 기판 상에 게이트 라인을 형성하는 단계를 포함하며, 상기 액티브 영역과 게이트 라인 간의 접촉면적을 넓혀 포화전류값을 증가시키는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a device isolation film defining an active region in a semiconductor substrate; Forming a trench in the active region; And forming a gate line on the substrate including the trench, and increasing a contact area between the active region and the gate line to increase a saturation current value.

상기 트렌치는 100~1000A의 깊이로 형성한다.The trench is formed to a depth of 100 ~ 1000A.

(실시예)(Example)

이하, 첨부한 도면을 참고하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도로, 액티브 영역의 장축을 자른 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along a major axis of an active region.

도 2a를 참조하면, 반도체 기판(20) 내에 액티브 영역을 한정하는 소자분리막(21)을 형성한다. 그런 다음, 상기 액티브 영역 상에 감광막을 도포한 후, 노광 및 현상 공정을 거쳐 액티브 영역의 일부를 노출시키는 감광막 패턴(22)을 형성한다.Referring to FIG. 2A, an isolation layer 21 defining an active region is formed in the semiconductor substrate 20. Then, after the photoresist film is coated on the active region, a photoresist pattern 22 is formed to expose a portion of the active region through an exposure and development process.

도 2b를 참조하면, 상기 감광막 패턴(22)을 마스크로 이용하여 액티브 영역을 식각하여 트렌치(23)를 형성한다. 상기 트렌치(23)는 100~1000A의 깊이로 형성한다.Referring to FIG. 2B, the trench 23 is formed by etching the active region using the photoresist pattern 22 as a mask. The trench 23 is formed to a depth of 100 ~ 1000A.

도 2c를 참조하면, 상기 트렌치(23)를 포함한 기판 상에 게이트 산화막(24), 게이트 도전막(25) 및 하드마스크막(26)을 증착한다. 이어서, 상기 하드마스크막(26)을 CMP 하여 단차를 제거한 후, 상기 하드마스크막(26) 상에 게이트 영역을 한정하는 감광막 패턴(미도시)을 형성하고, 상기 감광막 패턴을 마스크로 상기 하드마스크막(26), 게이트 도전막(25) 및 게이트 산화막(24)을 식각하여 게이트 라인(27)을 형성한다. Referring to FIG. 2C, a gate oxide layer 24, a gate conductive layer 25, and a hard mask layer 26 are deposited on a substrate including the trench 23. Subsequently, after the CMP of the hard mask layer 26 is removed to form a step, a photoresist pattern (not shown) defining a gate region is formed on the hard mask layer 26, and the hard mask is formed using the photoresist pattern as a mask. The film 26, the gate conductive film 25, and the gate oxide film 24 are etched to form a gate line 27.

도 2d를 참조하면, 상기 게이트 라인(27) 사이를 매립하도록 폴리실리콘막을 증착한 후, 폴리실리콘막을 CMP하여 랜딩 플러그 폴리(28)를 형성한다.Referring to FIG. 2D, after the polysilicon film is deposited to fill the gate lines 27, the polysilicon film is CMP to form the landing plug poly 28.

도 3 및 도 4는 도 2c 및 도 2d의 평면도이고, 도 5a 및 도 5b는 도 2c 및 도 2d의 액티브 영역의 단축을 자른 단면도로서, 도면을 참조하면, 액티브 영역에 트렌치를 형성함으로써 액티브 영역과 게이트 라인의 접촉면적을 넓혀 포화전류값을 증가시킬 수 있다.3 and 4 are plan views of FIGS. 2C and 2D, and FIGS. 5A and 5B are cross-sectional views of the active region of FIGS. 2C and 2D. Referring to the drawings, an active region is formed by forming a trench in the active region. The saturation current value can be increased by increasing the contact area between the gate line and the gate line.

이후, 도시하지는 않았으나, 공지된 일련의 반도체 소자의 제조공정을 진행하여 반도체 소자의 제조를 완성한다.Subsequently, although not shown, a process of manufacturing a known series of semiconductor devices is performed to complete the manufacture of the semiconductor devices.

본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니고 이하의 특허청구의 범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변화될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not so limited and it is intended that the invention be limited without departing from the spirit or field of the invention as set forth in the following claims It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

이상에서와 같이 본 발명은, 액티브 영역을 리세스 시킴으로써 게이트 라인과 액티브 영역의 접촉면적을 늘려 셀 트랜지스터의 포화전류를 증가시킬 수 있다. 포화전류를 증가시킴으로써, 소자의 온/오프 특성 및 저전압하에서의 소자 구동 특성을 향상시킬 수 있다.As described above, the present invention can increase the saturation current of the cell transistor by increasing the contact area between the gate line and the active region by recessing the active region. By increasing the saturation current, it is possible to improve the on / off characteristics of the element and the element driving characteristic under low voltage.

Claims (2)

반도체 기판 내에 액티브 영역을 한정하는 소자분리막을 형성하는 단계;Forming a device isolation film defining an active region in the semiconductor substrate; 상기 액티브 영역 내에 트렌치를 형성하는 단계; 및Forming a trench in the active region; And 상기 트렌치를 포함한 기판 상에 게이트 라인을 형성하는 단계를 포함하며,Forming a gate line on the substrate including the trench, 상기 액티브 영역과 게이트 라인 간의 접촉면적을 넓혀 포화전류값을 증가시키는 것을 특징으로 하는 반도체 소자의 제조방법.And increasing the contact area between the active region and the gate line to increase the saturation current value. 제 1 항에 있어서, The method of claim 1, 상기 트렌치는 100~1000A의 깊이로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법. The trench is a method of manufacturing a semiconductor device, characterized in that formed in a depth of 100 ~ 1000A.
KR1020050027949A 2005-04-04 2005-04-04 Method for manufacturing semiconductor device KR20060105288A (en)

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