KR20060077939A - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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KR20060077939A
KR20060077939A KR1020040116575A KR20040116575A KR20060077939A KR 20060077939 A KR20060077939 A KR 20060077939A KR 1020040116575 A KR1020040116575 A KR 1020040116575A KR 20040116575 A KR20040116575 A KR 20040116575A KR 20060077939 A KR20060077939 A KR 20060077939A
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oxide film
ldd
spacer
gate pattern
semiconductor device
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KR100643915B1 (en
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차한섭
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 반도체 기판의 활성영역을 식각하여 SiGe 에피층을 성장시켜 그에 따른 스트레스를 채널 영역에 인가함으로써 채널에서의 캐리어 이동도 및 전류 안정성을 증가시키며, LDD 이온주입시 버퍼 산화막을 사용하여 LDD 이온주입이 채널영역으로 최대한 적게 유입되도록 하여 단채널 효과를 억제시키는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, wherein an active region of a semiconductor substrate is etched to grow a SiGe epi layer, thereby applying a stress to the channel region, thereby increasing carrier mobility and current stability in the channel, and LDD ions. The present invention relates to a technique of suppressing short channel effects by using a buffer oxide film to minimize LDD ion implantation into a channel region during implantation.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

도 1a 내지 도 1h는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들. 1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

< 도면의 주요 부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>

10 : 반도체 기판 20 : 소자 분리막10 semiconductor substrate 20 device isolation film

30 : 게이트 산화막 40 : 폴리 실리콘층30 gate oxide film 40 polysilicon layer

50 : 제 1 산화막 60 : 제 1 스페이서50: first oxide film 60: first spacer

70 : SiGe 에피층 80 : LDD 이온주입영역70: SiGe epi layer 80: LDD ion implantation region

90 : 제 2 스페이서 100 : 소스/드레인 이온주입영역 90: second spacer 100: source / drain ion implantation region

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 반도체 기판의 활성영역을 식각하여 SiGe 에피층을 성장시켜 그에 따른 스트레스를 채널 영역에 인가함으로써 채널에서의 캐리어 이동도 및 전류 안정성을 증가시키며, LDD 이온주입시 버퍼 산화막을 사용하여 LDD 이온주입이 채널영역으로 최대한 적게 유입되도록 하여 단채널 효과를 억제시키는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, wherein an active region of a semiconductor substrate is etched to grow a SiGe epi layer, thereby applying a stress to the channel region, thereby increasing carrier mobility and current stability in the channel, and LDD ions. The present invention relates to a method of suppressing short channel effects by allowing LDD ion implantation to flow into the channel region as little as possible by using a buffer oxide film during implantation.

종래 기술에 따른 반도체 소자의 제조 방법은 소자 분리막이 형성된 반도체 기판 상부에 게이트 산화막 및 게이트 폴리의 적층구조로 게이트 전극을 형성한다. 상기 게이트 전극 측벽에 산화막 스페이서를 형성하고 상기 산화막 스페이서를 마스크로 LDD 이온 주입을 수행한다. In the method of manufacturing a semiconductor device according to the related art, a gate electrode is formed in a stacked structure of a gate oxide film and a gate poly on a semiconductor substrate on which a device isolation film is formed. An oxide spacer is formed on the sidewalls of the gate electrode, and LDD ion implantation is performed using the oxide spacer as a mask.

다음에 상기 게이트 전극의 산화막 스페이서를 제거한 후 상기 게이트 전극을 포함한 반도체 기판 전면에 산화막 및 질화막을 형성한다. 상기 산화막 및 질화막을 식각하여 LDD 스페이서를 형성한다. 상기 LDD 스페이서를 마스크로 소스/드레인 이온주입공정을 수행한다. Next, after the oxide spacer of the gate electrode is removed, an oxide film and a nitride film are formed over the entire semiconductor substrate including the gate electrode. The oxide film and the nitride film are etched to form an LDD spacer. A source / drain ion implantation process is performed using the LDD spacer as a mask.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, LDD 이온 주입이 채널영역에 많이 유입됨으로써 캐리어 이동도가 감소하고 전류 안정성이 악화되며, 단채널 효과가 발생하는 문제점이 있다. In the method of manufacturing a semiconductor device according to the related art described above, since a large amount of LDD ion implantation flows into a channel region, carrier mobility decreases, current stability deteriorates, and a short channel effect occurs.

상기 문제점을 해결하기 위하여, 활성영역을 식각하여 SiGe 에피층을 성장시키면 SiGe층은 Si층 보다 격자상수가 크기 때문에 채널 영역에 물리적인 스트레스가 인가된다. 따라서, 채널에서의 캐리어 이동도를 증가시키며 이에 따라 전류 안정성이 증가되며, 소스 드레인 영역 내부에 SiGe 에피층이 존재하여 LDD 이온주입이 채널영역에 최소한으로 유입된 초고집적 소자가 형성되는 반도체 소자의 제조 방법을 제공하는 것을 그 목적으로 한다. In order to solve the above problem, when the SiGe epitaxial layer is grown by etching the active region, the SiGe layer has a larger lattice constant than the Si layer, so that physical stress is applied to the channel region. Therefore, the carrier mobility in the channel is increased and accordingly the current stability is increased, and the SiGe epitaxial layer is present inside the source drain region, thereby forming an ultra-high density device in which LDD ion implantation is minimally introduced into the channel region. It aims at providing the manufacturing method.

본 발명에 따른 반도체 소자의 제조 방법은Method for manufacturing a semiconductor device according to the present invention

소자 분리막이 형성된 반도체 기판의 상부에 게이트 산화막, 폴리 실리콘층 및 제 1 산화막 적층구조의 게이트 패턴을 형성하는 단계와,Forming a gate pattern of a gate oxide film, a polysilicon layer, and a first oxide film stacked structure on the semiconductor substrate on which the device isolation film is formed;

상기 게이트 패턴 측벽에 제 1 스페이서를 형성하는 단계와,Forming a first spacer on sidewalls of the gate pattern;

상기 제 1 스페이서 및 게이트 패턴을 마스크로 상기 반도체 기판의 활성 영역을 소정 깊이 식각하는 단계와,Etching an active region of the semiconductor substrate by a predetermined depth using the first spacer and the gate pattern as a mask;

상기 소정 깊이 식각된 활성영역에 SiGe 에피층을 형성하여 매립하는 단계와,Forming a buried SiGe epitaxial layer in the predetermined depth etched active region;

상기 SiGe 에피층의 표면에 LDD 이온 주입을 수행하는 단계와,Performing LDD ion implantation on a surface of the SiGe epi layer,

상기 제 1 산화막 및 제 1 스페이서를 제거하는 단계와,Removing the first oxide film and the first spacer;

상기 게이트 패턴 측벽에 제1 LDD 산화막, LDD 질화막 및 제 2 LDD 산화막 적층구조의 제 2 스페이서를 형성하는 단계와,Forming a second spacer having a first LDD oxide film, an LDD nitride film, and a second LDD oxide film stacked structure on the sidewall of the gate pattern;

상기 제 2 스페이서 및 게이트 패턴을 마스크로 소스/드레인 이온주입공정 및 열처리 공정을 순차적으로 수행하는 단계와,Sequentially performing a source / drain ion implantation process and a heat treatment process using the second spacer and the gate pattern as masks;

를 포함하는 것을 특징으로 한다. Characterized in that it comprises a.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 1a 내지 도 1h는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다. 1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 1a를 참조하면, 소자 분리막(20)이 형성된 반도체 기판(10)의 상부에 게 이트 산화막(30), 폴리 실리콘층(40) 및 제 1 산화막(50)의 적층구조를 형성하고, 제 1 산화막(50), 폴리 실리콘층(40) 및 게이트 산화막(30)을 식각하여 게이트 패턴을 형성한다.Referring to FIG. 1A, a stacked structure of the gate oxide film 30, the polysilicon layer 40, and the first oxide film 50 is formed on the semiconductor substrate 10 on which the device isolation film 20 is formed. The oxide film 50, the polysilicon layer 40, and the gate oxide film 30 are etched to form a gate pattern.

여기서, 제 1 산화막(50)은 CVD 산화막과 같은 TEOS막 또는 열산화막이며, 100 내지 500Å의 두께로 형성하는 것이 바람직하다. Here, the first oxide film 50 is a TEOS film or a thermal oxide film such as a CVD oxide film, and is preferably formed to a thickness of 100 to 500 kPa.

도 1b를 참조하면, 반도체 기판(10) 전면에 제 2 산화막을 형성하고, 상기 제 2 산화막을 식각하여 상기 게이트 패턴 측벽에 제 1 스페이서(60)를 형성한다. Referring to FIG. 1B, a second oxide layer is formed on the entire surface of the semiconductor substrate 10, and the second oxide layer is etched to form first spacers 60 on the sidewalls of the gate pattern.

여기서, 상기 제 2 산화막은 CVD 산화막인 열 산화막 또는 TEOS막이며, 100 내지 500Å의 두께로 형성하는 것이 바람직하다. Here, the second oxide film is a thermal oxide film or a TEOS film, which is a CVD oxide film, and is preferably formed to a thickness of 100 to 500 GPa.

도 1c를 참조하면, 제 1 스페이서(60) 및 게이트 패턴을 마스크로 반도체 기판(10)의 활성 영역을 소정 깊이 식각한다. 상기 식각되는 반도체 기판의 활성 영역은 50 내지 2000Å인 것이 바람직하다. Referring to FIG. 1C, the active region of the semiconductor substrate 10 is etched to a predetermined depth using the first spacer 60 and the gate pattern as a mask. The active region of the etched semiconductor substrate is preferably 50 to 2000 microns.

도 1d를 참조하면, 상기 소정 깊이 식각된 활성영역에 SiGe 에피층(70)을 형성하여 상기 식각된 활성영역을 매립한다. 여기서, SiGe 에피층(70)은 2000 내지 2500Å의 두께로 형성하여 상기 식각된 활성영역이 완전히 매립되도록 하는 것이 바람직하다. Referring to FIG. 1D, a SiGe epi layer 70 is formed in the active region etched to a predetermined depth to fill the etched active region. Here, the SiGe epi layer 70 is preferably formed to a thickness of 2000 to 2500 내지 so that the etched active region is completely filled.

도 1e를 참조하면, 상기 게이트 패턴 양측의 SiGe 에피층(70)에 LDD 이온 주입(80)을 수행한다. 이때, 제 1 스페이서(60)를 마스크로 LDD 이온 주입을 수행하여 이온 주입 영역이 채널영역과 소정 거리 이격되어 형성된다. Referring to FIG. 1E, LDD ion implantation 80 is performed on the SiGe epi layer 70 on both sides of the gate pattern. In this case, the LDD ion implantation is performed using the first spacer 60 as a mask to form the ion implantation region spaced apart from the channel region by a predetermined distance.

도 1f를 참조하면, 제 1 산화막(50) 및 제 1 스페이서(60)를 제거한다. Referring to FIG. 1F, the first oxide film 50 and the first spacer 60 are removed.

도 1g를 참조하면, 상기 게이트 패턴 및 소자 분리막(20)을 포함하는 전체 표면상부에 제 1 LDD 산화막, 제 1 LDD 질화막 및 제 2 LDD 산화막을 순차적으로 형성하고 식각하여 상기 게이트 패턴 측벽에 제 2 스페이서(90)를 형성한다. Referring to FIG. 1G, a first LDD oxide film, a first LDD nitride film, and a second LDD oxide film are sequentially formed and etched on an entire surface including the gate pattern and the device isolation layer 20 to etch a second layer on the sidewall of the gate pattern. The spacer 90 is formed.

도 1h를 참조하면, 제 2 스페이서(90) 및 게이트 패턴을 마스크로 소스/드레인 이온 주입(100)공정 및 열처리 공정을 순차적으로 수행한다. 이때, 소스/드레인 영역(100)은 SiGe 에피층(70)을 둘러싸도록 형성되는 것이 바람직하다. Referring to FIG. 1H, the source / drain ion implantation process 100 and the heat treatment process may be sequentially performed using the second spacer 90 and the gate pattern as a mask. In this case, the source / drain region 100 may be formed to surround the SiGe epi layer 70.

본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판의 활성영역을 식각하여 SiGe 에피층을 성장시켜 그에 따른 스트레스를 채널 영역에 인가함으로써 채널에서의 캐리어 이동도 및 전류 안정성을 증가시키며, LDD 이온주입시 버퍼 산화막을 사용하여 LDD 이온주입이 채널영역으로 최대한 적게 유입되도록 하여 단채널 효과를 억제되는 효과가 있다. The method of manufacturing a semiconductor device according to the present invention increases the carrier mobility and current stability in the channel by growing the SiGe epi layer by etching the active region of the semiconductor substrate and applying the stress to the channel region, and during LDD ion implantation. By using a buffer oxide film, the LDD ion implantation is introduced into the channel region as little as possible, thereby reducing the short channel effect.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

소자 분리막이 형성된 반도체 기판의 상부에 게이트 산화막, 폴리 실리콘층 및 제 1 산화막 적층구조의 게이트 패턴을 형성하는 단계;Forming a gate pattern of a gate oxide film, a polysilicon layer, and a first oxide film stacked structure on the semiconductor substrate on which the device isolation film is formed; 상기 게이트 패턴 측벽에 제 1 스페이서를 형성하는 단계;Forming a first spacer on sidewalls of the gate pattern; 상기 제 1 스페이서 및 게이트 패턴을 마스크로 상기 반도체 기판의 활성 영역을 소정 깊이 식각하는 단계;Etching an active region of the semiconductor substrate by a predetermined depth using the first spacer and the gate pattern as a mask; 상기 소정 깊이 식각된 활성영역에 SiGe 에피층을 형성하여 매립하는 단계; 상기 SiGe 에피층의 표면에 LDD 이온 주입을 수행하는 단계;Forming a buried SiGe epitaxial layer in the active region etched to a predetermined depth; Performing LDD ion implantation on a surface of the SiGe epi layer; 상기 제 1 산화막 및 제 1 스페이서를 제거하는 단계;Removing the first oxide film and the first spacer; 상기 게이트 패턴 측벽에 제1 LDD 산화막, LDD 질화막 및 제 2 LDD 산화막 적층구조의 제 2 스페이서를 형성하는 단계; 및Forming second spacers having a first LDD oxide film, an LDD nitride film, and a second LDD oxide film stacked structure on sidewalls of the gate pattern; And 상기 제 2 스페이서 및 게이트 패턴을 마스크로 소스/드레인 이온주입공정 및 열처리 공정을 순차적으로 수행하는 단계;Sequentially performing a source / drain ion implantation process and a heat treatment process using the second spacer and the gate pattern as a mask; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 제 1 산화막 및 제 2 산화막은 CVD 산화막과 같은 TEOS막 또는 열산화막이며, 100 내지 500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The first oxide film and the second oxide film are a TEOS film or a thermal oxide film such as a CVD oxide film, and are formed in a thickness of 100 to 500 GPa. 제 1 항에 있어서, The method of claim 1, 상기 식각되는 반도체 기판의 활성 영역은 50 내지 2000Å인 것을 특징으로 하는 반도체 소자의 제조 방법. The active region of the semiconductor substrate to be etched is a method of manufacturing a semiconductor device, characterized in that 50 to 2000Å. 제 1 항에 있어서, The method of claim 1, 상기 SiGe 에피층은 2000 내지 2500Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 제조 방법. The SiGe epitaxial layer is a semiconductor device manufacturing method, characterized in that the deposition to a thickness of 2000 to 2500Å.
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Publication number Priority date Publication date Assignee Title
KR100834740B1 (en) * 2006-11-03 2008-06-05 삼성전자주식회사 Methods of forming field effect transistors having silicon-germanium source and drain regions
KR101436129B1 (en) * 2006-09-28 2014-09-01 글로벌파운드리즈 인크. Stressed field effect transistor and method for its fabrication

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101436129B1 (en) * 2006-09-28 2014-09-01 글로벌파운드리즈 인크. Stressed field effect transistor and method for its fabrication
KR100834740B1 (en) * 2006-11-03 2008-06-05 삼성전자주식회사 Methods of forming field effect transistors having silicon-germanium source and drain regions

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