KR20060070769A - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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KR20060070769A
KR20060070769A KR1020040109371A KR20040109371A KR20060070769A KR 20060070769 A KR20060070769 A KR 20060070769A KR 1020040109371 A KR1020040109371 A KR 1020040109371A KR 20040109371 A KR20040109371 A KR 20040109371A KR 20060070769 A KR20060070769 A KR 20060070769A
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layer
forming
via hole
ruo
metal wiring
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KR101165217B1 (en
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표성규
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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Abstract

본 발명은, 하지 금속층을 노출시키는 비아 홀과 금속 배선 트렌치를 포함하는 다공성 절연막 패턴을 형성하는 단계; ALD 공정을 수행하여 상기 다공성 절연막 패턴의 전체 표면에 RuO2 층을 형성하는 단계; RF 플라즈마 처리 공정을 수행하여 상기 비아 홀 하부의 상기 RuO2 층을 제거하는 단계; 상기 다공성 절연막 패턴의 전체 표면 상부에 확산 장벽층을 형성하는 단계; 및 상기 비아 홀과 금속 배선 트렌치를 금속 매립층으로 매립하여 금속 배선을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법을 제공한다.The present invention includes forming a porous insulating pattern including a via hole and a metal wiring trench to expose a base metal layer; Performing an ALD process to form a RuO 2 layer on the entire surface of the porous insulation pattern; Performing an RF plasma treatment process to remove the RuO 2 layer under the via hole; Forming a diffusion barrier layer over the entire surface of the porous insulation pattern; And filling the via hole and the metal wiring trench with a metal buried layer to form metal wiring.

비아 홀, 다공성 절연막 패턴Via Hole, Porous Insulation Pattern

Description

반도체 소자의 금속 배선 형성 방법{METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE}METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE

도 1a 내지 도 1f 는 본 발명에 따른 금속 배선 형성 방법을 나타낸 단면도.1A to 1F are cross-sectional views illustrating a metal wiring forming method according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100: 절연층 100a: 하지 금속층100: insulating layer 100a: base metal layer

105, 115: 식각 정지층 110: 비아 홀105, 115: Etch stop layer 110: Via hole

120: 금속 배선 트렌치 125: 하드 마스크120: metal wiring trench 125: hard mask

130, 135: 다공성 절연층 140: RuO2 층130, 135 porous insulating layer 140 RuO 2 layer

150: 확산 장벽층 160: 금속 매립층150: diffusion barrier layer 160: metal buried layer

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 더욱 상세하게는, 금속 배선 간의 절연을 위해 사용되는 다공성 절연막 패턴의 기계적 강도를 보완하여 반도체 소자 제조 시의 안정성과 수율을 개선할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다. The present invention relates to a method of forming a metal wiring of a semiconductor device, and more particularly, to a semiconductor that can improve the stability and yield in manufacturing a semiconductor device by supplementing the mechanical strength of the porous insulating film pattern used for the insulation between the metal wiring A metal wiring formation method of an element.                         

반도체 소자에는 배선을 위한 다수의 금속층 및 이들 금속층 간의 절연을 위한 절연층이 형성되어 있다. 그런데, 반도체 소자의 고집적화·고성능화의 요청에 따라 금속층 간의 간격이 갈수록 좁아지게 되어, 고집적화에 적합하면서도 절연 성능이 뛰어난 절연층을 필요하게 되었다.In the semiconductor device, a plurality of metal layers for wiring and an insulating layer for insulation between these metal layers are formed. However, in response to requests for high integration and high performance of semiconductor devices, the gaps between metal layers become smaller and narrower, so that an insulation layer suitable for high integration and excellent in insulation performance is required.

금속 배선 절연층으로는 나노폼(Nanofoam)이나 나노글래스(Nanoglass) 등을 이용한 것이 있는데, 이들은 각각 폴리머(Polymer)나 글래스(Glass) 물질을 큐링(Curing)하는 과정에서 인위적으로 내부에 작은 기공들을 형성시키거나 테오스 입자(TEOS Particle) 끼리의 약한 결합을 형성시킨 후 용액을 급격히 빼내어 다공성 구조를 그대로 지탱하게 만드는 방법을 이용함으로써 만들어진다. 이렇게 다공성의 저유전 물질층을 이용하여 절연층을 형성하는 것은, 반도체 소자의 고집적화에 유리하기 때문이다.The metal wiring insulation layer may be made of nanofoam or nanoglass, which are each artificially filled with pores in the process of curing polymer or glass material. It can be made by forming a weak bond between the TEOS particles and then rapidly removing the solution to support the porous structure. The formation of the insulating layer using the porous low dielectric material layer is advantageous for high integration of the semiconductor device.

그러나, 이와 같이 다공성 저유전 물질층을 이용한 절연층은 구조적 강도가 취약하여 쉽게 파손될 수 있다는 문제점이 있다. 특히, 다마신 공정을 이용하여 금속 배선을 형성하는 경우, 금속 배선 트렌치를 형성한 후 다시 비아 홀을 형성하는 공정을 수행해야 하는데, 이 과정에서 안정성이 떨어져 반도체 소자 형성의 수율이 떨어지게 된다.However, the insulating layer using the porous low dielectric material layer as described above has a problem in that its structural strength is weak and easily broken. In particular, in the case of forming the metal interconnection using the damascene process, a process of forming the via hole again after forming the metal interconnection trench must be performed. In this process, the yield of the semiconductor device is lowered due to poor stability.

본 발명은, 상술한 종래기술의 문제점을 감안하여 이루어진 것으로, 다공성 절연막 패턴을 외부 충격으로부터 보호하여 절연용 다공성 절연막 패턴의 기계적 강도를 개선한 반도체 소자의 금속 배선 형성 방법을 제공하는 것을 목적으로 한 다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide a method for forming a metal wiring of a semiconductor device in which the porous insulating film pattern is protected from external impact and the mechanical strength of the insulating insulating film is improved. All.

상기 목적을 달성하기 위해, 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은, 하지 금속층을 노출시키는 비아 홀과 금속 배선 트렌치를 포함하는 다공성 절연막 패턴을 형성하는 단계; ALD 공정을 수행하여 상기 다공성 절연막 패턴의 전체 표면에 RuO2 층을 형성하는 단계; RF 플라즈마 처리 공정을 수행하여 상기 비아 홀 하부의 상기 RuO2 층을 제거하는 단계; 상기 다공성 절연막 패턴의 전체 표면 상부에 확산 장벽층을 형성하는 단계; 및 상기 비아 홀과 금속 배선 트렌치를 금속 매립층으로 매립하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the method for forming a metal wiring of the semiconductor device according to the present invention, forming a porous insulating film pattern including a via hole and a metal wiring trench to expose the underlying metal layer; Performing an ALD process to form a RuO 2 layer on the entire surface of the porous insulation pattern; Performing an RF plasma treatment process to remove the RuO 2 layer under the via hole; Forming a diffusion barrier layer over the entire surface of the porous insulation pattern; And filling the via hole and the metal wiring trench with a metal buried layer to form a metal wiring.

본 발명에 따르면, 다공성 절연막 패턴에 있어서 비아 홀과 금속 배선 트렌치의 측벽에 고강도의 나도 두께의 RuO2 층을 형성하는 방법을 통해 다공성 절연층의 기계적 강도가 약한 문제점을 보완할 수 있다. 이로써, 고성능 RuO2/Cu 반도체 배선을 형성할 수 있다.According to the present invention, a problem of weak mechanical strength of the porous insulating layer may be compensated through a method of forming a high-strength bare RuO 2 layer on the sidewalls of the via hole and the metal wiring trench in the porous insulating pattern. Thereby, a high performance RuO 2 / Cu semiconductor wiring can be formed.

이하, 도면을 참조하여 본 발명의 바람직한 실시형태에 대해 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described with reference to drawings.

도 1a 내지 도 1f 는 본 발명에 따른 금속 배선 형성 방법을 도시한 단면도들이다.1A to 1F are cross-sectional views illustrating a metal wiring forming method according to the present invention.

도 1a 를 참조하면, 하지 금속층(100a)을 포함하는 절연층(100) 위에 식각 장벽층(105)을 형성하고, 식각 장벽층(105) 위에는 다공성 절연층(130)을 형성한다. 다공성 절연층(130) 위에 다시 트렌치 레벨 식각 장벽층(135)을 형성한 다음, 트렌치 레벨 다공성 절연층(135)을 형성한다. 125 는 하드 마스크로서, 상술한 다층 구조에 비아 홀(110)과 금속 배선 트렌치(120)를 형성하는데 있어서의 마스크로서 사용된다. 비아 홀(100)과 금속 배선 트렌치(120)는 비아 퍼스트(Via First)법이나 트렌치 퍼스트(Trench First)법 등의 종래기술에 따라 형성하면 된다. 이로써, 다공성 절연층 패턴을 완성한다.Referring to FIG. 1A, an etch barrier layer 105 is formed on an insulating layer 100 including a base metal layer 100a, and a porous insulating layer 130 is formed on the etch barrier layer 105. After forming the trench level etching barrier layer 135 on the porous insulating layer 130, the trench level porous insulating layer 135 is formed. 125 is a hard mask, and is used as a mask for forming the via hole 110 and the metal wiring trench 120 in the above-described multilayer structure. The via hole 100 and the metal wiring trench 120 may be formed according to a conventional technique such as a via first method or a trench first method. This completes the porous insulating layer pattern.

다음으로, 도 1b 에 나타낸 바와 같이, RuO2 층(140)을 다마신 패턴의 전체 표면 상부에 형성하는 공정을 실시한다. 이 공정을 실시할 때에는, RuO2 층(140)이 지나치게 많은 부피를 차지할 경우 금속 배선층의 단면적이 적어져 저항이 증가하는 점을 감안하여, RuO2 층(140)의 두께를 나노 단위로 하는 것이 바람직하다. 이 경우, Bottom-up 방식의 원자층 성장법인 ALD(Atomic Layer Deposition)법을 이용한다면 보다 효과적으로 박형의 RuO2 층(140)을 형성할 수 있다. 이 RuO2 층(140)이 다공성 저유전 절연층(130)의 기계적 강도를 보완하는 역할을 수행하게 된다.Next, as shown in FIG. 1B, a process of forming the RuO 2 layer 140 on the entire surface of the damascene pattern is performed. In carrying out this step, considering that the RuO 2 layer 140 occupies an excessively large volume, the cross-sectional area of the metal wiring layer decreases and the resistance increases, so that the thickness of the RuO 2 layer 140 is in nano units. desirable. In this case, if the ALD (Atomic Layer Deposition) method of the bottom-up atomic layer growth method is used, the thin RuO 2 layer 140 can be formed more effectively. The RuO 2 layer 140 serves to complement the mechanical strength of the porous low dielectric insulating layer 130.

도 1c 를 참조하면, RF 플라즈마 처리 공정을 실시하여 비아 홀(110) 하부의 RuO2 층(140)을 제거한다. RuO2 층(140)을 형성하는 것은 다공성 저유전 절연층(130)의 기계적 강도를 증가시키기 위한 것이므로, 다공성 저유전 절연층(130)의 기계적 강도 개선과는 무관한 하지 금속층(100a)의 표면에 형성되어 있는 RuO2 층(140)을 제거한다. 여기서, RF 플라즈마 처리 공정으로 제거 공정을 실시하는 이유는, 종래 기술에서 수행되던 확산 장벽층 및 시드층의 증착 없이도 보이드와 같은 결함이 발생하지 않도록 직접 금속층을 형성하는 공정이 가능하기 때문이다.Referring to FIG. 1C, an RF plasma treatment process is performed to remove the RuO 2 layer 140 under the via hole 110. Since the RuO 2 layer 140 is formed to increase the mechanical strength of the porous low dielectric insulating layer 130, the surface of the underlying metal layer 100 a is not related to the improvement of the mechanical strength of the porous low dielectric insulating layer 130. Remove the RuO 2 layer 140 formed in the. The reason why the removal process is performed by the RF plasma treatment process is that the metal layer may be directly formed so that defects such as voids do not occur even without the deposition of the diffusion barrier layer and the seed layer.

다음으로, 도 1d 를 참조하면, 절연막 패턴의 전체 표면 상부에 확산 장벽층(150)을 형성하는 공정을 실시한다. 확산 장벽층(150)은 Ru 로 이루어진 구리 확산 장벽층일 수 있으나, 특별히 이에 한정되는 것은 아니다. 구리 확산 장벽층(150)의 경우, 상술한 ALD 법으로 형성하는 것이 바람직하다.Next, referring to FIG. 1D, a process of forming the diffusion barrier layer 150 on the entire surface of the insulating film pattern is performed. The diffusion barrier layer 150 may be a copper diffusion barrier layer made of Ru, but is not particularly limited thereto. In the case of the copper diffusion barrier layer 150, it is preferable to form by the ALD method mentioned above.

도 1e 및 도 1f 는 무전해 도금법 등의 전기 도금을 통해 비아 홀(110)과 금속 배선 트렌치(120)를 매립하는 공정과 과도 매립층 부분을 CMP 법으로 제거하는 공정을 각각 나타낸다. 무전해 도금법 등의 전기 도금으로 금속 매립층(160: 예를 들면, 구리층)을 형성한 후(도 1e 참조), 비아 홀(110)과 트렌치(120)가 형성되지 않은 영역에 도금된 과도 매립층 부분을 도 1f 와 같이 CMP 법으로 제거한다. 절연막 패턴의 상부면 상에 존재하는 RuO2 층과 확산 장벽층(150)도 CMP 공정을 실시하는 과정에서 같이 제거한다.1E and 1F illustrate a process of embedding the via hole 110 and the metal wiring trench 120 through electroplating such as an electroless plating method and a process of removing the excess buried layer portion by the CMP method, respectively. After forming the metal buried layer 160 (for example, copper layer) by electroplating such as electroless plating (see FIG. 1E), the transient buried layer plated in the region where the via hole 110 and the trench 120 are not formed. The part is removed by the CMP method as shown in FIG. 1F. The RuO 2 layer and the diffusion barrier layer 150 on the upper surface of the insulating film pattern are also removed during the CMP process.

이상 설명한 바와 같이, 본 발명에 따른 반도체 소자의 금속 배선 형성 방법에 의하면, 종래기술과는 달리, 나노두께의 고강도 RuO2 층(140)이 비아 홀(110)과 금속 배선 트렌치(120)의 측벽에 형성시킬 수 있다. 이 RuO2 층(140)에 의해 다공성 절연막 패턴을 기계적 충격으로부터 보호하여, 그 기계적 강도를 보완할 수 있다.As described above, according to the method for forming the metal wiring of the semiconductor device according to the present invention, unlike the prior art, the high-strength RuO 2 layer 140 having a nano-thickness has sidewalls of the via hole 110 and the metal wiring trench 120. Can be formed on. The RuO 2 layer 140 protects the porous insulating film pattern from mechanical impact and compensates for its mechanical strength.

본 발명에 따른 반도체 소자의 금속 배선 형성 방법에 의하면, 고강도의 나노두께의 RuO2 층에 의해 다공성 절연막 패턴을 외부 충격으로부터 보호하여 다공성 절연막 패턴의 기계적 강도를 개선할 수 있다.According to the method for forming a metal wiring of the semiconductor device according to the present invention, the porous insulating film pattern can be protected from external impact by the high-strength nano-thick RuO 2 layer to improve the mechanical strength of the porous insulating film pattern.

이로써, 반도체 소자 제조 시 안정성과 수율을 높일 수 있다. 특히, 고집적 반도체 소자의 저유전율 공정에 효과적으로 적용할 수 있다.As a result, stability and yield may be increased during fabrication of a semiconductor device. In particular, the present invention can be effectively applied to low dielectric constant processes of highly integrated semiconductor devices.

Claims (8)

하지 금속층을 노출시키는 비아 홀과 금속 배선 트렌치를 포함하는 다공성 절연막 패턴을 형성하는 단계;Forming a porous insulating pattern including a via hole and a metal wiring trench exposing the underlying metal layer; ALD 공정을 수행하여 상기 다공성 절연막 패턴의 전체 표면에 RuO2 층을 형성하는 단계;Performing an ALD process to form a RuO 2 layer on the entire surface of the porous insulation pattern; RF 플라즈마 처리 공정을 수행하여 상기 비아 홀 하부의 상기 RuO2 층을 제거하는 단계;Performing an RF plasma treatment process to remove the RuO 2 layer under the via hole; 상기 다공성 절연막 패턴의 전체 표면 상부에 확산 장벽층을 형성하는 단계; 및Forming a diffusion barrier layer over the entire surface of the porous insulation pattern; And 상기 비아 홀과 금속 배선 트렌치를 금속층으로 매립하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And filling the via hole and the metal wiring trench with a metal layer to form a metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 다공성 절연막 패턴을 형성한 후, 산화막 또는 질화막을 형성하여 상기 다공성 절연막 패턴을 실링(Sealing)하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming an oxide film or a nitride film to seal the porous insulating film pattern after forming the porous insulating film pattern. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 확산 장벽층은 ALD 공정으로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The diffusion barrier layer is formed by an ALD process. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 RuO2 층의 두께는 3Å 내지 100Å 인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The RuO 2 layer has a thickness of 3 kPa to 100 kPa. 제 1 항에 있어서,The method of claim 1, 상기 확산 장벽층은 Ru 층인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the diffusion barrier layer is a Ru layer. 제 5 항에 있어서,The method of claim 5, 상기 Ru 층의 두께는 5Å 내지 200Å 인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the thickness of the Ru layer is 5 kPa to 200 kPa. 제 1 항에 있어서,The method of claim 1, 상기 RF 플라즈마 처리 공정은 DFE(Dual Frequency Etch) 법으로 수행하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The RF plasma treatment process is a metal wire forming method of a semiconductor device, characterized in that performed by the DFE (Dual Frequency Etch) method. 제 1 항에 있어서,The method of claim 1, 상기 확산 장벽층을 형성한 후, 상기 확산 장벽층의 표면에 시드층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming a seed layer on the surface of the diffusion barrier layer after forming the diffusion barrier layer.
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