KR20060040859A - Method for manufacturing cell transistor in semiconductor device - Google Patents

Method for manufacturing cell transistor in semiconductor device Download PDF

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KR20060040859A
KR20060040859A KR1020040089701A KR20040089701A KR20060040859A KR 20060040859 A KR20060040859 A KR 20060040859A KR 1020040089701 A KR1020040089701 A KR 1020040089701A KR 20040089701 A KR20040089701 A KR 20040089701A KR 20060040859 A KR20060040859 A KR 20060040859A
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forming
insulating film
semiconductor substrate
gate
cell transistor
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임성혁
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 DRAM 패턴 미세화에 따른 패턴 불량 문제 및 숏 채널 효과를 개선하고, 누설전류 증가를 방지하는데 적합한 반도체 소자의 셀 트랜지스터 제조 방법을 제공하기 위한 것으로, 이를 위한 본 발명의 셀 트랜지스터 제조 방법은 반도체 기판 상에 게이트 패턴을 형성하는 단계; 상기 게이트 패턴의 측벽과 상기 게이트 패턴 사이의 반도체 기판이 산화되도록 열산화를 실시하는 단계; 상기 열산화에 의해 형성된 산화물을 제거하는 단계; 결과물의 전면에 스페이서 절연막을 형성하는 단계; 상기 반도체 기판 전면에 층간절연막을 형성하는 단계; 상기 층간절연막과 상기 스페이서 절연막을 식각하여 콘택홀을 형성하는 단계; 및 상기 콘택홀 내에 도전층을 형성하는 단계를 포함한다.
The present invention is to provide a cell transistor manufacturing method of a semiconductor device suitable for improving the pattern defect problem and short channel effect according to the DRAM pattern miniaturization, and to prevent leakage current increase, the cell transistor manufacturing method of the present invention for this Forming a gate pattern on the substrate; Thermally oxidizing the semiconductor substrate between the sidewall of the gate pattern and the gate pattern; Removing the oxide formed by the thermal oxidation; Forming a spacer insulating film on the entire surface of the resultant product; Forming an interlayer insulating film over the semiconductor substrate; Etching the interlayer insulating film and the spacer insulating film to form a contact hole; And forming a conductive layer in the contact hole.

Bird's Beak, 셀 트랜지스터, 랜딩 플러그Bird's Beak, Cell Transistor, Landing Plug

Description

반도체 소자의 셀 트랜지스터 제조 방법{METHOD FOR MANUFACTURING CELL TRANSISTOR IN SEMICONDUCTOR DEVICE} Method for manufacturing cell transistor of semiconductor device {METHOD FOR MANUFACTURING CELL TRANSISTOR IN SEMICONDUCTOR DEVICE}             

도 1a 내지 도 1e는 종래 기술에 따른 셀 트랜지스터 제조 방법을 도시한 공정 단면도,1A to 1E are cross-sectional views illustrating a method of manufacturing a cell transistor according to the prior art;

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 셀 트랜지스터 제조 방법을 도시한 공정 단면도.
2A to 2F are cross-sectional views illustrating a method of manufacturing a cell transistor of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 반도체 기판 32 : 소자분리막31 semiconductor substrate 32 device isolation film

33 : 게이트 산화막 34 : 폴리실리콘33: gate oxide film 34: polysilicon

35 : 텅스텐실리사이드 36 : 하드마스크질화막35 tungsten silicide 36 hard mask nitride film

37 : 열산화막 38 : 이온 주입37: thermal oxide 38: ion implantation

39 : LDD 영역 40 : 스페이서 질화막39: LDD region 40: spacer nitride film

41 : 버드빅 42 : 층간절연막41: Budvik 42: interlayer insulating film

43 : 콘택 플러그
43: contact plug

본 발명은 반도체 제조 기술에 관한 것으로, 특히 DRAM 셀 트랜지스터 제조 방법에 관한 것이다. TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a DRAM cell transistor.

잘 알려진 바와 같이, DRAM과 같은 반도체 소자의 고집적화가 진행됨에 따라, 미세 패턴을 형성하는 기술이 더욱더 중요해졌다. 따라서 리소그라피 해상도 마진 부족에 기인한 여러가지 문제점이 발생하고 있다. 특히 그 중 낮은 DICD(Develope Inspection Critical Demension; 이하 'DICD'라 칭함)에 기인한 패턴 붕괴 현상이 심각한 문제로 대두되고 있다. As is well known, as the integration of semiconductor devices, such as DRAM, proceeds, the technology of forming fine patterns becomes more and more important. Therefore, various problems are caused by lack of lithography resolution margin. In particular, the collapse of the pattern due to the low DECD (Develope Inspection Critical Demension) (hereinafter referred to as 'DICD') is a serious problem.

반도체 소자의 고집적화에 따라 각종 패턴이 미세화되고 있으며, 최근에는 0.15㎛ 선폭 이하까지 미세화가 진행되고 있다. 이에 따라, 통상적인 전극 형성시 사용되어 온 도핑된 폴리실리콘(doped polysilicon)은 그 자체의 높은 비저항 특성으로 인하여 지연 시간이 길어 빠른 동작을 요구하는 소자에 적용하기가 어려운 문제점이 있었다. 이러한 문제점은 반도체 장치의 고집적화에 따라 더욱 심각한 문제로 대두되고 있으며, 이를 개선하기 위하여 1기가 DRAM급 이상의 반도체 소자 제조시 전극 재료로서 비저항이 낮은 티타늄 실리사이드(TiSi), 텅스텐(W) 등의 적용이 유력시되고 있다. 그러나, 이와 같은 티타늄 실리사이드, 텅스텐 등을 사용하여 워드라인 전극을 형성할 경우 다음과 같은 근본적인 문제를 안고 있다. Various patterns are miniaturized with high integration of semiconductor devices, and in recent years, miniaturization has been progressed to 0.15 µm or less. Accordingly, doped polysilicon, which has been used in conventional electrode formation, has a problem that it is difficult to apply to a device requiring fast operation due to its long resistivity due to its high resistivity. This problem is becoming more serious due to the high integration of semiconductor devices, and to improve this problem, application of titanium silicide (TiSi), tungsten (W), etc., which have low resistivity, is an important electrode material for manufacturing semiconductor devices of more than 1 Gigabit DRAM. Being potent. However, when forming a word line electrode using such a titanium silicide, tungsten or the like has the following fundamental problems.

즉, 게이트 산화막(gate oxide) 위에 폴리실리콘 및 텅스텐을 증착하고, 워 드 라인 마스크를 이용하여 이들을 패터닝할 때 게이트 산화막의 열화가 발생하는데, 이를 보상하기 위하여 게이트 구조를 재산화(LDD oxidation) 시키게 된다. In other words, the deposition of polysilicon and tungsten on the gate oxide and patterning them using a word line mask causes deterioration of the gate oxide, which is required to reoxidize the gate structure to compensate for this. do.

따라서, 소자의 고집적화에 따라 디자인 룰(design rule)이 작아짐에 따라 사진 및 식각 공정의 마진(margin)을 확보하는 것이 매우 어려운 상황에 있어 양산시 수율 확보가 매우 어렵다.Therefore, as the design rule decreases due to the high integration of the device, it is very difficult to secure a margin of the photo and etching process, and thus it is very difficult to secure the yield in mass production.

도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자의 DRAM 셀 트랜지스터 제조 방법을 도시한 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a DRAM cell transistor of a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 국부적으로 소자분리막(12)을 형성한다. 소자분리막(12)은 LOCOS(Local Oxidation of Silicon) 또는 STI(Shallow Trench Isolation) 방식을 적용한다. As shown in FIG. 1A, a device isolation film 12 is locally formed on the semiconductor substrate 11. The device isolation layer 12 employs a local oxide of silicon (LOCOS) or shallow trench isolation (STI) method.

이어서, 반도체 기판(11) 상에 게이트 산화막(13), 폴리실리콘막(14), 텅스텐실리사이드(15) 및 하드마스크질화막(16)의 순서로 적층된 게이트 패턴을 형성한다. Subsequently, a gate pattern stacked in the order of the gate oxide film 13, the polysilicon film 14, the tungsten silicide 15, and the hard mask nitride film 16 is formed on the semiconductor substrate 11.

도 1b에 도시된 바와 같이, 다수의 게이트 패턴이 형성된 반도체 기판(11) 전체에 라이트 옥시데이션(Light Oxidation)을 진행한다. 라이트 옥시데이션은 게이트 패터닝 시 하부 게이트 산화막(13)의 측벽의 손실이 유발되는 것을 복원하고, 이온 주입시 완충 역할을 하기 위한 산화 공정이다. 라이트 옥시데이션은 N2 분위기의 900℃∼1000℃ 건식 산화(Dry oxidation)로 진행한다. 산화 공정을 마친 후, 소스/드레인 형성용 N- 이온 주입(17)을 진행한다. 이온 주입(17)후, N- 영역(18)이 형성된다. 라이트 옥시데이션 후, 게이트 전극 패턴의 양측면에 열공정에 의한 산화막(19)이 형성되고, 결국 쇼트 채널 이펙트(Short Channel Effect; SCE)를 증대시키는 문제가 있다. As shown in FIG. 1B, light oxidation is performed on the entire semiconductor substrate 11 on which the plurality of gate patterns are formed. The write oxidation is an oxidation process for restoring loss of sidewalls of the lower gate oxide layer 13 during gate patterning and for buffering during ion implantation. The light oxidization proceeds to 900 ° C. to 1000 ° C. dry oxidation in an N 2 atmosphere. After the oxidation process, the source / drain formation N-ion implantation 17 is performed. After ion implantation 17, an N-region 18 is formed. After the write oxidization, an oxide film 19 is formed on both sides of the gate electrode pattern by a thermal process, thereby increasing the short channel effect (SCE).

도 1c에 도시된 바와 같이, 게이트 전극 패턴을 포함한 반도체 기판(11) 전면에 스페이서 질화막(20)을 형성한다. 이 때 스페이서 질화막(20)은 쇼트 채널 이펙트 방지를 위해 500Å의 두꺼운 두께의 스페이서 질화막(20)을 두껍로 증착한다. 이후, 반도체 기판(11) 전면에 층간절연막(20)를 증착한다.As illustrated in FIG. 1C, a spacer nitride film 20 is formed on the entire surface of the semiconductor substrate 11 including the gate electrode pattern. At this time, the spacer nitride film 20 deposits a thick spacer nitride film 20 having a thickness of 500 kHz to prevent short channel effects. Thereafter, an interlayer insulating film 20 is deposited on the entire surface of the semiconductor substrate 11.

도 1d에 도시된 바와 같이, 랜딩 플러그 콘택(Landing Plug Contact)을 형성하기 위해 층간절연막(21)과 스페이서 질화막(20)을 식각하여 콘택홀을 형성한다.As illustrated in FIG. 1D, a contact hole is formed by etching the interlayer insulating layer 21 and the spacer nitride layer 20 to form a landing plug contact.

식각 공정 후, 게이트 패턴 측면에 사이드월(Side Wall)(19a)이 형성된다. 그러나, 계속되는 패턴 미세화에 의한 쇼트 채널 이펙트 즉, 고전계에 의한 핫 캐리어 이펙트(Hot Carrier Effect)를 제어하기에는 부족하다. After the etching process, a side wall 19a is formed on the side of the gate pattern. However, it is insufficient to control the short channel effect due to continuous pattern refinement, that is, the hot carrier effect due to the high field.

도 1e에 도시된 바와 같이, 랜딩 플러그 콘택을 형성하기 위한 마지막 공정으로 콘택홀 내부에 폴리실리콘(22)이 채워질 수 있도록 반도체 기판(11) 전면에 폴리실리콘(22)을 증착한다. 폴리실리콘(22)을 증착한 후, 화학적기계적연막(CMP)를 진행하여, 랜딩 플러그를 형성한다.As shown in FIG. 1E, polysilicon 22 is deposited on the entire surface of the semiconductor substrate 11 so that the polysilicon 22 may be filled in the contact hole as a final process for forming the landing plug contact. After depositing the polysilicon 22, a chemical mechanical smoke film (CMP) is performed to form a landing plug.

기존 공정을 통해서, 게이트 패턴이 미세화됨에 따라 패터닝에 따른 붕괴 현상 및 여러 문제점이 드러난다. 또한 측면 확산이 심화되어 쇼트 채널 이펙트를 쉽게 유발하고, 쇼트 채널 이펙트가 심화될수록 게이트유도드레인누설(Gate Induced Drain Leakage)이 증가하고 쇼트 채널 이펙트의 하나인 Bvmin(Snap Back BV) 특성 저하, 리프레시 시간(tREF) 감소와 같은 문제점이 발생한다.Through the existing process, as the gate pattern is miniaturized, a collapse phenomenon and various problems due to patterning are revealed. In addition, deep side diffusion deepens the short channel effect, and as the short channel effect deepens, gate induced drain leakage increases, and Bv min (Snap Back BV), which is one of the short channel effects, is refreshed. Problems such as reducing the time tREF occur.

상술한 것처럼, 종래 기술에서 하이 테크놀로지 DRAM 에서는 패턴 미세화로 인한 게이트 디파인이 불량하고, Nano Tech로 가면서, KrF 광원 대신 ArF를 광원으로 사용하기 위한 고가의 노광 장비의 구매 부담이 발생한다. 또한 쇼트 채널 이펙트가 발생하여 Snap Back Bv의 이펙티브 채널(Effective Channel) 감소로 인한 LDD 영역의 역할이 증대되나, 한정된 공간내에서 후속 열공정에 의한 측면 확산 및 이온 주입량 증가에 의한 전계가 가속화되고, 핫 캐리어 이펙트에 의한 누설이 증가한다. 그리고 위와 같은 문제점들로 인해 셀 데이타 유지 시간이 감소하는 문제가 발생한다.
As described above, in the high technology DRAM in the prior art, the gate fine due to the pattern miniaturization is poor, and as the Nano Tech goes, the burden of purchasing expensive exposure equipment for using ArF as a light source instead of KrF light source is generated. In addition, the short channel effect occurs to increase the role of the LDD region due to the reduction of the effective channel of the Snap Back Bv, but the electric field is accelerated by the lateral diffusion and the ion implantation amount by the subsequent thermal process in a limited space. The leakage caused by the hot carrier effect increases. As a result of the above problems, the cell data retention time is reduced.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, DRAM 패턴 미세화에 따른 패턴 불량 문제 및 숏 채널 효과를 개선하고, 누설전류 증가를 방지하는데 적합한 반도체 소자의 DRAM 셀 트랜지스터 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and provides a DRAM cell transistor manufacturing method of a semiconductor device suitable for improving the pattern defect problem and short channel effect caused by the DRAM pattern miniaturization and preventing leakage current increase. Its purpose is to.

상기 목적을 달성하기 위한 본 발명의 셀 트랜지스터 제조 방법은 반도체 기 판 상에 게이트 패턴을 형성하는 단계, 상기 게이트 패턴의 측벽과 상기 게이트 패턴 사이의 반도체 기판이 산화되도록 열산화를 실시하는 단계. 상기 열산화에 의해 형성된 산화물을 제거하는 단계, 결과물의 전면에 스페이서 절연막을 형성하는 단계, 상기 반도체 기판 전면에 층간절연막을 형성하는 단계, 상기 층간절연막과 상기 스페이서 절연막을 식각하여 콘택홀을 형성하는 단계; 및 상기 콘택홀 내에 도전층을 형성하는 단계를 포함한다.
According to another aspect of the present invention, there is provided a method of fabricating a cell transistor, the method including: forming a gate pattern on a semiconductor substrate, and performing thermal oxidation to oxidize a semiconductor substrate between the sidewall of the gate pattern and the gate pattern. Removing the oxide formed by the thermal oxidation, forming a spacer insulating film on the entire surface of the resultant, forming an interlayer insulating film on the entire surface of the semiconductor substrate, and forming a contact hole by etching the interlayer insulating film and the spacer insulating film. step; And forming a conductive layer in the contact hole.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2f는 본 발명의 일실시예에 따른 셀 트랜지스터 제조 방법을 도시한 공정 단면도이다.2A through 2F are cross-sectional views illustrating a method of manufacturing a cell transistor according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(31) 상에 국부적으로 소자분리막(32)을 형성한다. 소자분리막(32)은 LOCOS(Local Oxidation of Silicon) 또는 STI(Shallow Trench Isolation) 방식을 적용한다.As shown in FIG. 2A, a device isolation film 32 is locally formed on the semiconductor substrate 31. The device isolation layer 32 employs a local oxide of silicon (LOCOS) or shallow trench isolation (STI) method.

이어서 반도체 기판(31) 상에 게이트 산화막(33), 폴리실리콘막(34), 텅스텐실리사이드(35) 및 하드마스크질화막(36)이 순서로 적층된 게이트 패턴을 형성한다. 이 때, 종래보다 상대적으로 큰 CD를 갖도록 게이트 패턴을 형성한다. 이에 의해 패턴 쓰러짐 등 패턴 불량을 해결할 수 있다.Subsequently, a gate pattern in which the gate oxide film 33, the polysilicon film 34, the tungsten silicide 35, and the hard mask nitride film 36 are sequentially stacked is formed on the semiconductor substrate 31. At this time, the gate pattern is formed to have a relatively larger CD than in the prior art. As a result, pattern defects such as pattern collapse can be solved.

도 2b에 도시된 바와 같이, 다수의 게이트 패턴이 형성된 반도체 기판(31) 전체에 라이트 옥시데이션(Light Oxidation)을 진행한다. 라이트 옥시데이션은 게이트 전극 패터닝 시 하부 게이트 산화막(33)의 측벽의 손실이 유발되어 이 손실을 복원하고, 이온 주입시 완충 역할을 하기 위한 산화 공정이지만, 본 발명의 라이트 옥시데이션은 게이트 하부로의 충분한 버드빅을 형성하기 위해 스팀(Steam) 분위기의 1000℃∼1100℃의 조건에서 진행한다. 즉, 파이널 게이트 CD를 고려하여 패터닝된 게이트 길이와 게이트 하부로의 버드빅(bird's Beak; 산화정도)을 결정한다. 라이트 옥시데이션을 진행하는 동안 버드빅을 갖는 열산화막(37)이 형성된다.As shown in FIG. 2B, light oxidation is performed on the entire semiconductor substrate 31 on which the plurality of gate patterns are formed. The light oxidation is an oxidation process for restoring the loss of the sidewall of the lower gate oxide layer 33 during the gate electrode patterning and restoring the loss, and for buffering the ion implantation. In order to form sufficient Budvik, it proceeds in 1000 degreeC-1100 degreeC conditions of a steam atmosphere. That is, the final gate CD is considered and the patterned gate length and bird's beak (degree of oxidation) below the gate are determined. During the light oxidization process, a thermal oxide film 37 having Budvik is formed.

이어서, 도 2c에 도시된 바와 같이, 라이트 옥시데이션을 진행하는 동안 형성된 열산화막(37)을 제거하기 위해 습식 식각(Wet etch) 공정을 진행하고 LDD 이온 주입(38)을 진행하여 LDD 영역(39)을 형성한다. 이 때, 하드마스크질화막(36)을 제외한 텅스텐실리사이드(35) /폴리실리콘막(34)의 측면 손실이 발생한다. 소스/드레인 형성을 위한 N- 이온 주입 공정시 완충 역할을 하기 위해 약간의 열산화막(37)을 잔존시켜도 무방하다. Subsequently, as shown in FIG. 2C, a wet etch process and a LDD ion implantation 38 are performed to remove the thermal oxide film 37 formed during the light oxidization process. ). At this time, side loss of the tungsten silicide 35 / polysilicon film 34 except for the hard mask nitride film 36 occurs. Some thermal oxide film 37 may be left to act as a buffer during the N-ion implantation process for source / drain formation.

또한, 옥시데이션에 의해 반도체 기판(31)의 손실이 발생된 상태이기 때문에 N- 이온 주입시 에너지는 20keV 이하의 값을 갖고, 게이트 폭도 커져있는 상태에서 이온 주입을 진행하기 때문에, N- 이온 주입 마진은 증가하고, 측면 확산에 기인한 열화에 대한 면역(immunity)이 증가한다.In addition, since the loss of the semiconductor substrate 31 is caused by oxidization, the energy during N-ion implantation has a value of 20 keV or less, and the ion implantation proceeds in a state where the gate width is large, so that N-ion implantation is performed. Margins increase, and immunity to degradation due to lateral diffusion increases.

이어서, 도 2d에 도시된 바와 같이, 게이트 전극 패턴을 포함하는 반도체 기판(31) 전면에 400Å의 두께를 갖는 스페이서 질화막(40)을 증착한다. 게이트 전극 상부의 탑 질화막(36)은 옥시데이션시 손실이 발생한 텅스텐실리사이드(35)/폴리실 리콘막(34)과는 다르게 원상태를 유지하고 있기 때문에, 즉 자기정렬콘택(SAC) 페일(fail)에 취약한 숄더부 하드마스크질화막(36)의 두께가 결과적으로는 동일하게 진행할 수 있기 때문에 이펙티브 채널은 종래 기술과 동일하지만 게이트 폭은 종래 기술보다 크게 형성되기 때문에 얇게 증착 가능하다. 증착된 스페이서 질화막(40)은 이전 옥시데이션 진행시 형성된 게이트 하부의 버드빅(41) 부분까지 얇게 형성된다. Subsequently, as shown in FIG. 2D, a spacer nitride film 40 having a thickness of 400 μm is deposited on the entire surface of the semiconductor substrate 31 including the gate electrode pattern. Since the top nitride film 36 on the gate electrode maintains its original state differently from the tungsten silicide 35 / polysilicon film 34, which is lost during oxidization, that is, the self alignment contact (SAC) fails. Since the thickness of the shoulder portion hard mask nitride film 36, which is vulnerable to the same, can proceed in the same manner, the effective channel is the same as in the prior art, but the gate width is formed larger than in the prior art, so that the thin film can be deposited. The deposited spacer nitride layer 40 is thinly formed to the portion of Budvik 41 under the gate formed during the previous oxidization process.

이어서, 도 2e에 도시된 바와 같이, 층간절연막(42)을 증착한 후, 랜딩 플러그 콘택(Landing Plug Contact)을 형성하기 위해 층간절연막(42)과 스페이서 질화막(40)을 식각하여 콘택홀을 형성한다. Subsequently, as shown in FIG. 2E, after the interlayer dielectric layer 42 is deposited, the interlayer dielectric layer 42 and the spacer nitride layer 40 are etched to form a landing plug contact to form a contact hole. do.

이 때, 옥시데이션에 의해 형성된 랜딩 플러그 콘택의 바텀 부분은 라운드 형태를 계속 유지하고, 식각 후에도 반도체 기판(31) 측벽에 얇은 사이드월(38a)이 존재하도록 진행한다. 사이드월(38a)은 반도체 기판(31)까지 형성되어 있으므로 쇼트 채널 이펙트에 의한 HC 열화(전계 감소) 방지가 가능하다. 그리고, 사이드월(38a)이 만들어지면서 버드빅(41)은 더 정교한 형태를 갖게 된다. At this time, the bottom portion of the landing plug contact formed by the oxidization remains round, and the thin sidewall 38a is present on the sidewall of the semiconductor substrate 31 even after etching. Since the sidewall 38a is formed up to the semiconductor substrate 31, it is possible to prevent HC deterioration (electric field reduction) due to the short channel effect. Then, as the sidewall 38a is made, the budbig 41 has a more elaborate shape.

이어서, 도 2f에 도시된 바와 같이, 콘택홀 내부와 게이트 하부의 버드빅(41) 부분까지 모두 갭필(Gap Fill)되도록 폴리실리콘을 증착한다. 증착 공정 후, 화학적기계적연막(CMP)를 진행하고, 랜딩 플러그(43)를 형성한다. 이 때, 과도한 옥시데이션으로 인한 반도체 기판(31)이 라운드 형태를 띄므로 콘택 면적 확보가 가능하다.Subsequently, as shown in FIG. 2F, polysilicon is deposited so as to gap fill both the inside of the contact hole and the portion of Budvik 41 under the gate. After the deposition process, a chemical mechanical smoke film (CMP) is performed to form a landing plug 43. At this time, since the semiconductor substrate 31 due to excessive oxidation has a round shape, it is possible to secure a contact area.

본 발명과 같이 DRAM 셀 트랜지스터를 형성하면, 게이트 패턴 마진을 확보 할 수 있다. 버드빅으로 인한 이펙티브 패널 길이 감소를 고려하여 종래 타깃 대비 20%∼30% 정도의 게이트 폭을 증가시켜 패터닝하는 것이 가능하다. 이 때, 게이트 폭은 진행 장비와 제품에 따라 임의 조절 가능한 사항이다.If the DRAM cell transistor is formed as in the present invention, the gate pattern margin can be secured. In consideration of reducing the effective panel length due to Budvik, it is possible to pattern by increasing the gate width by about 20% to 30% compared to the conventional target. At this time, the gate width can be arbitrarily adjusted according to the equipment and the product.

또한 게이트 폭이 종래 대비 20%∼30% 증가한 상태에서 소스/드레인을 형성하는 이온 주입을 진행하므로 후속 열공정에 쇼트 채널 이펙트를 유발하는 측면 확산 제어가 가능하므로 이온 주입 마진이 향상 가능하다.In addition, since the ion implantation is performed to form the source / drain while the gate width is increased by 20% to 30%, the side diffusion control that causes the short channel effect is performed in the subsequent thermal process, thereby improving the ion implantation margin.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 셀 트랜지스터의 산화 공정에서 버드빅을 이용하여 게이트 길이를 증가시켜 패터닝하는 것이 가능하므로, 광원 교체가 불필요한 효과가 있다. The present invention described above can be patterned by increasing the gate length by using Budvik in the oxidation process of the cell transistor, so there is no need to replace the light source.

또한, 후속 열공정에 의한 측면 확산 제어가 가능하므로 이온 주입 마진이 향상 가능하고, 자기정렬콘택에 대한 숄더 마진이 없으므로, 사이드월 질화막을 얇게 증착해도 LDD 역할을 충분히 할 수 있다. In addition, since side diffusion control by a subsequent thermal process is possible, an ion implantation margin can be improved, and since there is no shoulder margin for self-aligned contact, a thin film of the sidewall nitride film can serve as an LDD sufficiently.

마지막으로, 사이드월 질화막을 채널 양단에까지 미치도록 형성하여 쇼트 채널하에서 전계 증가를 억제하고, 게이트유도드레인누설을 개선하므로써 쇼트 채널 이펙트를 감소시켜 소자의 리프레시 특성을 향상시킬 수 있는 효과가 있다.Finally, the sidewall nitride film is formed to extend to both ends of the channel, thereby suppressing the increase of the electric field under the short channel and reducing the short channel effect by improving the gate induced drain leakage, thereby improving the refresh characteristics of the device.

Claims (4)

반도체 기판 상에 게이트 패턴을 형성하는 단계;Forming a gate pattern on the semiconductor substrate; 상기 게이트 패턴의 측벽과 상기 게이트 패턴 사이의 반도체 기판이 산화되도록 열산화를 실시하는 단계;Thermally oxidizing the semiconductor substrate between the sidewall of the gate pattern and the gate pattern; 상기 열산화에 의해 형성된 산화물을 제거하는 단계;Removing the oxide formed by the thermal oxidation; 결과물의 전면에 스페이서 절연막을 형성하는 단계;Forming a spacer insulating film on the entire surface of the resultant product; 상기 반도체 기판 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film over the semiconductor substrate; 상기 층간절연막과 상기 스페이서 절연막을 식각하여 콘택홀을 형성하는 단계; 및Etching the interlayer insulating film and the spacer insulating film to form a contact hole; And 상기 콘택홀 내에 도전층을 형성하는 단계Forming a conductive layer in the contact hole 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1항에 있어서,The method of claim 1, 상기 열산화에 의해 형성된 산화물은 상기 게이트 패턴 측벽 하부에 침투하는 버드빅을 갖는 반도체 소자 제조 방법.And oxides formed by the thermal oxidation penetrate under the gate pattern sidewalls. 제 2항에 있어서,The method of claim 2, 상기 열산화는 스팀분위기의 1000℃∼1100℃의 온도로 진행하는 반도체 소자 제조 방법.The thermal oxidation is a semiconductor device manufacturing method that proceeds to a temperature of 1000 ℃ to 1100 ℃ in the steam atmosphere. 제 1항에 있어서,The method of claim 1, 상기 산화물은 습식 식각으로 제거되는 반도체 소자 제조 방법.The oxide is a method of manufacturing a semiconductor device is removed by wet etching.
KR1020040089701A 2004-11-05 2004-11-05 Method for manufacturing cell transistor in semiconductor device KR20060040859A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611667A (en) * 2021-07-02 2021-11-05 芯盟科技有限公司 Transistor array and manufacturing method thereof, semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611667A (en) * 2021-07-02 2021-11-05 芯盟科技有限公司 Transistor array and manufacturing method thereof, semiconductor device and manufacturing method thereof

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