KR20060038241A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20060038241A
KR20060038241A KR1020040087463A KR20040087463A KR20060038241A KR 20060038241 A KR20060038241 A KR 20060038241A KR 1020040087463 A KR1020040087463 A KR 1020040087463A KR 20040087463 A KR20040087463 A KR 20040087463A KR 20060038241 A KR20060038241 A KR 20060038241A
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South Korea
Prior art keywords
gate insulating
insulating film
semiconductor device
forming
trench
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KR1020040087463A
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Korean (ko)
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이안배
김형균
은용석
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주식회사 하이닉스반도체
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Priority to KR1020040087463A priority Critical patent/KR20060038241A/en
Publication of KR20060038241A publication Critical patent/KR20060038241A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate

Abstract

본 발명은 리세스 게이트 형성시 트렌치의 측면과 실질적으로 동일한 두께의 게이트절연막을 형성하는데 적합한 반도체 소자 제조 방법을 제공하기 위한 것으로, 이를 위한 본 발명의 반도체 소자 제조 방법은 반도체 기판에 트렌치를 형성하는 단계; 상기 트렌치의 측벽과 밑면에서 동일한 산화속도 조건으로 게이트절연막을 형성하는 단계; 및 상기 게이트절연막 상에 게이트전극을 형성하는 단계를 포함한다.
The present invention is to provide a method for manufacturing a semiconductor device suitable for forming a gate insulating film having a thickness substantially the same as the side of the trench when forming the recess gate, the method for manufacturing a semiconductor device of the present invention for forming a trench in a semiconductor substrate step; Forming a gate insulating film on the sidewall and the bottom of the trench under the same oxidation rate condition; And forming a gate electrode on the gate insulating film.

리세스 게이트, 라디컬 산화, 플라즈마 산화Recessed gate, radical oxidation, plasma oxidation

Description

반도체 소자 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE} Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}             

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자 제조 방법을 도시한 공정 단면도,1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 반도체 소자 제조 방법을 도시한 공정 단면도.
2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 실리콘기판 22 : 트렌치21: silicon substrate 22: trench

23 : 게이트절연막 24 : 트렌치모서리23: gate insulating film 24: trench corner

25 : 폴리실리콘 26 : 금속물25 polysilicon 26 metal

27 : 폴리심(seam) 28 : 메탈보이드
27: poly seam 28: metal void

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 리세스 게 이트 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing recess gates for semiconductor devices.

잘 알려진 바와 같이, DRAM 소자의 슈링크(shrink)가 계속 진행되면서, 소스/드레인과 게이트 채널(gate channel)간의 전계(electric field)의 상승으로 리프레시(refresh) 특성 저하가 발생하며 이를 개선하기 위하여 게이트 채널과 소스/드레인 간의 거리를 멀리하여 전계를 줄이는 리세스 게이트를 사용하고 있다. As is well known, as the shrinking of DRAM devices proceeds, a rise in the electric field between the source / drain and the gate channel causes a decrease in refresh characteristics, which is necessary to improve. A recess gate is used to reduce the electric field by keeping the distance between the gate channel and the source / drain.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자 제조 방법을 도시한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 실리콘기판(11)에 포토레지스트 패턴(도시하지 않음)을 이용하여 실리콘기판(11) 내부의 소정영역을 식각하여 트렌치(12)를 형성한다.As shown in FIG. 1A, a trench 12 is formed by etching a predetermined region inside the silicon substrate 11 using a photoresist pattern (not shown) on the silicon substrate 11.

이어서, 도 1b에 도시된 바와 같이, 트렌치(12)를 포함한 실리콘기판(11) 전면에 습식산화 또는 건식산화 방법을 이용하여 얇은 게이트절연막(13)을 형성한다. Subsequently, as shown in FIG. 1B, a thin gate insulating film 13 is formed on the entire surface of the silicon substrate 11 including the trench 12 by using a wet oxidation method or a dry oxidation method.

이 때, 트렌치(12) 측벽과 밑면의 면지수가 상이하여, 각 면에서 형성되는 게이트절연막(13)의 두께가 다르게 된다. 주로 트렌치(12) 측벽 부분의 게이트절연막(13)의 두께가 두껍고, 측벽과 밑면이 만나는 트렌치모서리(14)에서 게이트절연막(13)에 스트레스(stress)가 집중된다. 따라서, 트렌치모서리(14)에서 트렌치(12) 측벽쪽으로 휜 모양의 게이트절연막(13)이 형성되는 것이다.At this time, the surface indexes of the sidewalls and the bottom surface of the trench 12 are different, so that the thickness of the gate insulating film 13 formed on each surface is different. Mainly, the thickness of the gate insulating film 13 in the sidewall portion of the trench 12 is thick, and stress is concentrated in the gate insulating film 13 in the trench corner 14 where the sidewall and the bottom face meet. Accordingly, a gate insulating film 13 having a 휜 shape is formed in the trench corner 14 toward the sidewalls of the trench 12.

도 1c에 도시된 바와 같이, 게이트절연막(13) 상부에 폴리실리콘(15)과 금속막(16)을 차례로 형성한다. 이 때, 트렌치(12) 내부의 측벽과 밑면에 형성된 게이트절연막(13)의 두께가 다르기 때문에, 폴리실리콘(15)의 심(seam)(17)이 깊게 발 생하고 따라서, 폴리실리콘(15)과 금속막(16) 사이에 메탈보이드(18)가 깊게 발생하게 된다. As shown in FIG. 1C, the polysilicon 15 and the metal film 16 are sequentially formed on the gate insulating film 13. At this time, since the thickness of the gate insulating film 13 formed on the sidewall and the bottom surface of the trench 12 is different, the seam 17 of the polysilicon 15 is deeply generated, and thus, the polysilicon 15 Between the metal film 16 and the metal void 18 is deeply generated.

따라서, 메탈보이드(18) 발생을 줄이기 위하여 폴리실리콘(15)을 상대적으로 두껍게 형성 후 화학적기계적연마(Chemical Mechanical Polishing; CMP) 등의 기술을 이용하여 폴리실리콘(15)를 평탄화할 수 있다.Accordingly, the polysilicon 15 may be planarized using a technique such as chemical mechanical polishing (CMP) after the relatively thick polysilicon 15 is formed to reduce the occurrence of the metal voids 18.

상술한 것처럼, 종래 기술에서 리세스 게이트를 형성하기 위한 게이트절연막이 동일한 두께로 형성되지 않는 이유는, 트렌치 내부의 측벽과 밑면의 면지수가 다르고, 측벽과 밑면이 만나는 트렌치 모서리에 스트레스가 집중되기 때문이다.
As described above, the reason why the gate insulating film for forming the recess gate is not formed in the same thickness in the related art is that the surface indexes of the sidewalls and the bottom surface of the trench are different, and stress is concentrated on the trench edges where the sidewalls and the bottom surface meet. Because.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 리세스 게이트 형성시 트렌치의 측면과 실질적으로 동일한 두께의 게이트절연막을 형성하는데 적합한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for forming a gate insulating film having a thickness substantially the same as the side surface of a trench when forming a recess gate.

상기 목적을 달성하기 위한 본 발명의 반도체 소자 제조 방법은 반도체 기판에 트렌치를 형성하는 단계, 상기 트렌치의 측벽과 밑면에서 동일한 산화속도 조건으로 게이트절연막을 형성하는 단계, 및 상기 게이트절연막 상에 게이트전극을 형성하는 단계를 포함하는 것을 특징으로 한다.
The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a trench in a semiconductor substrate, forming a gate insulating film at the same oxidation rate conditions on the sidewall and the bottom of the trench, and a gate electrode on the gate insulating film It characterized in that it comprises a step of forming.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 공정 단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 실리콘기판(21)에 포토레지스트 패턴(도시하지 않음)을 이용하여 실리콘기판(21) 내부의 소정영역을 식각하여 트렌치(22)를 형성한다.As shown in FIG. 2A, a trench 22 is formed by etching a predetermined region inside the silicon substrate 21 using a photoresist pattern (not shown) on the silicon substrate 21.

이어서, 도 2b에 도시된 바와 같이, 트렌치(22)를 포함한 실리콘기판(21) 전면에 라디컬 산화 또는 플라즈마 산화를 이용하여 얇은 게이트절연막(23)을 형성한다. Subsequently, as shown in FIG. 2B, a thin gate insulating film 23 is formed on the entire surface of the silicon substrate 21 including the trench 22 by using radical oxidation or plasma oxidation.

게이트절연막(23)을 형성하기 위한 라디컬 산화(Radical Oxidation)는 실리콘기판(21)의 Si와 O2가 반응하여 게이트절연막(23)이 성장되는데, 250℃∼400℃의 온도, 0.1Torr∼0.5Torr의 압력, H2/O2가스를 사용하는 공정 조건으로 진행된다.In the radical oxidation for forming the gate insulating film 23, the gate insulating film 23 is grown by reacting Si and O 2 of the silicon substrate 21 with a temperature of 250 ° C. to 400 ° C. and 0.1 Torr to The pressure is 0.5 Torr, and the process conditions are performed using H 2 / O 2 gas.

한편, 라디컬 산화 대신에 사용 가능한 플라즈마 산화(Plasma Oxidation)는 100℃∼700℃의 온도, 0.5Torr∼5Torr의 압력, 100Ｗ∼1000Ｗ의 R.F파워, O2/N2O/SiH4/DCS 가스를 사용하는 공정 조건으로 진행된다.Plasma Oxidation, which can be used instead of radical oxidation, has a temperature of 100 ° C. to 700 ° C., a pressure of 0.5 Torr to 5 Torr, an RF power of 100 mW to 1000 mW, and an O 2 / N 2 O / SiH 4 / DCS gas. Proceeds to the process conditions using.

도 2c에 도시된 바와 같이, 게이트절연막(23) 상부에 폴리실리콘(25)과 금속막(26)을 차례로 형성한다. 이 때, 트렌치(12) 내부에 형성된 게이트절연막(23)은 측벽과 밑면의 두께가 동일하게 형성되었기 때문에, 폴리실리콘(15)의 심(seam)(27)이 최소 깊이로 형성된다. 따라서, 폴리실리콘(25)과 금속막(26) 사이에 메탈보이드(28) 발생을 감소할 수 있다. As shown in FIG. 2C, the polysilicon 25 and the metal layer 26 are sequentially formed on the gate insulating layer 23. At this time, since the thickness of the sidewall and the bottom surface of the gate insulating film 23 formed in the trench 12 is the same, the seam 27 of the polysilicon 15 is formed to the minimum depth. Therefore, generation of the metal voids 28 between the polysilicon 25 and the metal film 26 can be reduced.

이처럼, 라디컬 산화와 플라즈마 산화를 이용해서 면지수와 무관하게 동일한 두께의 게이트절연막을 형성하여, 폴리실리콘 형성시 심(seam)이 최소화되고, 심(seam)이 최소화됨에 따라 폴리실리콘의 평탄화를 위한 추가의 CMP 공정이 생략되거나 축소 가능하다. As such, by forming a gate insulating film having the same thickness regardless of the surface index by using radical oxidation and plasma oxidation, polysilicon is minimized and seam is minimized to smooth the polysilicon. Additional CMP process for this may be omitted or reduced.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 트렌치의 측벽과 밑면에 동일한 두께의 게이트절연막을 형성하므로써, 게이트절연막의 신뢰성을 향상시키고 게이트 폴리실리콘의 평탄화 특성을 향상시킬 수 있으며, 공정 시간을 단축하는 효과가 있다.According to the present invention, by forming a gate insulating film having the same thickness on the sidewalls and the bottom of the trench, the reliability of the gate insulating film can be improved, the planarization characteristics of the gate polysilicon can be improved, and the process time can be shortened.

Claims (6)

반도체 기판에 트렌치를 형성하는 단계;Forming a trench in the semiconductor substrate; 상기 트렌치의 측벽과 밑면에서 동일한 산화속도 조건으로 게이트절연막을 형성하는 단계; 및Forming a gate insulating film on the sidewall and the bottom of the trench under the same oxidation rate condition; And 상기 게이트절연막 상에 게이트전극을 형성하는 단계 Forming a gate electrode on the gate insulating layer 를 포함하는 반도체 소자 제조 방법. Semiconductor device manufacturing method comprising a. 제 1항에 있어서,The method of claim 1, 상기 게이트절연막은 라디컬 산화로 형성되는 반도체 소자 제조 방법.And the gate insulating film is formed by radical oxidation. 제 1항에 있어서,The method of claim 1, 상기 게이트절연막은 플라즈마 산화로 형성되는 반도체 소자 제조 방법.And the gate insulating film is formed by plasma oxidation. 제 2항에 있어서,The method of claim 2, 상기 라디컬 산화는 250℃∼400℃의 온도, 0.1Torr∼0.5Torr의 압력, H2/O2 가스의 공정 조건으로 진행되는 반도체 소자 제조 방법.The radical oxidation is a semiconductor device manufacturing method that proceeds at a temperature of 250 ℃ to 400 ℃, a pressure of 0.1 Torr to 0.5 Torr, processing conditions of H 2 / O 2 gas. 제 3항에 있어서,The method of claim 3, wherein 상기 플라즈마 산화는 100℃∼700℃의 온도, 0.5Torr∼5Torr의 압력, 100Ｗ∼1000Ｗ의 R.F파워, O2/N2O/SiH4/DCS 가스의 공정 조건으로 진행되는 반도체 소자 제조 방법.The plasma oxidation is a method of manufacturing a semiconductor device is carried out at the temperature of 100 ℃ to 700 ℃, pressure of 0.5 Torr to 5 Torr, RF power of 100 kPa to 1000 kPa, process conditions of O 2 / N 2 O / SiH 4 / DCS gas. 제 1항에 있어서,The method of claim 1, 상기 게이트전극은 폴리실리콘과 게이트금속으로 이루어진 반도체 소자 제조 방법.The gate electrode is a semiconductor device manufacturing method consisting of polysilicon and a gate metal.
KR1020040087463A 2004-10-29 2004-10-29 Method for manufacturing semiconductor device KR20060038241A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100314672A1 (en) * 2009-06-11 2010-12-16 Sony Corporation Semiconductor device, method for manufacturing same, and solid-state image sensing device
US8497494B2 (en) 2006-11-24 2013-07-30 Lg Display Co., Ltd. Thin film transistor and array substrate for liquid crystal display device comprising organic insulating material
US9312124B2 (en) 2011-12-27 2016-04-12 Samsung Electronics Co., Ltd. Methods of fabricating gate insulating layers in gate trenches and methods of fabricating semiconductor devices including the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497494B2 (en) 2006-11-24 2013-07-30 Lg Display Co., Ltd. Thin film transistor and array substrate for liquid crystal display device comprising organic insulating material
US20100314672A1 (en) * 2009-06-11 2010-12-16 Sony Corporation Semiconductor device, method for manufacturing same, and solid-state image sensing device
CN101924135A (en) * 2009-06-11 2010-12-22 索尼公司 Semiconductor device, its manufacture method and solid-state image sensing device
US8878263B2 (en) * 2009-06-11 2014-11-04 Sony Corporation Semiconductor device, method for manufacturing same, and solid-state image sensing device
US9312124B2 (en) 2011-12-27 2016-04-12 Samsung Electronics Co., Ltd. Methods of fabricating gate insulating layers in gate trenches and methods of fabricating semiconductor devices including the same

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