KR20050101607A - Method for forming contact plug of semiconductor device - Google Patents

Method for forming contact plug of semiconductor device Download PDF

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KR20050101607A
KR20050101607A KR1020040026537A KR20040026537A KR20050101607A KR 20050101607 A KR20050101607 A KR 20050101607A KR 1020040026537 A KR1020040026537 A KR 1020040026537A KR 20040026537 A KR20040026537 A KR 20040026537A KR 20050101607 A KR20050101607 A KR 20050101607A
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forming
substrate
interlayer insulating
insulating film
single crystal
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KR1020040026537A
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조준희
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주식회사 하이닉스반도체
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Publication of KR20050101607A publication Critical patent/KR20050101607A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 단결정실리콘의 에피택셜 성장이 원활히 이루어지도록 할 수 있는 반도체 소자의 콘택 플러그 형성방법을 개시한다. 개시된 본 발명의 콘택 플러그 형성방법은, 실리콘 기판 상에 게이트들을 형성하는 단계와, 상기 게이트의 양측벽에 스페이서를 형성하는 단계와, 상기 게이트 양측의 기판 표면 내에 접합 영역을 형성하는 단계와, 상기 스페이서를 포함한 게이트들을 덮도록 기판 전면 상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 식각하여 게이트들 사이의 접합 영역을 노출시키는 콘택홀을 형성하는 단계와, 상기 콘택홀 표면 및 층간절연막 상에 산화막을 증착하는 단계와, 상기 산화막을 전면 식각하여 기판 접합 영역을 노출시키는 단계와, 상기 노출된 기판 접합 영역 상에 단결정실리콘을 에피택셜 성장시키는 단계를 포함한다. The present invention discloses a method for forming a contact plug of a semiconductor device capable of facilitating epitaxial growth of single crystal silicon. The disclosed method for forming a contact plug includes forming gates on a silicon substrate, forming spacers on both side walls of the gate, forming a junction region in the substrate surface on both sides of the gate, and Forming an interlayer insulating film on the entire surface of the substrate to cover the gates including the spacers; forming a contact hole to etch the interlayer insulating film to expose the junction regions between the gates; and on the contact hole surface and the interlayer insulating film. Depositing an oxide film on the substrate, etching the oxide film on the entire surface to expose a substrate bonding region, and epitaxially growing single crystal silicon on the exposed substrate bonding region.

Description

반도체 소자의 콘택 플러그 형성방법{Method for forming contact plug of semiconductor device}Method for forming contact plug of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 단결정 실리콘의 에피택셜 성장을 통한 반도체 소자의 콘택 플러그 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact plug of a semiconductor device through epitaxial growth of single crystal silicon.

반도체 소자 제조 공정중, 콘택 형성 공정은 반도체 소자의 접합 및 트랜지스터 특성, 신뢰성, 그리고, 수율 측면에서 매우 중요한 공정이다. 최근까지 메모리 반도체 소자의 제조 공정중 실리콘 기판에 형성된 콘택 공정의 플러그 물질로서는 퍼니스 타입(furnace type) 장비에서의 다결정실리콘이 널리 사용되고 있다. 이러한 다결정실리콘은 500∼600℃의 퍼니스에서 소오스 가스로 SiH4 가스를 이용하면서 도펀트로서 PH3 가스를 이용하여 증착한다. In the semiconductor device manufacturing process, the contact forming process is a very important process in terms of junction and transistor characteristics, reliability, and yield of the semiconductor device. Until recently, polycrystalline silicon in furnace type equipment has been widely used as a plug material of a contact process formed on a silicon substrate during a manufacturing process of a memory semiconductor device. Such polycrystalline silicon is deposited using a PH 3 gas as a dopant while using SiH 4 gas as a source gas in a furnace at 500 to 600 ° C.

그러나, 이와 같은 다결정실리콘의 증착방법은 콘택 저항의 증가, 분포 열화 및 높은 인(P) 농도에 의한 셀 접합 영역으로의 확산 등이 문제가 된다. However, such a polysilicon deposition method has problems such as increase in contact resistance, deterioration of distribution, and diffusion into cell junction regions due to high phosphorus (P) concentration.

이에, 상기한 문제를 극복하고 콘택 저항을 낮추기 위해 싱글-타입(single-type) CVD 장비에서 플러그 물질인 단결정실리콘을 성장시키는 에피-실리콘(epi-Si) 성장법이 활발하게 연구되고 있다. In order to overcome the above problems and lower the contact resistance, epi-silicon (epi-Si) growth method for growing single crystal silicon, which is a plug material, has been actively studied in single-type CVD equipment.

여기서, 상기 에피-실리콘 성장법으로는 SEG(Silicon Epitaxial Growth)와 SPE(Solid Phase Epitaxy)의 두 가지가 있다. 상기 두 가지 방법 모두 단결정실리콘의 증착 전에 인-시튜(in-situ)로 수소-베이크 공정을 진행하며, 이를 통해, 계면 산화막을 제거하여 콘택 저항을 낮춘다. Here, the epi-silicon growth method includes two kinds of silicon epitaxial growth (SEG) and solid phase epitaxy (SPE). Both methods perform a hydrogen-baking process in-situ before deposition of single crystal silicon, thereby lowering contact resistance by removing an interfacial oxide film.

그러나, 종래 단결정실리콘의 에피택셜 성장 공정에서는 콘택홀 측벽의 거칠기(Roughness), 금속 불순물(metal impurity)의 노출, 층간절연막에서의 이종 물질, 즉, 보론(B), 인(P)의 외방 확산 등으로 인해 다결정실리콘의 핵생성이 촉진되어, 도 1에서와 같이, 국부적으로 다결정실리콘(2)이 성장되며, 이에 따라, 단결정실리콘(1)의 에피택셜 성장이 원활히 이루어지지 못하고 있다. However, in the epitaxial growth process of conventional single crystal silicon, outward diffusion of the roughness of the contact hole sidewalls, exposure of metal impurity, heterogeneous materials in the interlayer insulating film, that is, boron (B) and phosphorus (P) Etc., the nucleation of the polycrystalline silicon is promoted, and as shown in FIG. 1, the polycrystalline silicon 2 is locally grown. As a result, the epitaxial growth of the single crystal silicon 1 is not smoothly performed.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 단결정실리콘의 에피택셜 성장이 원활히 이루어지도록 할 수 있는 반도체 소자의 콘택 플러그 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a contact plug of a semiconductor device capable of smoothly performing epitaxial growth of single crystal silicon.

또한, 본 발명은 단결정실리콘의 에피택셜 성장이 원활히 이루어지도록 함으로써 소망하는 콘택 특성을 얻을 수 있는 반도체 소자의 콘택 플러그 형성방법을 제공함에 그 다른 목적이 있다. In addition, another object of the present invention is to provide a method for forming a contact plug of a semiconductor device which can achieve desired contact characteristics by facilitating epitaxial growth of single crystal silicon.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 실리콘 기판 상에 게이트들을 형성하는 단계; 상기 게이트의 양측벽에 스페이서를 형성하는 단계; 상기 게이트 양측의 기판 표면 내에 접합 영역을 형성하는 단계; 상기 스페이서를 포함한 게이트들을 덮도록 기판 전면 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 게이트들 사이의 접합 영역을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀 표면 및 층간절연막 상에 산화막을 증착하는 단계; 상기 산화막을 전면 식각하여 기판 접합 영역을 노출시키는 단계; 상기 노출된 기판 접합 영역 상에 단결정실리콘을 에피택셜 성장시키는 단계를 포함하는 반도체 소자의 콘택 플러그 형성방법을 제공한다. In order to achieve the above object, the present invention, forming a gate on a silicon substrate; Forming spacers on both side walls of the gate; Forming a junction region in the substrate surface on both sides of the gate; Forming an interlayer insulating film on the entire surface of the substrate to cover the gates including the spacers; Etching the interlayer insulating film to form a contact hole exposing a junction region between gates; Depositing an oxide film on the contact hole surface and the interlayer insulating film; Etching the entire oxide film to expose a substrate bonding region; It provides a method for forming a contact plug of a semiconductor device comprising epitaxially growing single crystal silicon on the exposed substrate bonding region.

여기서, 상기 산화막은 30∼70Å 두께로 증착한다. Here, the oxide film is deposited to a thickness of 30 to 70 Å.

또한, 상기 단결정실리콘을 에피택셜 성장시키는 단계는 550∼650℃에서 SPE 방법으로 진행한다. In addition, the epitaxial growth of the single crystal silicon is performed by the SPE method at 550 ~ 650 ℃.

게다가, 상기한 본 발명의 콘택 플러그 형성방법은 상기 산화막을 전면 식각한 후, 그리고, 단결정실리콘을 에피택셜 성장시키기 전, 900∼1000℃ 온도에서 H2 베이크를 수행한다. In addition, the method for forming a contact plug according to the present invention performs H 2 bake at a temperature of 900 to 1000 ° C. after the entire surface of the oxide film is etched and before epitaxially growing single crystal silicon.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택 플러그 형성방법을 설명하기 위한 공정별 단면도이다. 2A through 2D are cross-sectional views illustrating processes for forming a contact plug of a semiconductor device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 소자분리막(21)에 의해 한정된 반도체 기판(20)의 액티브 영역 상에 공지의 공정에 따라 게이트(22)를 형성한다. 이때, 상기 게이트(22)는 게이트절연막과, 폴리실리콘막과 금속실리사이드막의 적층막으로된 게이트도전막 및 질화막으로된 하드마스크막의 적층 구조로 형성한다. Referring to FIG. 2A, the gate 22 is formed on the active region of the semiconductor substrate 20 defined by the device isolation film 21 according to a known process. At this time, the gate 22 is formed in a laminated structure of a gate insulating film, a gate conductive film made of a laminated film of a polysilicon film and a metal silicide film, and a hard mask film made of a nitride film.

다음으로, 기판 전면 상에 절연막을 증착한 후, 이를 블랭킷 식각하여 게이트(22)의 양측벽에 스페이서(23)를 형성한다. 그런다음, 기판 결과물에 대해 소오스/드레인 이온주입을 수행하여 상기 스페이서(23)를 포함한 게이트(22) 양측의 기판 표면 내에 접합 영역(24)을 형성한다. Next, after the insulating film is deposited on the entire surface of the substrate, the spacer 23 is formed on both sidewalls of the gate 22 by blanket etching the insulating film. Then, source / drain ion implantation is performed on the substrate product to form a junction region 24 in the substrate surface on both sides of the gate 22 including the spacer 23.

그 다음, 상기 단계까지의 기판 결과물 상에, 예컨데, BPSG막으로 이루어진 층간절연막(25)을 증착한 후, 상기 층간절연막(25) 상에 접합 영역(24) 상부의 층간절연막 부분을 노출시키는 감광막 패턴(26)을 형성한다. 그런다음, 노출된 층간절연막 부분을 식각하여 기판 접합 영역(24)을 노출시키는 콘택홀(27)을 형성한다. A photoresist film is then deposited on the substrate resultant up to the step, for example, by depositing an interlayer insulating film 25 made of a BPSG film and then exposing an interlayer insulating film portion over the junction region 24 on the interlayer insulating film 25. The pattern 26 is formed. Then, the exposed interlayer insulating film portion is etched to form a contact hole 27 exposing the substrate junction region 24.

도 2b를 참조하면, 감광막 패턴을 제거한 상태에서, 콘택홀(27)의 표면 및 층간절연막(25) 상에 박막의 산화막(28)을 증착한다. 이때, 상기 산화막(28)은 콘택홀(27)의 표면 거칠기를 완화시키고, 금속 불순물의 노출 및 BPSG막으로된 층간절연막(25)의 보론(B) 및 인(P)이 외방 확산되는 것이 억제되도록 대략 30∼70Å의 두께로 증착한다. Referring to FIG. 2B, a thin film oxide film 28 is deposited on the surface of the contact hole 27 and the interlayer insulating film 25 in a state where the photoresist pattern is removed. At this time, the oxide film 28 reduces the surface roughness of the contact hole 27 and suppresses the exposure of metal impurities and the diffusion of boron (B) and phosphorus (P) out of the interlayer insulating film 25 made of the BPSG film. The deposition is carried out to a thickness of approximately 30 to 70 mm as possible.

도 2c를 참조하면, 상기 산화막(28)을 마스크의 사용없이 전면 식각하고, 이를 통해, 기판 접합 영역(24)을 노출시킨다. 이때, 상기 산화막(28)은 기판 접합 영역 및 층간절연막(25) 상에 증착된 부분이 제거되어 콘택홀(27)의 측벽에만 스페이서 형태로 잔류된다.Referring to FIG. 2C, the oxide layer 28 is etched entirely without using a mask, thereby exposing the substrate bonding region 24. At this time, the oxide layer 28 is removed from the portion deposited on the substrate bonding region and the interlayer insulating layer 25 and is left in the form of a spacer only on the sidewall of the contact hole 27.

도 2d를 참조하면, 콘택홀(27) 내에 SPE 방법에 따라 550∼650℃의 저온에서 단결정실리콘을 에피택셜 성장시키고, 이를 통해, 노출된 기판 접합 영역(24) 상에 콘택 플러그(29)를 형성한다. Referring to FIG. 2D, the single crystal silicon is epitaxially grown in the contact hole 27 at a low temperature of 550 to 650 ° C. according to the SPE method, thereby forming the contact plug 29 on the exposed substrate bonding region 24. Form.

여기서, 상기 콘택홀(27)의 측벽에는 박막의 산화막(28)이 형성되어 있으므로, 이러한 산화막(28)에 의해 콘택홀(27)의 거칠기는 완화되고, 또한, 금속 불순물의 노출이 억제되며, 특히, BPSG막으로된 층간절연막(25)에서의 보론(B) 및 인(P)의 외방 확산이 차단되는 바, 상기 콘택홀(27) 내에 다결정실리콘의 핵성장없이 단결정실리콘만을 에피택셜 성장시킬 수 있다. Here, since the thin film oxide film 28 is formed on the sidewall of the contact hole 27, the roughness of the contact hole 27 is alleviated by the oxide film 28, and the exposure of metal impurities is suppressed. In particular, the outward diffusion of boron (B) and phosphorus (P) in the interlayer insulating film 25 of the BPSG film is blocked, so that only single crystal silicon can be epitaxially grown without nucleation of polycrystalline silicon in the contact hole 27. Can be.

따라서, 본 발명은 단결정실리콘의 에피택셜 성장이 원활하게 이루어지도록 할 수 있는 바, 용이하게 소망하는 콘택 특성을 갖는 콘택 플러그(29)를 형성할 수 있다. Therefore, the present invention can facilitate the epitaxial growth of single crystal silicon, and can easily form a contact plug 29 having desired contact characteristics.

한편, 본 발명은 상기 단결정실리콘을 에피택셜 성장시키기 전, 기판 접합 영역(24) 상의 이물질 및 자연산화막이 제거되도록 전처리(pretreatment) 공정을 수행하며, 이러한 전처리 공정으로는 바람직하게 900∼1000℃의 고온에서 수소 베이크로 진행하거나, 또는, 수소분위기에서 플라즈마에 노출시키는 방법으로 진행한다. On the other hand, before the epitaxial growth of the single crystal silicon, the present invention performs a pretreatment process to remove the foreign matter and the natural oxide film on the substrate bonding region 24, such a pretreatment process is preferably 900 ~ 1000 ℃ Proceed to hydrogen bake at high temperature or to exposure to plasma in a hydrogen atmosphere.

이후, 공지된 일련의 후속 공정을 진행하여 본 발명의 반도체 소자를 완성한다. Thereafter, a series of known subsequent processes are performed to complete the semiconductor device of the present invention.

이상에서와 같이, 본 발명은 단결정실리콘이 에피택셜 성장될 콘택홀의 측벽만에 선택적으로 산화막을 형성해 줌으로써 콘택홀 측벽의 거칠기 완화, 금속 불순물 노출 억제 및 층간절연막 물질에서의 보론 및 인의 외방 확산 감소 등을 통해 상기 단결정실리콘의 에피택셜 성장이 원활히 이루어지도록 할 수 있으며, 이에 따라, 단결정실리콘으로 이루어진 콘택 플러그를 형성할 수 있는 바, 소망하는 콘택 특성 및 소자 특성을 확보할 수 있다.As described above, the present invention forms an oxide film only on the sidewalls of the contact holes to be epitaxially grown, thereby reducing the roughness of the contact hole sidewalls, suppressing the exposure of metal impurities, and reducing the outward diffusion of boron and phosphorus in the interlayer insulating film material. Through the epitaxial growth of the single crystal silicon can be made smoothly, thereby forming a contact plug made of single crystal silicon, it is possible to secure the desired contact characteristics and device characteristics.

이상, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있으며, 그러므로, 이하 특허청구범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다. As described above, specific embodiments of the present invention have been described and illustrated, but modifications and variations can be made by those skilled in the art. Therefore, the following claims are intended to cover all modifications and modifications as long as they fall within the true spirit and scope of the present invention. It is understood to include variations.

도 1은 종래 문제점을 설명하기 위한 사진. 1 is a photograph for explaining the conventional problem.

도 2a 내지 도 2d는 본 발명에 따른 콘택 플러그 형성방법을 설명하기 위한 공정별 단면도. 2A to 2D are cross-sectional views for each process for explaining a method for forming a contact plug according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on main parts of drawing

20 : 실리콘 기판 21 : 소자분리막20 silicon substrate 21 device isolation film

22 : 게이트 23 : 스페이서22: gate 23: spacer

24 : 접합 영역 25 : 층간절연막24 junction area 25 interlayer insulating film

26 : 감광막 패턴 27 : 콘택홀26: photosensitive film pattern 27: contact hole

28 : 산화막 29 : 콘택 플러그28: oxide film 29: contact plug

Claims (4)

실리콘 기판 상에 게이트들을 형성하는 단계; Forming gates on a silicon substrate; 상기 게이트의 양측벽에 스페이서를 형성하는 단계; Forming spacers on both side walls of the gate; 상기 게이트 양측의 기판 표면 내에 접합 영역을 형성하는 단계; Forming a junction region in the substrate surface on both sides of the gate; 상기 스페이서를 포함한 게이트들을 덮도록 기판 전면 상에 층간절연막을 형성하는 단계; Forming an interlayer insulating film on the entire surface of the substrate to cover the gates including the spacers; 상기 층간절연막을 식각하여 게이트들 사이의 접합 영역을 노출시키는 콘택홀을 형성하는 단계; Etching the interlayer insulating film to form a contact hole exposing a junction region between gates; 상기 콘택홀 표면 및 층간절연막 상에 산화막을 증착하는 단계; Depositing an oxide film on the contact hole surface and the interlayer insulating film; 상기 산화막을 전면 식각하여 기판 접합 영역을 노출시키는 단계; Etching the entire oxide film to expose a substrate bonding region; 상기 노출된 기판 접합 영역 상에 단결정실리콘을 에피택셜 성장시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성방법.And epitaxially growing single crystal silicon on the exposed substrate bonding region. 제 1 항에 있어서, 상기 산화막은 30∼70Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성방법. The method of claim 1, wherein the oxide film is deposited to a thickness of 30 to 70 kHz. 제 1 항에 있어서, 상기 단결정실리콘을 에피택셜 성장시키는 단계는 The method of claim 1, wherein the epitaxial growth of the single crystal silicon is 550∼650℃에서 SPE 방법으로 진행하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성방법.A method of forming a contact plug for a semiconductor device, characterized by advancing by SPE at 550-650 ° C. 제 1 항에 있어서, 상기 산화막을 전면 식각한 후, 그리고, 단결정실리콘을 에피택셜 성장시키기 전, 900∼1000℃ 온도에서 H2 베이크를 수행하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성방법. The method of claim 1, wherein H 2 bake is performed at a temperature of 900 to 1000 ° C. after the entire surface is etched and before epitaxially growing single crystal silicon.
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