KR20050100283A - Manufacturing method for metal electrode capacitor - Google Patents
Manufacturing method for metal electrode capacitor Download PDFInfo
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- KR20050100283A KR20050100283A KR1020040025508A KR20040025508A KR20050100283A KR 20050100283 A KR20050100283 A KR 20050100283A KR 1020040025508 A KR1020040025508 A KR 1020040025508A KR 20040025508 A KR20040025508 A KR 20040025508A KR 20050100283 A KR20050100283 A KR 20050100283A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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Abstract
본 발명은 금속전극 커패시터 제조방법에 관한 것으로, 제1산화막에 트렌치를 형성하고, 금속의 증착 및 평탄화 공정을 통하여 그 트렌치 내에 제1금속전극을 형성하는 단계와; 상기 제1금속전극과 제1산화막 상에 유전층을 증착하는 단계와; 상기 유전층의 상부전면에 제2산화막을 증착하고, 상기 제1금속전극의 중앙 상부에 해당하는 제2산화막에 트렌치를 형성하여 그 하부의 유전층을 노출시킨 후, 금속의 증착 및 평탄화 공정을 통해 제2산화막의 트렌치에 위치하는 제2금속전극을 형성하는 단계로 구성된다. 이와 같은 구성에 의하여 본 발명은 금속전극 커패시터의 두 전극을 트렌치의 형성과 금속의 증착 및 평탄화공정을 통해 제조함으로써, 금속전극의 형성시 발생되는 부산물이 다른 금속전극의 형성시 영향을 주지 않도록 하여 금속전극간에 브리지가 발생하는 것을 방지하여, 소자의 신뢰성을 향상시킴과 아울러 수율을 향상시키는 효과가 있다. The present invention relates to a method for manufacturing a metal electrode capacitor, comprising: forming a trench in a first oxide film, and forming a first metal electrode in the trench through a metal deposition and planarization process; Depositing a dielectric layer on the first metal electrode and the first oxide film; After depositing a second oxide film on the upper surface of the dielectric layer, forming a trench in the second oxide film corresponding to the upper center of the first metal electrode to expose the lower dielectric layer, and through the deposition and planarization process of the metal And forming a second metal electrode positioned in the trench of the second oxide film. By the above configuration, the present invention manufactures two electrodes of the metal electrode capacitor through the formation of the trench and the deposition and planarization of the metal, so that by-products generated during the formation of the metal electrode do not affect the formation of the other metal electrode. There is an effect of preventing the occurrence of bridges between metal electrodes, improving the reliability of the device and improving the yield.
Description
본 발명은 금속전극 커패시터 제조방법에 관한 것으로, 특히 다수의 금속전극 커패시터를 제조함에 있어서, 식각 부산물에 의한 금속전극 커패시터의 상부전극과 하부전극 사이에 브리지가 발생되는 것을 방지할 수 있는 금속전극 커패시터 제조방법에 관한 것이다. The present invention relates to a method of manufacturing a metal electrode capacitor, in particular, in manufacturing a plurality of metal electrode capacitors, metal electrode capacitors that can prevent the bridge is generated between the upper electrode and the lower electrode of the metal electrode capacitor by the etching by-products It relates to a manufacturing method.
일반적으로 금속전극 커패시터는 두 금속전극의 사이에 유전층을 구비하는 것으로, 금속, 유전층, 금속을 순차적으로 증착하고 마스크를 사용하는 건식식각공정으로 그 증착된 금속, 유전층, 금속을 차례로 패터닝하여 형성한다.In general, a metal electrode capacitor includes a dielectric layer between two metal electrodes, and is formed by sequentially depositing a metal, a dielectric layer, and a metal, and patterning the deposited metal, the dielectric layer, and the metal in sequence by a dry etching process using a mask. .
그러나 종래 금속전극 커패시터 제조방법은 다수 회의 건식식각공정을 사용하여 식각부산물과 파티클이 발생하여 단일 커패시터에서의 상부전극과 하부전극간에 브리지가 형성되어 소자의 신뢰성과 수율을 저하시키는 문제점이 있었다. However, in the conventional metal electrode capacitor manufacturing method, etching by-products and particles are generated by using a plurality of dry etching processes, and a bridge is formed between the upper electrode and the lower electrode in a single capacitor, thereby reducing the reliability and yield of the device.
상기와 같은 문제점을 감안한 본 발명은 상부전극과 하부전극의 사이에 브리지가 발생되는 것을 방지할 수 있는 금속전극 커패시터 제조방법을 제공함에 그 목적이 있다. It is an object of the present invention to provide a method for manufacturing a metal electrode capacitor capable of preventing a bridge from being generated between an upper electrode and a lower electrode.
상기와 같은 목적을 달성하기 위한 본 발명은 제1산화막에 트렌치를 형성하고, 금속의 증착 및 평탄화 공정을 통하여 그 트렌치 내에 제1금속전극을 형성하는 단계와; 상기 제1금속전극과 제1산화막 상에 유전층을 증착하는 단계와; 상기 유전층의 상부전면에 제2산화막을 증착하고, 상기 제1금속전극의 중앙 상부에 해당하는 제2산화막에 트렌치를 형성하여 그 하부의 유전층을 노출시킨 후, 금속의 증착 및 평탄화 공정을 통해 제2산화막의 트렌치에 위치하는 제2금속전극을 형성하는 단계로 구성함에 그 특징이 있다. The present invention for achieving the above object comprises forming a trench in the first oxide film, and forming a first metal electrode in the trench through a metal deposition and planarization process; Depositing a dielectric layer on the first metal electrode and the first oxide film; After depositing a second oxide film on the upper surface of the dielectric layer, forming a trench in the second oxide film corresponding to the upper center of the first metal electrode to expose the lower dielectric layer, and through the deposition and planarization process of the metal It is characterized by the step of forming a second metal electrode located in the trench of the oxide film.
상기와 같이 구성되는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings an embodiment of the present invention configured as described above are as follows.
도 1a 내지 도 1g는 본 발명에 따르는 금속전극 커패시터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부전면에 산화막(2), 질화막(3), 산화막(4)을 순차적으로 증착한 후, 사진식각공정을 통해 상기 산화막(4)의 일부와 그 하부의 질화막(3) 및 그 질화막(4) 하부의 산화막(2) 상부일부를 식각한 후, 그 식각영역에 배리어 금속층(5)과 구리(6)를 증착하는 단계(도 1a)와; 상기 구조의 상부에 질화막(7)을 증착하는 단계(도 1b)와; 상기 구조의 상부전면에 산화막(8)을 증착하고, 그 산화막(8) 상에 포토레지스트 패턴(PR)을 형성하여 상기 구리(6)의 중앙 상부측에 위치하는 산화막(8)의 일부를 노출시키는 단계(도 1c)와; 상기 포토레지스트 패턴(PR)을 식각마스크로 상기 노출된 산화막(8)을 식각하여 그 하부의 질화막(7)을 노출시키고, 포토레지스트 패턴(PR)을 제거하는 단계(도 1d)와; 상기 구조의 상부전면에 배리어 금속층(9)과 구리(10)를 증착하고, 평탄화하여 상기 산화막(8)의 식각영역에 상부전극을 형성하는 단계(도 1e)와; 상기 구조의 상부전면에 질화막(11)과 산화막(12)을 증착하는 단계(도 1f)와; 상기 증착된 산화막(12)과 질화막(11)의 일부 및 산화막(12)과 질화막(11)과 그 하부의 산화막(8)과 질화막(7)의 일부를 식각하여 상기 구리(6),(10)의 상부일부를 노출시킨 후, 노출된 구리(6),(10)에 각각 접속되는 플러그(13, 14)를 형성하는 단계(도 1g)로 구성된다.1A to 1G are cross-sectional views of a manufacturing process of a metal electrode capacitor according to the present invention. As shown therein, an oxide film 2, a nitride film 3, and an oxide film 4 are sequentially formed on an upper surface of a substrate 1. After deposition, a portion of the oxide film 4 and a portion of the nitride film 3 below and the upper portion of the oxide film 2 under the nitride film 4 are etched through a photolithography process, and then a barrier metal layer ( 5) and depositing copper (FIG. 1A); Depositing a nitride film (7) on top of the structure (FIG. 1B); An oxide film 8 is deposited on the upper surface of the structure, and a photoresist pattern PR is formed on the oxide film 8 to expose a portion of the oxide film 8 located above the center of the copper 6. Step (FIG. 1C); Etching the exposed oxide film 8 by using the photoresist pattern PR as an etch mask to expose the lower nitride film 7 and removing the photoresist pattern PR (FIG. 1D); Depositing and planarizing a barrier metal layer (9) and copper (10) on the upper surface of the structure to form an upper electrode in an etching region of the oxide film (FIG. 1E); Depositing a nitride film (11) and an oxide film (12) on the upper surface of the structure (FIG. 1F); A portion of the deposited oxide film 12 and nitride film 11, an oxide film 12, a nitride film 11, and a portion of an oxide film 8 and a nitride film 7 below is etched to form the copper 6, 10. After exposing a portion of the upper part, the step of forming a plug (13, 14) connected to the exposed copper (6), 10, respectively (Fig. 1g).
이하, 상기와 같이 구성되는 본 발명에 따르는 금속전극 커패시터 제조방법을 보다 상세히 설명한다.Hereinafter, the metal electrode capacitor manufacturing method according to the present invention configured as described above in more detail.
먼저, 도 1a에 도시한 바와 같이 기판(1)의 상부전면에 산화막(2), 질화막(3), 산화막(4)을 순차적으로 증착한다.First, as illustrated in FIG. 1A, an oxide film 2, a nitride film 3, and an oxide film 4 are sequentially deposited on the upper surface of the substrate 1.
그 다음, 사진식각공정을 통해 상기 산화막(4)의 일부와 그 하부의 질화막(4) 및 그 질화막(3) 하부의 산화막(2) 상부일부를 식각하여 트렌치를 형성한다.Then, a trench is formed by etching a portion of the oxide film 4, a nitride film 4 under the oxide film 4, and an upper portion of the oxide film 2 under the nitride film 3 through a photolithography process.
그 다음, 상기 구조의 상부전면에 배리어 금속층(5)과 구리(6)를 순차적으로 증착하고, 그 구리(6)와 배리어 금속층(5)을 평탄화하여 상기 산화막(4), 질화막(3) 및 산화막(2)의 일부에 형성된 트렌치 내에 위치하는 하부전극을 형성한다.Then, the barrier metal layer 5 and the copper 6 are sequentially deposited on the upper surface of the structure, and the copper 6 and the barrier metal layer 5 are planarized so that the oxide film 4, the nitride film 3, and the like. A lower electrode located in the trench formed in part of the oxide film 2 is formed.
그 다음, 도 1b에 도시한 바와 같이 상기 구조의 상부에 질화막(7)을 증착한다.Then, a nitride film 7 is deposited on top of the structure as shown in FIG. 1B.
이때의 질화막(7)은 유전체로서, 본 발명에 따르는 커패시터의 금속전극 사이에 위치한다.The nitride film 7 at this time is a dielectric material and is located between the metal electrodes of the capacitor according to the present invention.
그 다음, 도 1c에 도시한 바와 같이 상기 구조의 상부전면에 산화막(8)을 증착한다.Then, an oxide film 8 is deposited on the upper surface of the structure as shown in Fig. 1C.
그 다음, 상기 산화막(8)의 상부전면에 포토레지스트를 도포하고, 노광 및 현상하여 상기 형성한 구리(6)의 중앙 상부측에 위치하는 산화막(8)의 일부를 노출시키는 포토레지스트 패턴(PR)을 형성한다.Next, a photoresist is applied to the entire upper surface of the oxide film 8, and the photoresist pattern PR is exposed and developed to expose a portion of the oxide film 8 located at the center upper side of the formed copper 6. ).
그 다음, 도 1d에 도시한 바와 같이 상기 상기 포토레지스트 패턴(PR)을 식각마스크로 사용하는 식각공정으로 상기 노출된 산화막(8)을 식각하여 그 하부의 질화막(7)을 노출시킨다.Next, as shown in FIG. 1D, the exposed oxide layer 8 is etched by using the photoresist pattern PR as an etching mask to expose the lower nitride layer 7.
그 다음, 세정공정을 통해 포토레지스트 패턴(PR)과 산화막(8)의 식각부산물을 제거한다.Then, the etching by-products of the photoresist pattern PR and the oxide film 8 are removed through a cleaning process.
그 다음, 도 1e에 도시한 바와 같이 상기 구조의 상부전면에 배리어 금속층(9)과 구리(10)를 증착하고, 평탄화하여 상기 산화막(8)의 식각영역에 위치하는 상부전극을 형성한다.Next, as shown in FIG. 1E, the barrier metal layer 9 and copper 10 are deposited on the upper surface of the structure, and planarized to form an upper electrode positioned in an etching region of the oxide film 8.
그 다음, 도 1f에 도시한 바와 같이 상기 구조의 상부전면에 질화막(11)과 산화막(12)을 증착한다.Next, as shown in FIG. 1F, a nitride film 11 and an oxide film 12 are deposited on the upper surface of the structure.
그 다음, 도 1g에 도시한 바와 같이 상기 증착된 산화막(12)의 상부에 포토레지스트(도면 미도시)를 도포하여, 상기 구리(10)의 중앙상부측과 구리(6)의 측면 상부측에 해당하는 산화막(12)의 일부를 노출시킨다.Next, as shown in FIG. 1G, a photoresist (not shown) is applied to the deposited oxide film 12, and the upper portion of the center of the copper 10 and the upper side of the copper 6 are applied. A portion of the corresponding oxide film 12 is exposed.
그 다음, 상기 노출된 산화막(12)과 그 하부에 위치하는 질화막(11), 그 산화막(12)과 질화막(11) 및 그 하부의 산화막(8)과 질화막(7)의 일부를 식각하여 상기 구리(6),(10)의 상부일부를 노출시키는 콘택홀을 형성한다.Next, the exposed oxide film 12 and the nitride film 11 positioned below the oxide film 12, the oxide film 12 and the nitride film 11, and a portion of the oxide film 8 and the nitride film 7 below it are etched. Contact holes exposing upper portions of the copper 6 and 10 are formed.
그 다음, 배리어 금속과 구리를 증착한 후, 평탄화하여 상기 콘택홀 내에 위치하는 플러그(13, 14)를 형성한다. The barrier metal and copper are then deposited and planarized to form plugs 13 and 14 located in the contact holes.
이처럼 본 발명에 따르는 금속전극 커패시터는 두 전극층과 유전막을 별도의 구분된 공정 단계로 제조하여 전극의 형성에 따른 식각부산물이 다른 전극의 형성시에 영향을 주지 않도록 함으로써, 전극간의 브리지가 발생하는 것을 방지할 수 있게 된다. As described above, the metal electrode capacitor according to the present invention manufactures the two electrode layers and the dielectric film in separate process steps so that the etching by-product according to the formation of the electrode does not affect the formation of the other electrode, thereby generating a bridge between the electrodes. It can be prevented.
이상에서는 본 발명을 특정의 바람직한 실시 예들을 들어 도시하고 설명하였으나, 본 발명은 상기한 실시 예들에 한정되지 않으며 본 발명의 개념을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능하다. The present invention has been shown and described with reference to certain preferred embodiments, but the present invention is not limited to the above-described embodiments and has ordinary skill in the art to which the present invention pertains without departing from the concept of the present invention. Various changes and modifications are possible by the user.
상기한 바와 같이 본 발명은 금속전극 커패시터의 두 전극을 트렌치의 형성과 금속의 증착 및 평탄화공정을 통해 제조함으로써, 금속전극의 형성시 발생되는 부산물이 다른 금속전극의 형성시 영향을 주지 않도록 하여 금속전극간에 브리지가 발생하는 것을 방지하여, 소자의 신뢰성을 향상시킴과 아울러 수율을 향상시키는 효과가 있다.As described above, the present invention manufactures two electrodes of the metal electrode capacitor through the formation of the trench and the deposition and planarization of the metal, so that the by-products generated during the formation of the metal electrode do not affect the formation of the other metal electrode. There is an effect of preventing the occurrence of bridges between the electrodes, improving the reliability of the device and improving the yield.
도 1a 내지 도 1g는 본 발명에 따르는 금속전극 커패시터의 제조공정 수순단면도. Figure 1a to 1g is a cross-sectional view of the manufacturing process of the metal electrode capacitor according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1:기판 2,4,8,12:산화막1: substrate 2, 4, 8, 12: oxide film
3,7,11:질화막 5,9:배리어 금속3,7,11: nitride film 5,9: barrier metal
6,10:구리 13,14:플러그 6, 10: copper 13, 14: plug
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