KR20050096694A - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
- Publication number
- KR20050096694A KR20050096694A KR1020040022154A KR20040022154A KR20050096694A KR 20050096694 A KR20050096694 A KR 20050096694A KR 1020040022154 A KR1020040022154 A KR 1020040022154A KR 20040022154 A KR20040022154 A KR 20040022154A KR 20050096694 A KR20050096694 A KR 20050096694A
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- South Korea
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- etching
- cmp
- plate
- fail
- semiconductor device
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60J—WINDOWS, WINDSCREENS, NON-FIXED ROOFS, DOORS, OR SIMILAR DEVICES FOR VEHICLES; REMOVABLE EXTERNAL PROTECTIVE COVERINGS SPECIALLY ADAPTED FOR VEHICLES
- B60J1/00—Windows; Windscreens; Accessories therefor
- B60J1/20—Accessories, e.g. wind deflectors, blinds
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- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B9/00—Screening or protective devices for wall or similar openings, with or without operating or securing mechanisms; Closures of similar construction
- E06B9/52—Devices affording protection against insects, e.g. fly screens; Mesh windows for other purposes
-
- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B9/00—Screening or protective devices for wall or similar openings, with or without operating or securing mechanisms; Closures of similar construction
- E06B9/52—Devices affording protection against insects, e.g. fly screens; Mesh windows for other purposes
- E06B2009/527—Mounting of screens to window or door
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- Engineering & Computer Science (AREA)
- Structural Engineering (AREA)
- Mechanical Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Insects & Arthropods (AREA)
- Pest Control & Pesticides (AREA)
- Architecture (AREA)
- Civil Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본원 발명은 플레이트 에칭(Plate Etching) 공정, 층간절연막 증착, CMP 공정, 층간절연막 추가 증착 공정 순서로 진행되는 반도체 소자 제조 공정에서, 공정시 발생된 불필요한 입자(particle)을 CMP 공정을 통해 제거하고자 할 경우에는 과도한 CMP 또는 CMP 공정에서 떨어져 나온 찌꺼기 등으로 인하여, Direct Current Fail(DC Fail)이 발생할 수 있게 되는데, 이를 경사식각 방식을 적용한 플레이트 에칭 공정을 수행함으로써, 불필요한 입자를 발생시킬 가능성이 있는 CMP 공정을 생략하여 결과적으로 DC Fail 문제를 감소시키는 것을 특징으로 한다.According to the present invention, in the semiconductor device fabrication process in which the plate etching process, the interlayer dielectric film deposition, the CMP process, and the interlayer dielectric additional deposition process are performed, the unwanted particles generated during the process are to be removed through the CMP process. In this case, direct current fail (DC fail) may occur due to excessive CMP or debris falling from the CMP process. By performing a plate etching process using a gradient etching method, CMP that may generate unnecessary particles may be generated. By omitting the process, as a result, the DC fail problem is reduced.
Description
본원 발명은 반도체 소자 제조 공정중에 발생되는 DC Fail을 감소시키는 방법에 관한 것으로서, 특히 경사 식각 방식을 적용한 플레이트 에칭 공정을 수행함으로써, CMP 공정을 통해 발생될 수 있는 DC Fail을 감소시키는 기술에 관한 것이다.The present invention relates to a method for reducing DC fail generated during a semiconductor device manufacturing process, and more particularly, to a technique for reducing DC fail generated through a CMP process by performing a plate etching process using a gradient etching method. .
일반적으로, 반도체 소자의 제조 공정은 플레이트 에칭 공정, 층간절연막 증착, CMP 공정, 층간절연막 추가 증착 공정 순서로 진행되게 되는데, 특히 플레이트 에칭 공정, 또는 층간절연막 증착 과정에서 또는 그 전 공정에서 발생된 불필요한 입자(particle)는 CMP를 통해 제거하게 된다.In general, the semiconductor device fabrication process is performed in the order of a plate etching process, an interlayer dielectric film deposition, a CMP process, and an additional interlayer dielectric film deposition process. In particular, unnecessary processes generated during or before the plate etching process or the interlayer dielectric film deposition process are performed. Particles are removed through CMP.
그런데, 이러한 CMP 공정을 수행하는데 있어서 과도 식각을 하게 될 수도 있고, 또는 CMP 공정 과정 자체에서 찌꺼기 등이 발생될 수도 있는데, 이러한 경우에는 발생된 찌꺼기로 인해서 DC Fail이 발생하게 된다.However, excessive etching may be performed in performing the CMP process, or debris may be generated in the CMP process itself. In this case, DC fail occurs due to the generated debris.
그러나, 이러한 CMP 공정을 생략할 경우에는 도 1에 도시된 바와 같은 또 다른 문제를 발생시키긴다.However, omitting such a CMP process causes another problem as shown in FIG. 1.
플레이트(1)에 대하여 에칭 공정을 수행하고, 그 위에 층간 절연막(IDL3; 2)을 증착한 후, DC Fail 발생의 원인이 되는 CMP 공정을 생략하게 될 경우에는, 도 1에 도시된 것과 같이 metal residue가 쌓이게 되는 문제가 발생하게 된다.In the case where the etching process is performed on the plate 1, the interlayer insulating film IDL3 is deposited thereon, and the CMP process, which causes DC fail, is omitted, as shown in FIG. The problem is that residues accumulate.
종래 방식에 따른 상술한 문제들에 착안하여, 본원 발명은 경사 식각 방식을 적용하여 플레이트 에칭 공정을 수행함으로써, 과도 식각 또는 찌꺼기 발생의 원인이 될 수 있는 CMP 공정을 생략할 수 있고 결과적으로 DC Fail 발생 가능성을 감소시키는 것을 목적으로 한다.In view of the above-described problems according to the conventional method, the present invention can omit the CMP process that may cause excessive etching or debris by performing a plate etching process by applying a gradient etching method and consequently DC Fail It aims to reduce the possibility of occurrence.
이러한 DC Fail 문제를 해결하기 위하여, 본원 발명은 반도체 소자 제조 방법에 관한 것으로서, 반도체 소자 기판 상에 플레이트를 증착하는 제1 단계, 상기 플레이트에 대하여 선택적으로 식각 공정을 수행하되, 식각 면을 경사가 지게 하는 경사 식각 방식을 적용하는 제2 단계 및 상기 경사 식각된 플레이트의 상부에 층간 절연막을 증착하는 제3 단계를 포함하여, 상기 제3단계 이후에 후속 CMP 공정을 생략할 수 있도록 하는 것을 특징으로 한다.In order to solve the DC Fail problem, the present invention relates to a method for manufacturing a semiconductor device, the first step of depositing a plate on a semiconductor device substrate, and selectively performing an etching process for the plate, the inclined etching surface And a third step of applying an inclined etching method and a third step of depositing an interlayer insulating film on the inclined etched plate, so that a subsequent CMP process can be omitted after the third step. do.
도 2a 내지 2c는 본원 발명의 특징을 설명하기 위한 도면이다.2A to 2C are views for explaining features of the present invention.
본원 발명의 실시예에 따르면, 플레이트(10)가 준비되고(도 2a), 이런 플레이트(10)에 대하여 경사 식각을 수행하여 필요한 부분만 남기면, 도 2b에 도시된 바와 같다. 여기서, 플레이트 경사 식각을 수행하는 방법에 대한 본원 발명의 바람직한 실시예에 따르면, 플레이트에 대한 경사 식각을 확보하기 위해서 Cl2을 기반으로 한 기본 가스에 N2, HBr, BCl3를 추가하여 챔버 분위기를 조성하는 것이 좋다. 또는, 플레이트 식각 챔버의 전극의 온도는 섭씨 20도 이하로 조정하는 것이 바람직하다.According to an embodiment of the present invention, if the plate 10 is prepared (FIG. 2A), and only the necessary portions are left by performing an oblique etching on the plate 10, as shown in FIG. 2B. Here, according to a preferred embodiment of the present invention for the method of performing the plate gradient etching, the chamber atmosphere by adding N 2 , HBr, BCl 3 to the base gas based on Cl 2 to secure the gradient etching on the plate It is good to make up. Alternatively, the temperature of the electrode of the plate etching chamber is preferably adjusted to 20 degrees Celsius or less.
경사 식각을 수행한 후에 후속되는 공정으로, 층간 절연막(20)을 증착하게 된다. 이렇게 플레이트에 대하여 경사 식각을 수행하면, 층간 절연막 증착 후에 후속되는 CMP 공정을 생략하더라도 종래 방식과 달리 metal residue를 발생시키지 않게 된다(도 2c 참조).In the subsequent process after the inclined etching is performed, the interlayer insulating film 20 is deposited. When the etching is performed on the plate as described above, the metal residue is not generated unlike the conventional method even if the subsequent CMP process is omitted after the interlayer insulating film deposition (see FIG. 2C).
결과적으로, 플레이트에 대하여 경사 식각 방식을 적용하면 종래의 방식에서의 metal residue 문제는 발생하지 않으면서도, CMP 공정을 skip함으로써 DC Fail 발생 확률을 줄일 수 있게 된다.As a result, when the gradient etching method is applied to the plate, the possibility of DC fail can be reduced by skipping the CMP process without the problem of metal residue in the conventional method.
본원 발명의 이러한 특징에 따르면, 반도체 소자를 제조하는 공정 중에서 추가적인 장비를 구매하지 않고도 DC Fail을 감소시킴으로써, 반도체 소자의 수율을 향상시킬 수 있게 된다.According to this aspect of the invention, it is possible to improve the yield of the semiconductor device by reducing the DC Fail without purchasing additional equipment in the process of manufacturing the semiconductor device.
도 1은 종래의 일반적인 평면 식각을 사용한 예를 도시한 도면.1 is a view showing an example using a conventional general planar etching.
도 2a, 도 2b 및 도 2c는 본원 발명의 특징에 따른 경사 식각을 설명하기 위한 도면.2A, 2B and 2C are diagrams for explaining inclined etching according to a feature of the present invention.
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KR1020040022154A KR100569546B1 (en) | 2004-03-31 | 2004-03-31 | Method of fabricating semiconductor device |
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KR1020040022154A KR100569546B1 (en) | 2004-03-31 | 2004-03-31 | Method of fabricating semiconductor device |
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CN110571148A (en) * | 2019-07-18 | 2019-12-13 | 珠海格力电器股份有限公司 | Processing method of power semiconductor device and power semiconductor device |
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CN110571148A (en) * | 2019-07-18 | 2019-12-13 | 珠海格力电器股份有限公司 | Processing method of power semiconductor device and power semiconductor device |
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