KR20050073099A - Method for manufacturing transistor - Google Patents
Method for manufacturing transistor Download PDFInfo
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- KR20050073099A KR20050073099A KR1020040001286A KR20040001286A KR20050073099A KR 20050073099 A KR20050073099 A KR 20050073099A KR 1020040001286 A KR1020040001286 A KR 1020040001286A KR 20040001286 A KR20040001286 A KR 20040001286A KR 20050073099 A KR20050073099 A KR 20050073099A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 4
- 230000000903 blocking effect Effects 0.000 claims abstract description 3
- 239000007772 electrode material Substances 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 2
- 238000002407 reforming Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02469—Group 12/16 materials
- H01L21/02472—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 필드 산화막에 의해 셀 및 페리 영역이 분리된 실리콘 기판에 제 1 게이트 산화막 및 제 2 게이트 전극 물질을 증착한 후 식각 공정으로 제 1 게이트를 형성하는 단계와; 상기 게이트가 매립되도록 산화막을 증착하는 단계와; 상기 페리 영역과 필드 산화막 상의 제 1 게이트가 블로킹 되도록 포토레지스트 패턴을 형성하는 단계와; 상기 셀 영역의 제 1 게이트 상부가 노출되도록 에치백 한 후 상기 포토레지스트 패턴을 제거하는 단계와; 상기 산화막을 블로킹 막으로 셀 영역의 제 1 게이트를 제거하는 단계와; 상기 제 1 게이트가 제거된 부분을 소정 깊이 리세스시킨 후 채널 이온 주입을 실시하는 단계와; 상기 리세스된 영역에 제 2 게이트 산화막과 제 2 게이트 물질을 증착하고 에치백 하는 단계와; 상기 산화막을 제거하는 단계를 포함하여 구성된다.The present invention includes forming a first gate by an etching process after depositing a first gate oxide film and a second gate electrode material on a silicon substrate having cell and ferry regions separated by field oxide films; Depositing an oxide film so that the gate is buried; Forming a photoresist pattern such that the first gate on the ferry region and the field oxide film is blocked; Removing the photoresist pattern after etching back to expose the upper portion of the first gate of the cell region; Removing the first gate of the cell region using the oxide film as a blocking film; Performing channel ion implantation after recessing the portion from which the first gate is removed to a predetermined depth; Depositing and etching back a second gate oxide film and a second gate material in the recessed region; And removing the oxide film.
상기와 같이 구성되는 본 발명의 MOS 트랜지스터 제조 방법은, 셀 영역의 게이트를 제거하고 채널 영역을 소정 깊이 리세스 시켜 채널 이온 주입을 하고 셀 게이트를 재형성함으로써, 게이트와 채널을 완벽하게 오버랩 시켜 소자의 라프레시 특성을 향상시킬 수 있다. In the MOS transistor fabrication method of the present invention configured as described above, the gate and the channel are completely overlapped by removing the gate of the cell region, recessing the channel region to a predetermined depth, implanting channel ions, and reforming the cell gate. Can improve the refreshing characteristics.
Description
본 발명은 트랜지스터 제조 방법에 관한 것으로, 보다 상세하게는 실리콘 기판을 소정 깊이 리세스 시켜 게이트와 채널을 형성하는 RCAT(Recess-Channel-Array Transistor)에 있어서 게이트와 채널의 오버랩 특성을 향상시키기 위한 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor, and more particularly, a transistor for improving overlapping characteristics of a gate and a channel in a recess-channel-array transistor (RCAT) that forms a gate and a channel by recessing a silicon substrate to a predetermined depth. It relates to a manufacturing method.
최근, 소자의 집적도 증가에 따라 실리콘 기판을 일부 리세스 시켜 리세스된 영역에 게이트를 형성하고 게이트의 양측 실리콘 기판에 채널을 형성하는 ECAT(Recess-Channel-Array Transistor} 기술이 적용되어 리프레시 타임을 향상시킬 수 있게되었다. 그런데, 이러한 RCAT 구조를 이용할 경우 게이트와 채널이 오버랩되는 문제점이 발생하게 된다. Recently, a recess-channel-array transistor (ECAT) technique is applied to partially recess a silicon substrate to form a gate in a recessed region and to form a channel in the silicon substrate on both sides of the gate, as the integration density of the device increases. However, when the RCAT structure is used, the gate and the channel overlap with each other.
이러한 종래 기술에 의한 RCAT 구조 트랜지스터 제조 방법의 문제점을 하기 도면을 참조하여 설명하도록 한다.The problem of the RCAT structure transistor manufacturing method according to the prior art will be described with reference to the following drawings.
도1a 내지 도1c는 종래 기술에 의한 트랜지스터 제조 방법을 나타낸 개략적인 공정 순서도이다.1A to 1C are schematic process flowcharts showing a transistor manufacturing method according to the prior art.
우선, 도1a에 도시된 바와 같이 실리콘 기판(100)에 통상의 소자 분리 공정으로 필드 산화막(102)을 형성하여 셀 영역과 페리 영역은 구분한다. 그리고 나서, 소정의 포토레지스트 패턴(PR)을 형성하여 셀 영역의 실리콘 기판의 채널 예정 영역에 소정 깊이의 트렌치(104)를 형성한다.First, as shown in FIG. 1A, a field oxide film 102 is formed on a silicon substrate 100 by a conventional device isolation process to distinguish a cell region and a ferry region. Then, a predetermined photoresist pattern PR is formed to form a trench 104 having a predetermined depth in the channel predetermined region of the silicon substrate in the cell region.
이어서, 도1b에 도시된 바와 같이 게이트 산화막(106)을 형성하고, 그 상부에 게이트 폴리실리콘(106), 텅스텐 실리사이드(108) 및 하드 마스크용 질화막(110)을 차례로 형성한다. 그런 다음, 게이트 패턴을 위한 포토레지스트 패턴(PR)을 형성한다.Subsequently, as shown in FIG. 1B, a gate oxide film 106 is formed, and a gate polysilicon 106, a tungsten silicide 108, and a nitride film 110 for a hard mask are sequentially formed thereon. Then, the photoresist pattern PR for the gate pattern is formed.
이후, 상기 하드 마스크용 질화막(110)을 식각한 후에 하드 마스크용 질화막을 마스크로 이용하여 게이트 식각 공정을 진행하는 RCAT(Recess-Channel-Array Transistor) 기술을 실시한다.Thereafter, after etching the hard mask nitride film 110, a gate-etch process (RCAT) technology is performed using the hard mask nitride film as a mask.
이와 같은 종래 기술에 의한 트랜지스터 제조 방법에 따르면, 게이트 식각 공정시에 사진 식각 상의 문제로 인하여 상기 채널 부분과 게이트간의 오버랩되지 않고 오정렬 되어 패턴의 정확도가 떨어지는 문제점이 발생하게 된다. According to the transistor manufacturing method according to the prior art, due to the problem of the photo-etching during the gate etching process, there is a problem that the accuracy of the pattern is lowered due to misalignment without overlapping between the channel portion and the gate.
상기와 같은 문제점을 해결하기 위한 본 발명은 셀 영역의 게이트를 제거하고 실리콘 기판의 채널 영역을 리세스시킨 다음, 채널 이온 주입을 실시하고 리세스된 영역에 게이트 물질을 증착한 후 에치백으로 셀 게이트를 재형성함으로써, 게이트와 채널의 오버랩되도록 하는 트랜지스터 제조 방법을 제공하기 위한 것이다. In order to solve the above problems, the present invention removes the gate of the cell region, recesses the channel region of the silicon substrate, performs channel ion implantation, deposits the gate material in the recessed region, and then etches the cell. The present invention provides a method of fabricating a transistor in which a gate is overlapped with a channel by reforming the gate.
상기와 같은 목적을 실현하기 위한 본 발명은 필드 산화막에 의해 셀 및 페리 영역이 분리된 실리콘 기판에 제 1 게이트 산화막 및 제 2 게이트 전극 물질을 증착한 후 식각 공정으로 제 1 게이트를 형성하는 단계와; 상기 게이트가 매립되도록 산화막을 증착하는 단계와; 상기 페리 영역과 필드 산화막 상의 제 1 게이트가 블로킹 되도록 포토레지스트 패턴을 형성하는 단계와; 상기 셀 영역의 제 1 게이트 상부가 노출되도록 에치백 한 후 상기 포토레지스트 패턴을 제거하는 단계와; 상기 산화막을 블로킹 막으로 셀 영역의 제 1 게이트를 제거하는 단계와; 상기 제 1 게이트가 제거된 부분을 소정 깊이 리세스시킨 후 채널 이온 주입을 실시하는 단계와; 상기 리세스된 영역에 제 2 게이트 산화막과 제 2 게이트 물질을 증착하고 에치백 하는 단계와; 상기 산화막을 제거하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 제조 방법에 관한 것이다.According to the present invention, a first gate oxide film and a second gate electrode material are deposited on a silicon substrate in which a cell and a ferry region are separated by a field oxide film, followed by forming a first gate by an etching process. ; Depositing an oxide film so that the gate is buried; Forming a photoresist pattern such that the first gate on the ferry region and the field oxide film is blocked; Removing the photoresist pattern after etching back to expose the upper portion of the first gate of the cell region; Removing the first gate of the cell region using the oxide film as a blocking film; Performing channel ion implantation after recessing the portion from which the first gate is removed to a predetermined depth; Depositing and etching back a second gate oxide film and a second gate material in the recessed region; It relates to a transistor manufacturing method comprising the step of removing the oxide film.
상기 본 발명에 의한 트랜지스터 제조 방법에서는, 상기 산화막 증착 이전에 질화막을 증착함으로써, 상기 산화막 제거 시에 필드 산화막을 보호할 수 있다.In the transistor manufacturing method according to the present invention, by depositing a nitride film before the oxide film deposition, it is possible to protect the field oxide film when the oxide film is removed.
또한, 상기 제 1 산화막과 제 2 산화막을 그 두께를 달리 함으로써 추가의 공정 없이 듀얼 게이트 산화막 구조를 형성할 수 있다.In addition, by varying the thicknesses of the first oxide film and the second oxide film, a dual gate oxide film structure may be formed without an additional process.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2a 내지 도2i는 본 발명에 의한 트랜지스터 제조 방법을 나타낸 순차적인 공정 단면도이다.2A to 2I are sequential cross-sectional views showing a transistor manufacturing method according to the present invention.
우선, 도2a에 도시된 바와 같이 실리콘 기판(200)에 통상의 공정으로 필드 산화막(202)을 형성하여 페리 영역과 셀 영역을 분리한 후에 실리콘 기판(200) 상에 게이트 산화막(204)을 형성한다. 그리고, 그 상부에 게이트 폴리실리콘(206), 텅스텐 실리사이드(208)를 형성한 후에 하드 마스크용 질화막(210)을 이용한 식각 공정을 진행하여 게이트를 패터닝 한다.First, as shown in FIG. 2A, the field oxide film 202 is formed on the silicon substrate 200 by a normal process to separate the ferry region and the cell region, and then the gate oxide film 204 is formed on the silicon substrate 200. do. After the gate polysilicon 206 and the tungsten silicide 208 are formed thereon, the gate is patterned by performing an etching process using the nitride film 210 for a hard mask.
이어서, 도2b에 도시된 바와 같이 하부의 필드 산화막(202) 보호막으로 질화막(212)을 증착한 후 결과물 전면에 산화막(214)을 증착하여 게이트 사이를 매립한다. Subsequently, as shown in FIG. 2B, the nitride film 212 is deposited using the protective field oxide 202 under the protective film, and the oxide film 214 is deposited on the entire surface of the resultant to fill the gaps between the gates.
그런 다음, 도2c에 도시된 바와 같이 포토레지스트(216)를 증착한 후 페리 영역과 필드 산화막(202) 상부의 게이트가 블로킹 되도록 사진 공정을 진행한 후에 도2d에 도시된 바와 같이 셀 영역의 게이트 하드 마스크(210)가 노출되도록 에치백 공정을 진행한 후에 셀 영역의 게이트 사이 산화막을 식각 마스크로 이용하여 셀 영역의 게이트를 제거한다.Then, after the photoresist 216 is deposited as shown in FIG. 2C, the photolithography process is performed such that the gate of the ferry region and the field oxide layer 202 is blocked, and then the gate of the cell region is shown in FIG. 2D. After the etch back process is performed to expose the hard mask 210, the gate of the cell region is removed using an oxide film between gates of the cell region as an etching mask.
이어서, 도2e에 도시된 바와 같이 상기 산화막(214)을 식각 마스크로 이용하여 채널 형성 예정 영역의 실리콘 기판을 소정 깊이로 식각하여 트렌치(218)을 형성하고 상기 포토레지스트 패턴(216)을 제거한다. Next, as shown in FIG. 2E, the silicon substrate in the channel formation region is etched to a predetermined depth by using the oxide film 214 as an etching mask to form the trench 218 to remove the photoresist pattern 216. .
그리고 나서, 도2f에 도시된 바와 같이 상기 트렌치(218)에 채널 이온 주입 공정을 진행하고, 트렌치에 셀 게이트 산화막(220) 및 셀 게이트 폴리실리콘(222)을 형성한 후에 에치백 공정을 진행한다. 이때, 상기 트렌치 내부에 형성된 게이트 산화막의 두께가 페리 영역의 게이트 산화막과 다른 두께로 형성이 가능하여 자연스럽게 듀얼 게이트 산화막을 형성할 수 있게 된다. Then, as illustrated in FIG. 2F, a channel ion implantation process is performed in the trench 218, and after the cell gate oxide film 220 and the cell gate polysilicon 222 are formed in the trench, an etch back process is performed. . In this case, the thickness of the gate oxide film formed in the trench may be different from the gate oxide film of the ferry region so that the dual gate oxide film may be naturally formed.
그런 다음, 도2g에 도시된 바와 같이 셀 게이트 텅스텐 실리사이드(224) 및 셀 게이트 하드 마스크용 질화막(226)을 증착하고 에치백 공정을 진행하고, 도2h에 도시된 바와 같이 상기 산화막(214)을 습식 식각 공정을 제거한다. 이때, 상기 습식 식각 공정시 상기 필드 산화막(202)은 질화막(210)에 의해 보호되어 있어 식각되지 않는다.Then, as shown in FIG. 2G, the cell gate tungsten silicide 224 and the nitride film 226 for the cell gate hard mask are deposited, and an etch back process is performed. As shown in FIG. Remove the wet etch process. In this case, the field oxide layer 202 is protected by the nitride layer 210 and is not etched during the wet etching process.
이후, 도2i에 도시된 바와 같이 질화막(210)을 제거하면 게이트와 채널 간에 오버랩 발생하지 않는 RACT 구조를 형성할 수 있다.Thereafter, as shown in FIG. 2I, when the nitride film 210 is removed, an RACT structure may not be formed between the gate and the channel.
상기한 바와 같이 본 발명은 셀 영역의 채널 예정 영역의 게이트를 제거하고 실리콘 기판을 리세스한 후에 채널 이온 주입을 실시하고 셀 게이트를 재형성함으로써, 채널과 게이트가 완벽하게 오버랩 되도록 할 수 있어 정렬의 정확도가 향상되는 이점이 있다.As described above, according to the present invention, the channel and the gate can be completely overlapped by removing the gate of the channel predetermined region of the cell region, recessing the silicon substrate, and performing channel ion implantation and reforming the cell gate. There is an advantage that the accuracy of the is improved.
또한, 리세스된 셀 영역의 실리콘 기판에 셀 게이트 산화막을 재형성함으로써 페리 영역의 게이트 산화막과 두께를 달리할 수 있어 듀얼 게이트 산화막 구조를 형성할 수 있는 이점이 있다. In addition, by reforming the cell gate oxide film on the silicon substrate of the recessed cell region, the thickness of the cell gate oxide layer may be different from that of the ferry region, thereby forming a dual gate oxide layer structure.
도1a 내지 도1c는 종래 기술에 의한 트랜지스터 제조 방법을 나타낸 개략적인 공정 순서도이다.1A to 1C are schematic process flowcharts showing a transistor manufacturing method according to the prior art.
도2a 내지 도2i는 본 발명에 의한 트랜지스터 제조 방법을 나타낸 순차적인 공정 단면도이다.2A to 2I are sequential cross-sectional views showing a transistor manufacturing method according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 - -Explanation of symbols for the main parts of the drawings-
200 : 실리콘 기판 202 : 필드 산화막200: silicon substrate 202: field oxide film
204 : 제 1 게이트 산화막 206 : 폴리실리콘204: first gate oxide film 206: polysilicon
208 : 텅스텐 실리사이드 210 : 하드 마스크208: tungsten silicide 210: hard mask
212 : 질화막 214 : 산화막212: nitride film 214: oxide film
218 : 트렌치 220 : 셀 게이트 산화막218 trench 220 cell gate oxide film
222 : 셀 게이트 폴리실리콘 222: cell gate polysilicon
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| KR10-2004-0001286A KR100533394B1 (en) | 2004-01-08 | 2004-01-08 | Method for manufacturing Transistor |
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| KR10-2004-0001286A KR100533394B1 (en) | 2004-01-08 | 2004-01-08 | Method for manufacturing Transistor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100704475B1 (en) * | 2005-12-28 | 2007-04-09 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with dual poly recess gate |
| KR100801315B1 (en) * | 2006-09-29 | 2008-02-05 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device with the finfet transistor |
| KR100881729B1 (en) * | 2007-06-27 | 2009-02-06 | 주식회사 하이닉스반도체 | Semiconductor dvice and method for manufacturing of the same |
| US7595529B2 (en) | 2007-02-21 | 2009-09-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same |
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2004
- 2004-01-08 KR KR10-2004-0001286A patent/KR100533394B1/en not_active IP Right Cessation
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100704475B1 (en) * | 2005-12-28 | 2007-04-09 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with dual poly recess gate |
| US7381605B2 (en) | 2005-12-28 | 2008-06-03 | Hynix Semiconductor, Inc. | Method for fabricating semiconductor device with dual poly-recess gate |
| KR100801315B1 (en) * | 2006-09-29 | 2008-02-05 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device with the finfet transistor |
| US7915108B2 (en) | 2006-09-29 | 2011-03-29 | Hynix Semiconductor Inc. | Method for fabricating a semiconductor device with a FinFET |
| US7595529B2 (en) | 2007-02-21 | 2009-09-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same |
| US7745876B2 (en) | 2007-02-21 | 2010-06-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same |
| US8872262B2 (en) | 2007-02-21 | 2014-10-28 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gates having connection lines thereon |
| US9299827B2 (en) | 2007-02-21 | 2016-03-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gates having connection lines thereon |
| KR100881729B1 (en) * | 2007-06-27 | 2009-02-06 | 주식회사 하이닉스반도체 | Semiconductor dvice and method for manufacturing of the same |
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| KR100533394B1 (en) | 2005-12-06 |
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