KR20050009896A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20050009896A KR20050009896A KR1020030049250A KR20030049250A KR20050009896A KR 20050009896 A KR20050009896 A KR 20050009896A KR 1020030049250 A KR1020030049250 A KR 1020030049250A KR 20030049250 A KR20030049250 A KR 20030049250A KR 20050009896 A KR20050009896 A KR 20050009896A
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- Prior art keywords
- mim
- lower metal
- gas
- film
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 69
- 239000010410 layer Substances 0.000 claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000007769 metal material Substances 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 31
- 239000000654 additive Substances 0.000 claims description 5
- 230000000996 additive effect Effects 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000008239 natural water Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 230000000737 periodic effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- 239000012212 insulator Substances 0.000 abstract description 4
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052701 rubidium Inorganic materials 0.000 description 2
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 2
- 229910052712 strontium Inorganic materials 0.000 description 2
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical group FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052799 carbon Chemical group 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011737 fluorine Chemical group 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 MIM(Metal/Insulator/Metal) 구조의 캐패시터의 하부전극과 상부전극 간의 브릿지(bridge)가 발생되는 것을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing a bridge between a lower electrode and an upper electrode of a capacitor having a metal / insulator / metal (MIM) structure. will be.
아날로그(analog) 반도체 소자의 필수 구성요소인 캐패시터(capacitor)는 DRAM(Dynamic Random Access Memory)의 캐패시터와 달리 신호지연(signal delay) 역할을 한다. 그 구조는 일반적으로 폴리실리콘막/절연막/폴리실리콘막 구조나 금속층/절연막/금속층 구조가 채택되어 사용되고 있다. 특히, 금속층/절연막/금속층 (Metal/Insulator/Metal; 이하, 'MIM'이라 함)구조를 형성하기 위한 반도체 공정 재현시 상부(top) 금속층 식각공정후, 인-시튜(in-situ) 포토레지스트 패턴(photoresist pattern) 스트립 공정(strip)이 진행되는데, 이는 상부 금속층 식각공정시 식각용액(etchant)인 Cl2, BCl3등에 함유된 염소(chlorine)가 포토레지스트와 상부 금속층 측벽에 남아 있다가 대기중 노출시 H2O와 반응하여 HCl이 형성되고, 이 HCl에 의한 부식이 발생되기 때문이다. 따라서, 후속공정인 절연막 식각공정시에는 상부 금속층에서 TiN이 베리어(barrier)막으로 이용되는데, 이때, 상부 금속층의 손실(loss)에 의해 상부 금속층과 하부 금속층 사이에 식각 부산물 등에 의한 브릿지(bridge; 도 6의 'A'참조) 현상이 부분적으로 발생하게 되고, 이는 캐패시터의 누설전류(leakage current) 성분으로 작용하여 MIM 등의 특성에 민감한영향을 주게 된다. 이를 제거하기 위한 복잡한 공정들이 반복적으로 이루어져야 하며, 턴-어라운드-타임(turn-around-time)(즉, 웨이퍼가 팹-인(fab-in)된 후 팹-아웃(fab-out)되는 시간) 등, 원가 차원에서 제품의 경쟁력을 떨어뜨리는 결과가 초래된다.A capacitor, which is an essential component of an analog semiconductor device, acts as a signal delay unlike a capacitor of a dynamic random access memory (DRAM). Generally, the structure employs a polysilicon film / insulation film / polysilicon film structure or a metal layer / insulation film / metal layer structure. In particular, in-situ photoresist after a top metal layer etching process during semiconductor process reproduction to form a metal layer / insulation film / metal layer (hereinafter referred to as “MIM”) structure. The photoresist pattern strip process is performed. In the upper metal layer etching process, chlorine contained in the etchant Cl 2 , BCl 3, etc. remains on the photoresist and the upper metal layer sidewall, and then atmosphere. This is because HCl is formed by reaction with H 2 O during heavy exposure, and corrosion by HCl is generated. Therefore, in the subsequent insulating film etching process, TiN is used as a barrier film in the upper metal layer. In this case, a bridge is formed between the upper metal layer and the lower metal layer by an etching by-product due to a loss of the upper metal layer; The phenomenon of 'A' of FIG. 6 occurs partially, which acts as a leakage current component of the capacitor, thereby affecting sensitive characteristics of the MIM. Complex processes to eliminate this have to be repeated, turn-around-time (ie the time the wafer is fab-out after it is fab-in). As a result, the competitiveness of the product in terms of cost is reduced.
따라서, 본 발명의 바람직한 실시예는 MIM(Metal/Insulator/Metal) 구조의 캐패시터의 하부전극과 상부전극 간의 브릿지(bridge)가 발생되는 것을 방지하는데 그 목적이 있다.Accordingly, a preferred embodiment of the present invention is to prevent the bridge between the lower electrode and the upper electrode of the capacitor of the MIM (Metal / Insulator / Metal) structure.
도 1 내지 도 5는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 도시된 단면도들이다.1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
도 6은 종래기술에 따라 발생되는 금속성 폴리머(metallic polymer)에 의한 MIM 구조의 캐패시터의 하부전극과 상부전극 간에 발생되는 브릿지(bridge)가 도시된 TEM(Transmission Electon Microscope) 사진이다.FIG. 6 is a transmission electron microscope (TEM) photograph showing a bridge generated between a lower electrode and an upper electrode of a capacitor of a MIM structure by a metallic polymer generated according to the prior art.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
10 : 반도체 기판 12 : 반도체 구조물층10 semiconductor substrate 12 semiconductor structure layer
14 : 하부 금속배선 16 : 반사방지막14 lower metal wiring 16 antireflection film
18 : 절연막 20, 22, 26 : 포토레지스트 패턴18: insulating film 20, 22, 26: photoresist pattern
24 : 층간절연막 28 : 콘택홀24: interlayer insulating film 28: contact hole
30: 금속 플러그 32 : 상부 금속배선30: metal plug 32: upper metal wiring
본 발명의 일측면에 따르면, MIM 구조의 캐패시터가 형성되는 MIM부와 하부 금속배선이 형성되는 하부 금속배선부로 정의되는 반도체 기판이 제공되는 단계와, 상기 반도체 기판 상에 금속층, 반사방지막 및 절연막이 순차적으로 증착되는 단계와, 제1 포토레지스트 패턴을 이용한 식각공정을 실시하여 상기 MIM 부에만 상기 절연막이 잔류되도록 패터닝되는 단계와, 제2 포토레지스트 패턴을 이용한 식각공정을 실시하여 상기 금속층이 패터닝되어 상기 MIM부에는 하부전극이 형성되고, 상기 하부 금속배선부에는 하부 금속배선이 형성되는 단계와, 전체 구조 상부에 층간절연막이 증착되는 단계와, 제3 포토레지스트 패턴을 이용한 식각공정을 실시하여 상기 MIM부에서는 상기 절연막이 노출되고, 상기 하부 금속배선부에서는 상기 반사방지막이 노출되도록 상기 층간절연막이 패터닝되어 콘택홀이 형성되는 단계와, 상기 콘택홀이 갭 필링되도록 금속물질이 증착된 후 평탄화되어 상기 MIM부에는 상부전극이 형성되고, 상기 하부 금속배선부에는 금속 플러그가 형성되는 반도체 소자의 제조방법이 제공된다.According to an aspect of the present invention, there is provided a semiconductor substrate defined by a MIM portion in which a capacitor having a MIM structure is formed and a lower metal wiring portion in which a lower metal wiring is formed, and wherein a metal layer, an antireflection film, and an insulating film are formed on the semiconductor substrate. Sequentially depositing, performing an etching process using a first photoresist pattern, patterning the insulating film to remain only in the MIM portion, and performing an etching process using a second photoresist pattern, and patterning the metal layer. A lower electrode is formed on the MIM portion, a lower metal wiring is formed on the lower metal wiring portion, an interlayer insulating film is deposited on the entire structure, and an etching process using a third photoresist pattern is performed. The insulating film is exposed in the MIM part and the anti-reflection film is exposed in the lower metal wiring part. Forming a contact hole by patterning the interlayer insulating layer, and depositing a metal material so that the contact hole is gap-filled and planarized to form an upper electrode on the MIM portion, and a metal plug on the lower metal wiring portion. A method for manufacturing a semiconductor device is provided.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.
도 1 내지 도 5는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 도시된 단면도들이다. 여기서, 도 1 내지 도 5에 도시된 참조부호들 중 서로 동일한 참조부호는 동일한 기능을 하는 동일한 구성요소를 가리킨다.1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 5 indicate the same components having the same function.
도 1을 참조하면, MIM 구조의 캐패시터가 형성되는 MIM부(A)와 하부 금속배선이 형성되는 하부 금속배선부(B)로 정의되는 반도체 기판(10)이 제공된다. 이후, 상기 반도체 기판(10) 상에는 소정의 반도체 구조물층(12)이 형성된다. 이때, 상기 반도체 구조물층(12)은 트랜지스터, 메모리 셀, 캐패시터, 접합층 및 도전층 등이 포함될 수 있다. 이후, 상기 반도체 구조물층(12) 상에는 금속물질로 하부 금속배선(14)이 형성된다. 이때, 상기 하부 금속배선(14)은 Cu(copper), Al(Aluminum), Pt(Platinum), Pd(Palladium), Ru(Rubidium), St(Strontium), Rh(Rhadium) 및Co(Cobalt) 중 어느 하나로 형성될 수 있다. 바람직하게는 구리 원자가 0.05 내지 5% 함유된 Al으로 형성된다.Referring to FIG. 1, a semiconductor substrate 10 defined by a MIM portion A in which a capacitor having a MIM structure is formed and a lower metal wiring portion B in which a lower metal wiring is formed is provided. Thereafter, a predetermined semiconductor structure layer 12 is formed on the semiconductor substrate 10. In this case, the semiconductor structure layer 12 may include a transistor, a memory cell, a capacitor, a junction layer, and a conductive layer. Thereafter, a lower metal wiring 14 is formed of a metal material on the semiconductor structure layer 12. At this time, the lower metal wiring 14 is Cu (copper), Al (Aluminum), Pt (Platinum), Pd (Palladium), Ru (Rubidium), St (Strontium), Rh (Rhadium) and Co (Cobalt) It can be formed of either. Preferably, it is formed from Al containing 0.05 to 5% of copper atoms.
이어서, 상기 하부 금속배선(14) 상에는 반사방지막(hard mask; 16)가 형성된다. 이때, 상기 반사방지막(16)는 Ti, TiN, Ta 및 TaN 중 어느 하나의 단일막이거나, 이 들이 적층된 복합막일 수도 있다. 이어서, 상기 반사방지막(16) 상에는 절연막(18)이 형성된다. 이때, 상기 절연막(18)은 실리콘 질화막(silicon nitride), 실리콘 산화질화막(silicon oxynitride), Ta2O5또는 SiO2등의 단일막 또는 이 들이 적층된 적층막일 수도 있다.Subsequently, a hard mask 16 is formed on the lower metal wiring 14. In this case, the anti-reflection film 16 may be a single film of any one of Ti, TiN, Ta, and TaN, or may be a composite film in which they are stacked. Subsequently, an insulating film 18 is formed on the antireflection film 16. In this case, the insulating film 18 may be a single film such as silicon nitride, silicon oxynitride, Ta 2 O 5 or SiO 2 , or a stacked film in which these layers are stacked.
이어서, 전체 구조 상부에는 포토레지스트(photoresist)가 도포된 후 포토 마스크(photo mask)를 이용한 노광공정 및 현상공정을 순차적으로 실시하여 포토레지스트 패턴(20)이 형성된다. 이후, 상기 포토레지스트 패턴(20)을 식각 마스크로 이용한 식각공정을 실시하여 상기 하부 금속배선부(B)의 반사방지막(16)이 노출되도록 상기 절연막(18)이 패터닝된다. 이때, 상기 식각공정은 CxFyHz(x,y,z는 0 또는 자연수) 가스를 주(main) 식각가스로 이용하고, O2, N2, SF6, Ar, He 등의 첨가가스를 이용하여 실시된다.Subsequently, after the photoresist is applied to the entire structure, the photoresist pattern 20 is formed by sequentially performing an exposure process and a development process using a photo mask. Thereafter, the insulating layer 18 is patterned to perform an etching process using the photoresist pattern 20 as an etching mask so that the anti-reflection film 16 of the lower metal wiring part B is exposed. At this time, the etching process using C x F y H z (x, y, z is 0 or natural water) gas as the main etching gas, the addition of O 2 , N 2 , SF 6 , Ar, He, etc. It is carried out using gas.
도 2를 참조하면, 도 1에서 식각 마스크로 사용된 상기 포토레지스트 패턴(20)은 스트립 공정(strip)을 통해 제거된다. 이후, 전체 구조 상부에는 또 다른 포토레지스트가 도포된 후 포토 마스크를 이용한 노광공정 및 현상공정을 순차적으로 실시하여 포토레지스트 패턴(22)이 형성된다. 이후, 상기 포토레지스트 패턴(22)을 식각 마스크로 이용한 식각공정을 실시하여 하부 금속배선부(B)의 상기 반사방지막(16) 및 하부 금속배선(14)이 패터닝된다. 이때, 상기 식각공정은 건식식각방식으로 실시되며, Cl2, BCl3등이 주 식각가스로 이용되고, O2, N2, SF6, HBr, Ar, He 등이 첨가가스로 이용된다.Referring to FIG. 2, the photoresist pattern 20 used as an etching mask in FIG. 1 is removed through a strip process. Thereafter, another photoresist is applied on the entire structure, and then a photoresist pattern 22 is formed by sequentially performing an exposure process and a development process using a photomask. Thereafter, an etching process using the photoresist pattern 22 as an etching mask is performed to pattern the anti-reflection film 16 and the lower metal wiring 14 of the lower metal wiring part B. At this time, the etching process is carried out by a dry etching method, Cl 2 , BCl 3 and the like is used as the main etching gas, O 2 , N 2 , SF 6 , HBr, Ar, He and the like is used as the additive gas.
도 3을 참조하면, 도 3에서 사용된 상기 포토레지스트 패턴(22)은 스트립 공정을 통해 제거된다. 이후, 전체 구조 상부에는 층간절연막(24)이 형성된다. 이때, 상기 층간절연막(24)은 BPSG(Boron Phosphorus Silicate Glass), PSG(Phosphorus Silicate Glass), PETEOS(Plasma Enhanced Tetra Ethyle Ortho Silicate), USG(Un-doped Silicate Glass), FSG(Fluorinated Silicate Glass), SiO2막이거나, SiO2에 수소, 불소 또는 탄소 등이 결합된 산화막일 수 있다. 또한, 상기 층간절연막(24)은 상기 물질들이 단일막으로 형성되거나, 적어도 2층 이상 적층된 복합 구조로 형성될 수도 있다. 이후, 상기 층간절연막(24)은 평탄화공정을 통해 평탄화된다. 이때, 상기 평탄화공정은 CMP(Chemical Mechanical Polishing) 방식으로 실시되는 것이 바람직하다.Referring to FIG. 3, the photoresist pattern 22 used in FIG. 3 is removed through a strip process. Thereafter, an interlayer insulating film 24 is formed on the entire structure. In this case, the interlayer insulating layer 24 may include boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), plasma enhanced tetra thyle ortho silicate (peteos), un-doped silicate glass (USG), fluorinated silicate glass (FSG), It may be an SiO 2 film or an oxide film in which hydrogen, fluorine or carbon is bonded to SiO 2 . In addition, the interlayer insulating layer 24 may be formed of a single layer or a complex structure in which at least two layers are stacked. Thereafter, the interlayer insulating film 24 is planarized through a planarization process. At this time, the planarization process is preferably carried out by a chemical mechanical polishing (CMP) method.
이어서, 전체 구조 상부에는 포토레지스트가 도포된 후 포토 마스크를 이용한 노광공정 및 현상공정을 실시하여 포토레지스트 패턴(26)이 형성된다. 이후, 상기 포토레지스트 패턴(26)을 이용한 식각공정을 실시하여 콘택홀(28) 또는 비아홀(via hole)이 형성된다. 이때, 상기 식각공정은 건식식각방식으로 실시되며, CxFyHz(x,y,z는 0 또는 자연수) 가스를 주 식각가스로 이용하고, O2, N2, SF6, Ar, He등의 첨가가스를 이용하여 실시된다. 이때, CxFyHz가스의 x/y 값을 크게 하면, 절연막(18)에 대한 높은 선택비를 얻을 수 있으며, 첨가가스, 예컨대, O2가스 등의 첨가비율을 감소시키면 x/y 값을 크게 하는 효과가 있다. 상기 콘택홀(28)은 MIM부(A) 및 하부 금속배선부(B)에 모두 형성된다.Subsequently, after the photoresist is applied on the entire structure, an exposure process and a development process using a photomask are performed to form a photoresist pattern 26. Thereafter, an etching process using the photoresist pattern 26 is performed to form contact holes 28 or via holes. At this time, the etching process is carried out by a dry etching method, using C x F y H z (x, y, z is 0 or natural water) gas as the main etching gas, O 2 , N 2 , SF 6 , Ar, It is carried out using an additive gas such as He. In this case, when the x / y value of the C x F y H z gas is increased, a high selectivity to the insulating film 18 may be obtained, and when the addition ratio of the additive gas, for example, O 2 gas or the like is reduced, x / y The effect is to increase the value. The contact hole 28 is formed in both the MIM portion (A) and the lower metal wiring portion (B).
도 4를 참조하면, 도 3에서 형성된 상기 콘택홀(28)이 갭 필링(gap filling)되도록 금속 플러그(30)용 금속물질이 증착된다. 이때, 상기 금속물질은 텅스텐으로 형성되는 것이 바람직하다. 한편, 상기 금속물질이 증착되기 전에 상기 콘택홀(28) 내부면의 단차를 따라 확산방지막(즉, 접착층/베리어막; 미도시)이 형성될 수도 있다. 이때, 확산방지막은 Ti, TiN, Ta 및 TaN 중 어느 하나의 막으로 형성되거나, 이 들이 적층된 적층막으로 형성될 수 있다. 이후, 전체 구조 상부에 평탄화공정이 실시된다. 이때, 상기 평탄화공정은 식각 마스크없이 SF6, Cl2, BCl3등의 주기율표상 라디칼(radical)족의 원소를 포함한 가스를 이용하여 블랭켓(blanket) 또는 에치백(etch back) 방식으로 실시된다. 이로써, 콘택홀(28)이 매립되도록 금속 플러그(30)가 형성된다. 따라서, MIM부(A)에서는 하부 금속배선(14), 절연막(18) 및 텅스텐 플러그(33)으로 이루어진 MIM 구조의 캐패시터가 형성된다. 즉, MIM부(A)에서 하부 금속배선(14)은 하부전극으로 기능하고, 텅스텐 플러그(33)는 상부전극으로 기능한다.Referring to FIG. 4, a metal material for the metal plug 30 is deposited such that the contact hole 28 formed in FIG. 3 is gap filled. In this case, the metal material is preferably formed of tungsten. Meanwhile, before the metal material is deposited, a diffusion barrier layer (ie, an adhesive layer / barrier layer; not shown) may be formed along the step of the inner surface of the contact hole 28. In this case, the diffusion barrier may be formed of any one of Ti, TiN, Ta, and TaN, or may be formed of a laminated film in which they are stacked. Thereafter, a planarization process is performed on the entire structure. In this case, the planarization process is performed by a blanket or etch back method using a gas containing an element of a radical group of the periodic table such as SF 6 , Cl 2 , BCl 3 without an etching mask. . As a result, the metal plug 30 is formed to fill the contact hole 28. Therefore, in the MIM portion A, a capacitor having a MIM structure formed of the lower metal wiring 14, the insulating film 18, and the tungsten plug 33 is formed. That is, in the MIM unit A, the lower metal wiring 14 functions as a lower electrode, and the tungsten plug 33 functions as an upper electrode.
도 5를 참조하면, 듀얼 다마신 공정(dual damascene) 또는 싱글 다마신 공정(single damascene)을 이용한 배선공정을 실시하여 상부 금속배선(32)이 형성된다. 이때, 상기 상부 금속배선(32)은 Cu(copper), Al(Aluminum), Pt(Platinum), Pd(Palladium), Ru(Rubidium), St(Strontium), Rh(Rhadium) 및 Co(Cobalt) 중 어느 하나로 형성될 수 있다.Referring to FIG. 5, the upper metal wiring 32 is formed by performing a wiring process using a dual damascene process or a single damascene process. At this time, the upper metal wiring 32 is Cu (copper), Al (Aluminum), Pt (Platinum), Pd (Palladium), Ru (Rubidium), St (Strontium), Rh (Rhadium) and Co (Cobalt) It can be formed of either.
상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같이, 본 발명의 바람직한 실시예에 의하면, 하부 금속배선이 형성된 후 상기 하부 금속배선 상에 절연막이 형성되고, 하부 금속배선부에 형성되는 텅스텐 플러그를 MIM(Metal/Insulator/Metal)부에도 그대로 형성하고, 상기 텅스텐 플러그를 MIM 구조의 캐패시터의 상부전극으로 이용함으로써 상기 절연막 식각공정시 상부전극의 손실로 인한 금속성 폴리머(metallic polymer)의 발생이 억제되고, MIM 구조의 캐패시터의 상부전극과 하부전극 간의 브릿지(bridge)현상이 방지된다.As described above, according to the preferred embodiment of the present invention, after the lower metal wiring is formed, an insulating film is formed on the lower metal wiring, and the MIM (Metal / Insulator / Metal) portion of the tungsten plug formed on the lower metal wiring is formed. By forming the same, the tungsten plug is used as the upper electrode of the capacitor of the MIM structure, thereby suppressing the generation of a metallic polymer due to the loss of the upper electrode during the etching process of the insulating film, and the upper electrode of the capacitor of the MIM structure. Bridge phenomenon between the lower electrodes is prevented.
Claims (6)
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