KR20050009036A - Stack package and manufacturing method thereof - Google Patents

Stack package and manufacturing method thereof Download PDF

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Publication number
KR20050009036A
KR20050009036A KR1020030048284A KR20030048284A KR20050009036A KR 20050009036 A KR20050009036 A KR 20050009036A KR 1020030048284 A KR1020030048284 A KR 1020030048284A KR 20030048284 A KR20030048284 A KR 20030048284A KR 20050009036 A KR20050009036 A KR 20050009036A
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South Korea
Prior art keywords
package
chip scale
connection pad
pads
connection
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KR1020030048284A
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Korean (ko)
Inventor
고준영
전종근
신화수
전병석
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삼성전자주식회사
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Priority to KR1020030048284A priority Critical patent/KR20050009036A/en
Publication of KR20050009036A publication Critical patent/KR20050009036A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A stack package and a fabricating method thereof are provided to reduce the fabricating cost by using a chip scale package having same internal structure without changing an internal design structure of the chip scale package. CONSTITUTION: First ad second electrode pads(12,22) are formed around each center of first and second semiconductor chips. First and second wiring substrates(13,23) include first and second windows, an inner connection pad, an outer connection pad(15), and first and second solder bump pads(14,24). First and second bonding wires(17,27) are used for connecting the first and second electrode pads to the inner connection pad through the first and second windows. First sealing parts(51,52) are used for sealing the first and second bonding wires. First and second solder balls(16,26) are adhered to the first and second solder bump pads. First and second chip scale packages includes second sealing parts for sealing the first and second semiconductor chips. A package connection wiring layer(31) is formed on an outer circumference of the second sealing part of the first chip scale package and includes a package connection pad(33) and a package connection wiring(32).

Description

적층 패키지 및 그 제조 방법{Stack package and manufacturing method thereof}Stack package and manufacturing method thereof

본 발명은 적층 패키지(stack package) 및 그 제조 방법에 관한 것으로, 보다 상세하게는 칩 스케일 패키지(chip scale package)가 적층된 적층 패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack package and a method of manufacturing the same, and more particularly, to a stack package in which a chip scale package is stacked and a method of manufacturing the same.

최근의 전자 산업은 더욱 경량화, 소형화, 고속화, 다기능화되고 높은 신뢰성을 갖는 제품을 생산하는 추세이다. 이와 같은 추세에 부응하는 중요한 기술 중의 하나가 바로 패키지 조립 기술이며, 이에 따라 개발된 패키지 중의 하나가 볼 그리드 어레이(Ball Grid Array; 이하 "BGA"라 한다) 패키지이다. BGA 패키지는 통상적인 플라스틱 패키지에 비하여, 모 기판(mother board)에 대한 실장 면적을 축소시킬 수 있고, 전기적 특성이 우수하다는 장점들을 가지고 있다.In recent years, the electronics industry tends to produce products that are lighter, smaller, faster, more versatile, and have higher reliability. One important technology that meets this trend is package assembly technology, and one of the developed packages is a ball grid array (BGA) package. The BGA package has advantages in that the mounting area for the mother board can be reduced and the electrical characteristics are excellent, compared to the conventional plastic package.

BGA 패키지는 리드 프레임 대신에 인쇄 회로 기판을 사용한다. 인쇄 회로 기판은 반도체 칩이 접착되는 면의 반대쪽 전면에 솔더 볼(solder ball)들이 형성되므로 모 기판에 대한 실장 밀도에 있어서 유리하다. 그러나, 인쇄 회로 기판은 반도체 칩의 실장을 위하여 회로 배선이 형성되지 않은 영역을 필요로 하기 때문에 그 크기에 있어 반도체 칩의 크기보다 클 수밖에 없다. 이러한 이유로 제안된 것이 반도체 칩 크기에 보다 근접하는 칩 스케일 패키지(Chip Scale Package)이다.BGA packages use printed circuit boards instead of lead frames. Printed circuit boards are advantageous in terms of mounting density on the parent substrate because solder balls are formed on the front surface opposite to the surface to which the semiconductor chip is bonded. However, since the printed circuit board requires an area where no circuit wiring is formed for mounting the semiconductor chip, the printed circuit board is inevitably larger than the size of the semiconductor chip. For this reason, the proposed chip scale package is closer to the semiconductor chip size.

칩 스케일 패키지는 반도체 칩 크기 수준으로 제조되는 패키지로서, 대표적인 칩 스케일 패키지 중 하나는 유연성을 갖는 폴리이미드 테이프(polyimide tape)에 배선 패턴이 형성된 테이프 배선 기판을 이용한 칩 스케일 패키지이다. 테이프 배선 기판과 테이프 배선 기판에 부착되는 반도체 칩간의 전기적 연결 방법은 빔 리드 본딩(beam lead bonding) 방법과 와이어 본딩(wire bonding) 방법이 일반적으로 사용된다.A chip scale package is a package manufactured at a semiconductor chip size level, and one of the representative chip scale packages is a chip scale package using a tape wiring board having a wiring pattern formed on a flexible polyimide tape. As the electrical connection method between the tape wiring board and the semiconductor chip attached to the tape wiring board, a beam lead bonding method and a wire bonding method are generally used.

한편, 하나의 반도체 칩을 패키징하는 칩 스케일 패키지 이외에도, 예를 들면, 반도체 칩 또는 패키지를 입체적으로 복수개 적층한 패키징 기술이 있다. 이와 같은 적층 패키징 기술에 의해 구현된 패키지를 적층 패키지라 한다.On the other hand, in addition to a chip scale package for packaging one semiconductor chip, for example, there is a packaging technology in which a plurality of semiconductor chips or packages are stacked three-dimensionally. A package implemented by such a lamination packaging technique is called a lamination package.

그런데, 통상적인 반도체 패키지를 적층한 적층 패키지의 경우, 신뢰성 검사를 거친 반도체 패키지를 활용하기 때문에, 적층 패키지로 구현된 이후에 불량률은 적지만 적층되는 반도체 패키지의 두께에 대응되어 적층 패키지의 두께가 두꺼워지는 문제점을 안고 있다. 반도체 칩을 적층하여 적층 패키지를 구현하는 경우, 적층 패키지의 박형화를 구현할 수는 있지만, 적층되는 반도체 칩에 대한 신뢰성이 검증되지 않았기 때문에, 적층 패키지로 구현된 이후에 불량률이 발생될 우려가 크다.However, in the case of a laminated package in which a conventional semiconductor package is laminated, since the semiconductor package has been tested for reliability, since the defect rate is small after being implemented as the laminated package, the thickness of the laminated package corresponds to the thickness of the stacked semiconductor package. There is a problem of thickening. When the stack package is implemented by stacking semiconductor chips, the stack package may be thinned. However, since reliability of the stack semiconductor chip is not verified, a defective rate may be generated after the stack package is implemented.

따라서, 전술된 바와 같은 칩 스케일 패키지를 적층하여 적층 패키지를 구현할 수 있다면, 반도체 패키지를 적층하는 경우의 장점과 반도체 칩을 적층하는 경우의 장점을 모두 획득할 수 있을 것이다. 그러나, 칩 스케일 패키지는 칩 실장 기판에 평면적으로밖에 실장할 수 없기 때문에, 적층 패키지로 구현하기가 용이하지 않다. 즉, 칩 스케일 패키지의 외부 접속 단자로서 활용할 수 있는 솔더 범프가 반도체 칩이 실장된 테이프 배선 기판의 면에 반대되는 면에 형성되어 있고, 다른 접속 수단을 구비하고 있지 않기 때문에, 기존의 칩 스케일 패키지의 구조로는 복수개의 칩 스케일 패키지를 입체적으로 적층하는 것이 용이하지 않다.Therefore, if the stack package can be implemented by stacking the chip scale packages as described above, both advantages of stacking semiconductor packages and stacks of semiconductor chips can be obtained. However, since the chip scale package can only be mounted on the chip mounting substrate in a plan view, it is not easy to implement the chip scale package as a stacked package. That is, since the solder bump which can be utilized as an external connection terminal of a chip scale package is formed in the surface opposite to the surface of the tape wiring board on which the semiconductor chip is mounted, and does not have other connection means, the existing chip scale package It is not easy to three-dimensionally stack a plurality of chip scale packages with the structure of.

이에 의해, 칩 스케일 패키지가 적층된 적층 패키지를 구현하기 위해서는 양산중인 단일 디자인의 칩 스케일 패키지만을 사용하지 못하므로, 칩 스케일 패키지를 적층 방식에 맞도록 내부 설계 구조를 변경하여야 하고, 이러한 칩 스케일 패키지의 설계 구조 변경을 위해서는 새로운 패키지를 다시 제작해야 하므로 이에 따른 비용 및 시간의 소요가 있어 왔다.Accordingly, in order to implement a stacked package in which a chip scale package is stacked, only a single design chip scale package in mass production cannot be used. Therefore, the internal design structure of the chip scale package must be changed to match the stacking method. The design structure of the system has to be rebuilt to a new package, which has been costly and time-consuming.

따라서, 본 발명의 목적은 양산 중인 동일 내부 구조의 칩 스케일 패키지의 내부 설계 구조를 변경하지 않고 적층하는 것이 가능한 적층 패키지 및 그 제조 방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide a laminated package and a method of manufacturing the same, which can be laminated without changing the internal design structure of the chip scale package of the same internal structure in mass production.

도 1 내지 도 5는 본 발명에 따른 적층 패키지 제조 방법에 대한 도이다.1 to 5 are diagrams illustrating a method of manufacturing a laminated package according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10, 20: 제 1, 2칩 스케일 패키지 11, 21: 반도체 칩10, 20: first and second chip scale package 11, 21: semiconductor chip

12, 22: 전극 패드 13, 23: 배선 기판12, 22: electrode pad 13, 23: wiring board

14, 24: 솔더 범프 패드 15, 25: 외부 접속 패드14, 24: solder bump pad 15, 25: external connection pad

16, 26: 솔더 볼 17, 27: 본딩 와이어16, 26: solder ball 17, 27: bonding wire

18, 28: 윈도우 19, 29: 내부 접속 단자18, 28: window 19, 29: internal connection terminal

31: 패키지 접속 배선층 32: 패키지 접속 배선31: package connection wiring layer 32: package connection wiring

33: 패키지 접속 패드 34: 배선 보호층33: package connection pad 34: wiring protective layer

51, 52: 제 1봉지부 53, 54: 제 2봉지부51, 52: 1st sealing part 53, 54: 2nd sealing part

100: 적층 패키지100: laminated package

본 발명에 따른 적층 패키지는, 활성면의 중심 부분을 따라서 전극 패드가 형성된 반도체 칩, 전극 패드를 개방시키는 윈도우(window)가 형성되고 상부면에 형성된 엘라스토머(elastomer)를 통해 반도체 칩이 부착되며 하부면에는 내부 접속 패드와 외부 접속 패드와 솔더 범프 패드를 포함하는 배선 패턴이 형성된 배선 기판, 윈도우를 통하여 전극 패드와 내부 접속 패드를 연결하는 본딩 와이어, 본딩 와이어 부분을 봉지하는 제 1봉지부, 내부 접속 패드와 연결된 각 솔더 범프 패드에 부착된 솔더 볼, 그리고 반도체 칩을 봉지하는 제 2봉지부를 포함하는 제 1 및 제 2칩 스케일 패키지; 및 제 1칩 스케일 패키지의 제 2봉지부의 외주면에 형성되고 제 2칩 스케일 패키지의 솔더 볼이 부착되는 패키지 접속 패드와 제 1칩 스케일의 외부 접속 패드와 패키지 접속 패드들 연결하는 패키지 접속 배선을 포함하는 패키지 접속 배선층; 을 포함한다.In the stack package according to the present invention, a semiconductor chip having electrode pads formed along a center portion of an active surface, a window for opening the electrode pads is formed, and a semiconductor chip is attached through an elastomer formed on an upper surface thereof. A wiring board having a wiring pattern including an internal connection pad, an external connection pad, and a solder bump pad on a surface thereof, a bonding wire connecting the electrode pad and the internal connection pad through a window, and a first encapsulation portion encapsulating the bonding wire portion, the inside First and second chip scale packages including a solder ball attached to each solder bump pad connected to the connection pads, and a second encapsulation portion encapsulating the semiconductor chip; And package connection wirings formed on an outer circumferential surface of the second encapsulation portion of the first chip scale package and connecting the package connection pads to which the solder balls of the second chip scale package are attached, and the external connection pads and the package connection pads of the first chip scale package. A package connection wiring layer; It includes.

그리고, 본 발명에 따른 적층 패키지는 패키지 접속 패드를 제외한 패키지 접속 배선층 상에 형성된 배선 보호층을 더 포함한다.The laminated package according to the present invention further includes a wiring protection layer formed on the package connection wiring layer except for the package connection pad.

상술한 바와 같은 구성에 의해, 내부 설계 구조가 동일한 칩 스케일 패키지를 적층하는 것이 가능하므로, 양산 중인 동일 내부 설계 구조의 칩 스케일 패키지를 이용하여 적층 패키지를 구현하는 것이 가능하다.With the above-described configuration, since it is possible to stack chip scale packages having the same internal design structure, it is possible to implement a stack package using chip scale packages having the same internal design structure in mass production.

또한, 상술한 외부 접속 패드는 제 1 및 2칩 스케일 패키지의 측면으로 외부 개방되고, 제 1칩 스케일 패키지의 외부 접속 패드의 외부 개방면은 제 2칩 스케일 패키지가 적층되는 방향에 대해 경사지도록 형성된다.In addition, the external connection pad described above is opened to the side of the first and second chip scale package, and the external open surface of the external connection pad of the first chip scale package is inclined with respect to the stacking direction of the second chip scale package. do.

또한 상술한 패키지 접속 배선층은 Cu 금속으로 형성될 수 있다.In addition, the above-described package connection wiring layer may be formed of Cu metal.

한편, 본 발명에 따른 적층 패키지의 제조 방법은,On the other hand, the manufacturing method of the laminated package according to the present invention,

(a) 활성면의 중심 부분을 따라서 전극 패드가 형성된 반도체 칩, 전극 패드를 개방시키는 윈도우가 형성되고 상부면에 형성된 엘라스토머를 통해 반도체 칩이 부착되며 하부면에는 내부 접속 패드와 외부 접속 패드와 솔더 범프 패드를 포함하는 배선 패턴이 형성된 배선 기판, 윈도우를 통하여 전극 패드와 내부 접속 패드를 연결하는 본딩 와이어, 본딩 와이어 부분을 봉지하는 제 1봉지부, 내부 접속 패드와 연결된 각 솔더 범프 패드에 부착된 솔더 볼, 그리고 반도체 칩을 봉지하는 제 2봉지부를 포함하는 제 1 및 제 2칩 스케일 패키지를 준비하는 단계;(a) A semiconductor chip with electrode pads formed along a central portion of the active surface, a window for opening the electrode pads is formed, and a semiconductor chip is attached through an elastomer formed on the upper surface, and an inner connection pad, an external connection pad and solder are attached to the lower surface. A wiring board having a wiring pattern including a bump pad, a bonding wire connecting the electrode pad and the internal connection pad through a window, a first encapsulation portion encapsulating the bonding wire portion, and attached to each solder bump pad connected to the internal connection pad. Preparing first and second chip scale packages including a solder ball and a second encapsulation portion encapsulating a semiconductor chip;

(b) 제 1칩 스케일 패키지의 제 2봉지부 외주면에, 제 1칩 스케일 패키지의 외부 접속 패드와 접속되는 패키지 접속 배선 및 패키지 접속 배선과 연결되고 제 2칩 스케일 패키지의 솔더 볼에 대응하는 패키지 접속 패드를 형성하여 패키지 접속 배선층을 형성하는 단계; 및(b) a package corresponding to the solder ball of the second chip scale package, which is connected to the package connection wiring and the package connection wiring connected to the outer peripheral surface of the second encapsulation portion of the first chip scale package; Forming a connection pad to form a package connection wiring layer; And

(c) 제 2칩 스케일 패키지의 솔더 볼과 패키지 접속 패드가 대응되도록 제 2칩 스케일 패키지를 적층하고, 리플로우(reflow) 공정을 진행하여 제 2칩 스케일 패키지의 솔더 볼을 패키지 접속 배선층에 부착시키는 단계; 를 포함하는 것을 특징으로 한다.(c) Laminating the second chip scale package so that the solder balls of the second chip scale package and the package connection pad correspond to each other, and reflow process is performed to attach the solder balls of the second chip scale package to the package connection wiring layer. Making a step; Characterized in that it comprises a.

또한, 본 발명에 따른 적층 패키지의 제조 방법은 패키지 접속 패드를 제외한 패키지 접속 배선층 상에 배선 보호층을 형성하는 단계를 더 포함한다.In addition, the method for manufacturing a laminated package according to the present invention further includes forming a wiring protection layer on the package connection wiring layer except for the package connection pad.

이하 도 5를 참조하여 본 발명에 따른 적층 패키지의 일례에 대해 자세히 설명한다.Hereinafter, an example of a laminated package according to the present invention will be described in detail with reference to FIG. 5.

도 5는 본 발명에 따른 적층 패키지의 단면도이다. 도 5에 도시된 바와 같이, 본 발명의 적층 패키지(100)는 제 1칩 스케일 패키지(10), 제 2칩 스케일 패키지(20), 그리고 제 2칩 스케일 패키지(20)와 접속하는 패키지 접속 패드(33) 및 패키지 접속 패드(33)와 제 1칩 스케일 패키지(20)의 외부 접속 패드(15)를 연결하는 패키지 접속 배선을 포함하는 패키지 접속 배선층(31)을 포함한다. 패키지 접속 패드(33)는 제 2칩 스케일 패키지(20)의 솔더 볼(26)과 접속된다. 제 1칩 스케일 패키지(10)와 제 2칩 스케일 패키지(20)는 그 내부 구조가 동일하나, 제 1칩 스케일 패키지(10)의 외부 접속 패드(15)의 일부가 개방된 측면은 제 2칩 스케일 패키지(20)가 적층된 방향에 대하여 경사지게 형성된다. 제 1칩 스케일 패키지(10)가 기울어진 측면을 가짐으로서, 단일 방향, 즉, 제 2칩 스케일 패키지(20)가 적층되는 방향으로부터의 Cu 도금 및 에칭 작업을 실행하는 것이 가능하여 제 1칩 스케일 패키지(10) 상에 패키지 접속 배선층(31)을 형성하는데 보다 유리하다. 패키지 접속 배선층(31) 상에는 전기 배선 등의 보호를 위해 배선 보호층(32)이 형성된다.배선 보호층(32)은 패키지 접속 배선층(31)의 전(全)면에 형성한 후에 패키지 접속 패드(33) 부분에 홀을 형성하는 방법에 의해 형성될 수 있다.5 is a cross-sectional view of a laminated package according to the present invention. As shown in FIG. 5, the stack package 100 of the present invention is a package connection pad connected to a first chip scale package 10, a second chip scale package 20, and a second chip scale package 20. And a package connection wiring layer 31 including package connection wiring connecting the package connection pad 33 and the external connection pad 15 of the first chip scale package 20. The package connection pad 33 is connected to the solder balls 26 of the second chip scale package 20. Although the internal structure of the first chip scale package 10 and the second chip scale package 20 is the same, the side where the external connection pad 15 of the first chip scale package 10 is opened is the second chip. The scale package 20 is formed to be inclined with respect to the stacked direction. By having the inclined side surface of the first chip scale package 10, it is possible to execute Cu plating and etching operations from a single direction, that is, from the direction in which the second chip scale package 20 is stacked, so that the first chip scale It is more advantageous to form the package connection wiring layer 31 on the package 10. The wiring protection layer 32 is formed on the package connection wiring layer 31 to protect the electric wiring and the like. The wiring protection layer 32 is formed on the entire surface of the package connection wiring layer 31 and then the package connection pad. It can be formed by the method of forming a hole in the part (33).

각 칩 스케일 패지지(10,20)에서 반도체 칩(11,21) 및 배선 기판(13,23) 사이에는 엘라스토머(44,45)가 개재되어 있고, 각 반도체 칩(11,21)은 전극 패드(12,22)가 활성면의 중심 부분에 형성된 센터 패드형 반도체 칩이다. 그리고, 배선 기판(13,23)은 폴리이미드 테이프를 사용한 테이프 배선 기판 또는 인쇄 회로 기판일 수 있다.Elastomers 44 and 45 are interposed between the semiconductor chips 11 and 21 and the wiring boards 13 and 23 in each chip scale package 10 and 20, and each semiconductor chip 11 and 21 has electrode pads. (12, 22) are center pad type semiconductor chips formed in the center portion of the active surface. The wiring boards 13 and 23 may be tape wiring boards or printed circuit boards using polyimide tape.

배선 기판(13,23)에는 윈도우(18,28)가 형성되어 있고, 본딩 와이어(17,27)는 윈도우(18,28)를 관통하여 반도체 칩의 전극 패드(12,22)와 배선 기판(13,23)의 하부면에 형성된 내부 접속 패드(19,29)를 연결하고 있다. 윈도우(18,28) 부분은 본딩 와이어(17,27)가 와이어 본딩된 후 에폭시 등으로 봉지되어 제 1봉지부(51,52)를 형성한다.Windows 18 and 28 are formed in the wiring boards 13 and 23, and the bonding wires 17 and 27 penetrate through the windows 18 and 28 so that the electrode pads 12 and 22 of the semiconductor chip and the wiring board ( The internal connection pads 19 and 29 formed on the lower surfaces of the 13 and 23 are connected. The portions of the windows 18 and 28 are encapsulated with epoxy after the bonding wires 17 and 27 are wire bonded to form the first encapsulation portions 51 and 52.

상술한 바와 같은 구성에 의해 내부 설계 구조가 동일한 칩 스케일 패키지(10,20)들이 적층되고 각 칩 스케일 패키지(10,20)들이 전기적으로 상호 연결된 적층 패키지(100)의 구현이 가능하다.By the above-described configuration, it is possible to implement the stack package 100 in which chip scale packages 10 and 20 having the same internal design structure are stacked and the chip scale packages 10 and 20 are electrically interconnected.

본 발명에 따른 적층 패키지의 제조 방법에 대해 설명하겠다.The manufacturing method of the laminated package which concerns on this invention is demonstrated.

도 1 내지 도 5는 본 발명에 따른 적층 패키지 제조 방법에 대한 도이다.1 to 5 are diagrams illustrating a method of manufacturing a laminated package according to the present invention.

먼저, 적층 패키지를 형성하기 위한 제 1 및 2칩 스케일 패키지를 준비한다((a)단계). 그 중에서, 제 1칩 스케일 패키지를 준비하는 한 방식이 도 1에 도시된다. 일반적으로, 칩 스케일 패키지는 하나의 완제품으로 생산되기 위해개별적으로 한 개씩 제조되는 것이 아니라, 엘라스토머(44)를 통하여 복수의 반도체 칩(11)이 부착된 폴리이미드 테이프(13)에 반도체 칩(11) 및 내부 접속 단자(19)를 연결하는 와이어 본딩 공정을 실시하고, 본딩 와이어(17)를 보호하기 위한 제 1봉지부(51)를 형성하고, 반도체 칩(11)을 보호하기 위한 제 2봉지부(53)를 형성한 후 반도체 칩(11) 사이를 절단하여 개별 칩 스케일 패키지로 생산된다. 단일 칩 스케일 패키지를 형성하기 위해 절단 도구로서 블레이드(blade; 41)를 사용한다.First, first and second chip scale packages for forming a stack package are prepared (step (a)). Among them, one manner of preparing the first chip scale package is shown in FIG. 1. In general, the chip scale packages are not manufactured individually one by one to be produced as one finished product, but the semiconductor chips 11 are attached to the polyimide tape 13 to which the plurality of semiconductor chips 11 are attached through the elastomer 44. ) And a second encapsulation for protecting the semiconductor chip 11 by forming a first encapsulation portion 51 for protecting the bonding wire 17 and a wire bonding process for connecting the internal connection terminals 19. After the portion 53 is formed, the semiconductor chips 11 are cut to produce individual chip scale packages. A blade 41 is used as the cutting tool to form a single chip scale package.

도 1에 도시된 바와 같이, 블레이드(41)는 제조되는 제 1칩 스케일 패키지의 외부 접속 패드(15)의 일부분이 절단면 상에 노출되도록 절단하고, 블레이드(41)의 절단 날의 단면은 V자형인 것이 바람직하다. 외부 접속 패드(15)가 절단면에 노출되고, 블레이드(41)의 절단 날이 V자형으로 형성되면, 절단 후 제 1칩 스케일 패키지(10)의 절단면 및 외부 접속 패드(15)의 외부 노출 부분이 상방에서 봤을 때 보이게 되므로, 패키지 접속 패드 및 패키지 접속 배선을 형성하기 위한 상부 단일 방향으로부터의 Cu 도금 및 에칭을 보다 유리하게 실행하는 것이 가능하다. 여기서, 준비되는 각 칩 스케일 패키지는 신뢰성 검사를 마친 상태이다. 도 1에서의 절단 과정이 완료되면 도 2와 같은 제 1칩 스케일 패키지(10)가 준비된다.As shown in Fig. 1, the blade 41 is cut so that a portion of the external connection pad 15 of the first chip scale package to be manufactured is exposed on the cut surface, and the cross section of the cutting blade of the blade 41 is V-shaped. Is preferably. When the external connection pad 15 is exposed to the cut surface, and the cutting blade of the blade 41 is formed in a V shape, the cut surface of the first chip scale package 10 and the external exposed portion of the external connection pad 15 are cut after cutting. Since it is seen from above, it is possible to more advantageously perform the Cu plating and etching from the upper single direction for forming the package connection pad and the package connection wiring. Here, each of the chip scale packages to be prepared has been tested for reliability. When the cutting process in FIG. 1 is completed, the first chip scale package 10 shown in FIG. 2 is prepared.

그리고 나서, 도 3과 같은 상태가 되도록 솔더 볼(16) 형성면을 제외한 제 1칩 스케일 패키지(10)의 외주면상에 Cu 금속을 도금하고, 에칭을 실행하여 도 4와 같이 패키지 접속 배선(32) 및 패키지 접속 패드(33)를 포함하는 패키지 접속 배선층(31)을 형성한다((b)단계). 패키지 접속 배선(32)은 제 1칩 스케일 패키지(10)의외부 접속 단자(15)와 패키지 접속 패드(33)를 연결하고, 패키지 접속 패드(33)는 적층되는 칩 스케일 패키지의 솔더 볼의 형상에 따라 설정될 수 있다.Then, Cu metal is plated on the outer circumferential surface of the first chip scale package 10 except for the solder ball 16 forming surface so as to be in a state as shown in FIG. 3, and etching is performed to package connection wiring 32 as shown in FIG. 4. ) And a package connection wiring layer 31 including the package connection pad 33 (step (b)). The package connection wiring 32 connects the external connection terminal 15 of the first chip scale package 10 and the package connection pad 33, and the package connection pad 33 has a shape of solder balls of the chip scale package stacked thereon. It can be set according to.

제 1칩 스케일 패키지(10)의 외면상에 패키지 접속 배선층(31)을 형성한 후, 도 4의 상태가 되도록, 패키지 접속 배선층(31)의 보호를 위해 배선 보호층(32)을 형성한다. 배선 보호층(32)은 페이스트(paste) 수지로 형성될 수 있다. 배선 보호층(32)을 형성하기 위해서는, 우선 페이스트 수지 등을 패키지 접속 배선층(31)의 전면에 형성한 후에, 제 2칩 스케일 패키지의 솔더 볼이 부착될 패키지 접속 패드(33) 부위의 페이스트 수지를 제거하는 방법이 사용될 수 있다.After the package connection wiring layer 31 is formed on the outer surface of the first chip scale package 10, the wiring protection layer 32 is formed to protect the package connection wiring layer 31 so as to be in the state of FIG. 4. The wiring protection layer 32 may be formed of a paste resin. In order to form the wiring protection layer 32, first, paste resin or the like is formed on the entire surface of the package connection wiring layer 31, and then paste resin at the portion of the package connection pad 33 to which the solder balls of the second chip scale package are to be attached. A method of removing can be used.

그리고 나서, 도 5의 상태가 되도록 제 2칩 스케일 패키지(20)의 솔더 볼(26)이 패키지 접속 패드(33)에 대응하여 적층하고, 리플로우 공정을 진행하여 제 2칩 스케일 패키지의 솔더 볼(26)을 패키지 접속 패드(33)에 부착시킨다((c)단계). 리플로우 공정은 솔더 볼(26)을 녹여서 패키지지 접속 패드(33)에 납땜 결합을 해주는 역할을 한다.Then, the solder balls 26 of the second chip scale package 20 are laminated corresponding to the package connection pad 33 so as to be in the state of FIG. 5, and the reflow process is performed to solder balls of the second chip scale package. (26) is attached to the package connection pad 33 (step (c)). The reflow process melts the solder balls 26 and serves to solder the package connection pads 33.

한편, 본 발명은 상술한 바 이외에도 본 발명의 기술적 요지를 벗어나지 않는 범위 내에서 다양하게 변경 실시할 수 있음은 당 업계의 기술 분야에서 통상의 지식을 가진 자라면 누구나 이해할 것이다.On the other hand, it will be understood by those of ordinary skill in the art that the present invention may be variously modified and implemented within the scope not departing from the technical gist of the present invention in addition to the above.

본 발명에 따른 적층 패키지가 상술한 바와 같은 구조를 갖고, 상술한 바와 같은 방법에 의해 제조됨으로서, 평면 실장 방식으로 실장되어야 하는 칩 스케일 패키지의 특성에 의한 적층시 패키지 내부 설계 변경의 문제점을 해결하는 것이 가능하다. 이에 따라, 양산되는 동일 내부 구조의 칩 스케일 패키지를 내부 설계 변경 없이 사용하여 적층 패키지를 형성할 수 있고, 적층을 위해 내부가 새로 설계된 칩 스케일 패키지를 제조할 필요가 없으므로, 그에 따라 발생되는 비용 및 시간의 소요를 줄이는 것이 가능하다.Since the laminated package according to the present invention has the structure as described above and is manufactured by the method as described above, it solves the problem of the design change of the package inside the stack due to the characteristics of the chip scale package to be mounted in a planar mounting manner. It is possible. Accordingly, a stacked package can be formed using a mass-produced chip scale package of the same internal structure without changing an internal design, and there is no need to manufacture a newly designed chip scale package for lamination, thereby resulting in a cost and It is possible to reduce the time required.

Claims (7)

활성면의 중심 부분을 따라서 전극 패드가 형성된 반도체 칩,A semiconductor chip in which electrode pads are formed along a central portion of an active surface, 상기 전극 패드를 개방시키는 윈도우(window)가 형성되고, 상부면에 형성된 엘라스토머(elastomer)를 통해 상기 반도체 칩이 부착되며, 하부면에는 내부 접속 패드와 외부 접속 패드와 솔더 범프 패드를 포함하는 배선 패턴이 형성된 배선 기판,A window for opening the electrode pad is formed, and the semiconductor chip is attached through an elastomer formed on an upper surface, and a wiring pattern including an internal connection pad, an external connection pad, and a solder bump pad on a lower surface thereof. Formed wiring board, 상기 윈도우를 통하여 상기 전극 패드와 상기 내부 접속 패드를 연결하는 본딩 와이어,Bonding wires connecting the electrode pads to the internal connection pads through the window; 상기 본딩 와이어를 봉지하는 제 1봉지부,A first encapsulation unit encapsulating the bonding wire, 상기 내부 접속 패드와 연결된 상기 각 솔더 범프 패드에 부착된 솔더 볼, 그리고Solder balls attached to each of the solder bump pads connected to the internal connection pads, and 상기 배선 기판 상부면의 상기 반도체 칩을 봉지하는 제 2봉지부를 포함하는 제 1 및 제 2칩 스케일 패키지(chip scale package); 및First and second chip scale packages including a second encapsulation portion encapsulating the semiconductor chip on the upper surface of the wiring board; And 상기 제 1칩 스케일 패키지의 제 2봉지부 외주면에 형성되고, 상기 제 2칩 스케일 패키지의 솔더 볼이 부착되는 패키지 접속 패드, 그리고 상기 제 1칩 스케일 패키지의 외부 접속 패드와 상기 패키지 접속 패드를 연결하는 패키지 접속 배선을 포함하는 패키지 접속 배선층; 을 포함하는 것을 특징으로 하는 적층 패키지.A package connection pad formed on an outer circumferential surface of the second encapsulation portion of the first chip scale package and to which a solder ball of the second chip scale package is attached, and connecting an external connection pad of the first chip scale package to the package connection pad; A package connection wiring layer including package connection wiring to be formed; Laminated package comprising a. 제 1항에 있어서, 상기 적층 패키지는 상기 패키지 접속 패드를 제외한 상기패키지 접속 배선층 상에 형성된 배선 보호층을 더 포함하는 것을 특징으로 하는 적층 패키지.The stack package of claim 1, wherein the stack package further comprises a wiring protection layer formed on the package connection wiring layer except for the package connection pad. 제 1항에 있어서, 상기 외부 접속 패드는 상기 제 1 및 2칩 스케일 패키지의 측면으로 외부 개방되는 것을 특징으로 하는 적층 패키지.The stack package of claim 1, wherein the external connection pads are opened to the sides of the first and second chip scale packages. 제 2항에 있어서, 상기 제 1칩 스케일 패키지의 외부 접속 패드의 외부 개방면은 상기 제 2칩 스케일 패키지가 적층되는 방향에 대해 경사지도록 형성되는 것을 특징으로 하는 적층 패키지.The stack package of claim 2, wherein an outer open surface of the external connection pad of the first chip scale package is inclined with respect to a direction in which the second chip scale package is stacked. 제 1항에 있어서, 상기 패키지 접속 배선층은 Cu 금속으로 형성되는 것을 특징으로 하는 적층 패키지.The laminate package according to claim 1, wherein the package connection wiring layer is formed of Cu metal. (a) 활성면의 중심 부분을 따라서 전극 패드가 형성된 반도체 칩,(a) a semiconductor chip having electrode pads formed along a central portion of an active surface, 상기 전극 패드를 개방시키는 윈도우가 형성되고, 상부면에 형성된 엘라스토머를 통해 상기 반도체 칩이 부착되며, 하부면에는 내부 접속 패드와 외부 접속 패드와 솔더 범프 패드를 포함하는 배선 패턴이 형성된 배선 기판,A wiring board having a window for opening the electrode pads formed thereon, the semiconductor chip being attached through an elastomer formed on an upper surface thereof, and a wiring pattern including an inner connection pad, an external connection pad, and a solder bump pad formed on a lower surface thereof; 상기 윈도우를 통하여 상기 전극 패드와 상기 내부 접속 패드를 연결하는 본딩 와이어,Bonding wires connecting the electrode pads to the internal connection pads through the window; 상기 본딩 와이어 부분을 봉지하는 제 1봉지부,A first encapsulation portion encapsulating the bonding wire portion, 상기 내부 접속 패드와 연결된 상기 각 솔더 범프 패드에 부착된 솔더 볼, 그리고Solder balls attached to each of the solder bump pads connected to the internal connection pads, and 상기 반도체 칩의 외부를 봉지하는 제 2봉지부를 포함하는 제 1 및 제 2칩 스케일 패키지를 준비하는 단계;Preparing first and second chip scale packages including a second encapsulation portion encapsulating the outside of the semiconductor chip; (b) 제 2봉지부 외주면에, 패키지 접속 패드를 형성하고, 상기 패키지 접속 패드 및 상기 제 1칩 스케일 패키지의 외부 접속 패드를 패키지 접속 배선으로 연결하는 단계; 및(b) forming a package connection pad on an outer circumferential surface of the second encapsulation portion, and connecting the package connection pad and the external connection pad of the first chip scale package with a package connection wiring; And (c) 상기 제 2칩 스케일 패키지의 솔더 볼을 상기 패키지 접속 패드에 대응하도록 적층하고, 리플로우(reflow) 공정을 진행하여 상기 제 2칩 스케일 패키지의 솔더 볼을 상기 패키지 접속 패드에 부착시키는 단계; 를 포함하는 것을 특징으로 하는 적층 패키지 제조 방법.(c) stacking the solder balls of the second chip scale package so as to correspond to the package connection pads, and performing a reflow process to attach the solder balls of the second chip scale package to the package connection pads. ; Laminated package manufacturing method comprising a. 제 6항에 있어서, 상기 적층 패키지 제조 방법은 상기 (b)단계 및 (c)단계 사이에 상기 패키지 접속 패드를 제외한 패키지 접속 배선층 상에 배선 보호층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 적층 패키지 제조 방법.The method of claim 6, wherein the method for manufacturing a laminated package further comprises the step of forming a wiring protection layer on the package connection wiring layer except for the package connection pad between the steps (b) and (c). Laminated package manufacturing method.
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