KR20050000972A - Chip stack package - Google Patents

Chip stack package Download PDF

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Publication number
KR20050000972A
KR20050000972A KR1020030041580A KR20030041580A KR20050000972A KR 20050000972 A KR20050000972 A KR 20050000972A KR 1020030041580 A KR1020030041580 A KR 1020030041580A KR 20030041580 A KR20030041580 A KR 20030041580A KR 20050000972 A KR20050000972 A KR 20050000972A
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South Korea
Prior art keywords
semiconductor chip
lead frame
chip
leadframe
attached
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KR1020030041580A
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Korean (ko)
Inventor
조철호
정관호
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주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020030041580A priority Critical patent/KR20050000972A/en
Priority to US10/701,326 priority patent/US20040262773A1/en
Publication of KR20050000972A publication Critical patent/KR20050000972A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
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    • H01L2924/01078—Platinum [Pt]
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    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Abstract

PURPOSE: A chip stack package is provided to simplify a fabricating process and reduce fabricating cost by fabricating a chip stack package while using a leadframe of a conventional LOC(lead on chip) structure. CONSTITUTION: A dual downset leadframe(24) includes a tip part on which a wire bonding process is performed. The first semiconductor chip(21) is attached to the lower part of the tip downset part of the leadframe. A bonding pad of the first semiconductor chip is electrically connected to the tip downset leadframe by the first metal wire(25). The second semiconductor chip(22) is attached to the upper part of the leadframe. The second semiconductor chip is electrically connected to the leadframe by the second metal wire(27). An encapsulating material(28) encapsulates the first and second semiconductor chips except the back surface of the first semiconductor chip, the first and second metal wires and a spatial region including a part of the leadframe.

Description

칩 스택 패키지{Chip stack package}Chip stack package

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는, LOC(Lead On Chip) 구조의 리드프레임을 이용한 칩 스택 패키지(Chip stack package)에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a chip stack package using a lead frame having a lead on chip (LOC) structure.

전기/전자 제품의 고성능화가 진행됨에 따라 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 많은 기술들이 제안 및 연구되고 있다. 그런데, 패키지는 하나의 반도체 칩이 탑재되는 것을 기본으로 하기 때문에 소망하는 용량을 얻는데 한계가 있다.As the performance of electrical / electronic products is advanced, many technologies for mounting a larger number of packages on a limited size substrate have been proposed and studied. By the way, since a package is based on which one semiconductor chip is mounted, there is a limit in obtaining desired capacity.

한편, 메모리 칩의 용량 증대, 즉, 고집적화를 이룰 수 있는 방법으로는 한정된 공간 내에 보다 많은 수의 셀을 제조해 넣는 기술이 일반적으로 알려져 있다. 그런데, 이와 같은 방법은 정밀한 미세 선폭을 요구하는 등, 고난도의 공정 기술과 많은 개발 시간을 필요로 한다. 따라서, 보다 용이하게 고집적화를 이룰 수 있는 방법으로서 스택킹(stacking) 기술이 개발되었고, 현재 이에 대한 연구가 활발히 진행되고 있다.On the other hand, as a method of increasing the capacity of the memory chip, that is, high integration, a technique of manufacturing a larger number of cells in a limited space is generally known. However, such a method requires a high level of process technology and a lot of development time, such as requiring a precise fine line width. Therefore, a stacking technology has been developed as a method of achieving high integration more easily, and researches on this are being actively conducted.

반도체 업계에서 말하는 스택킹이란, 적어도 2개 이상의 반도체 칩을 스택하여 메모리 용량을 배가시키는 기술이다. 이러한 스택킹 기술에 의하면, 2개의 128M DRAM급 칩을 스택하여 256M DRAM급으로 구성할 수 있으며, 이에 따라, 실장 밀도 및 실장 면적 사용의 효율성을 높일 수 있다.Stacking as used in the semiconductor industry is a technique of stacking at least two or more semiconductor chips to double the memory capacity. According to such a stacking technology, two 128M DRAM chips can be stacked to be 256M DRAM, thereby increasing the mounting density and the efficiency of using the mounting area.

스택 패키지의 구현 방법으로는 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 칩 스택 방법과 패키징된 2개의 패키지를 스택하는 패키지 스택 방법이 있다. 그런데, 후자의 방법은 패키지의 전체 두께가 두꺼워질 뿐만 아니라, 미세 피치(fine pitch)로 인해 상,하 패키지들간의 전기적 연결에 어려움이 있는 바, 최근의 스택킹 기술은 전자의 방법에 대해 많이 연구되고 있다.Stack package implementation methods include a chip stack method for embedding two stacked chips in one package and a package stack method for stacking two packaged packages. However, the latter method not only thickens the overall thickness of the package, but also has difficulty in electrical connection between the upper and lower packages due to the fine pitch. Is being studied.

여기서, 전자의 방법에 따라 개발된 칩 스택 패키지로서는 회로패턴을 구비한 기판 상에 두 개의 칩을 한 개는 패드 형성면이 아래를 향하도록, 그리고, 다른 하나는 패드 형성면이 위를 향하도록 부착하여 제작한 것을 들 수 있다.Here, as a chip stack package developed according to the former method, two chips on a substrate having a circuit pattern, one pad side faces down, and the other pad side faces upwards. The thing attached and produced is mentioned.

또한, 이와 유사한 구조로 고가의 기판 대신 저가의 리드프레임(leadframe)을 이용하여 제작한 것을 들 수 있으며, 이에 대한 구조는 도 1에 도시된 바와 같다.In addition, a similar structure may be fabricated using a low cost leadframe instead of an expensive substrate, and the structure thereof is shown in FIG. 1.

도 1을 참조하면, 두 개의 칩(1, 2)이 한 개는 패드 형성면이 아래를 향하도록, 그리고, 다른 하나는 패드 형성면이 위를 향하도록 부착되어 있다. 바텀 칩(1) 및 탑 칩(2)의 패드 형성면 각각에는 리드(3)가 배치되어져 있고 이러한 리드들(3)은 대응하는 것들끼리 상호 연결되어져 패키지 몸체, 즉, 봉지제(5)의 외측으로 인출되어져 있다.Referring to FIG. 1, two chips 1 and 2 are attached with one pad facing down and the other facing upward. Leads 3 are disposed on each of the pad forming surfaces of the bottom chip 1 and the top chip 2, and the leads 3 are interconnected to each other so that the package body, i.e., the encapsulant 5 It is drawn outward.

그리고, 각 칩(1, 2)의 본딩패드들(1a, 2a)과 리드들(3)은 금속 와이어(4)에 의해 전기적으로 상호 연결되어져 있다.The bonding pads 1a and 2a of the chips 1 and 2 and the leads 3 are electrically connected to each other by the metal wire 4.

그러나, 현재 디램소자는 칩 중앙부에 패드가 나열된 센터 패드(center pad) 구조가 주류를 이루고 있는 것과 관련해서, 이러한 센터 패드의 칩들을 스택함은 칩 에지에 패드가 나열된 에지 패드(edge pad)의 칩들을 스택하는 것 보다 어려움이 있다.However, currently DRAM devices have a mainstream center pad structure in which pads are located at the center of the chip, and stacking the chips of such center pads is performed by the edge pads having the pads at the chip edges. There is more difficulty than stacking chips.

또한, 도 1에 도시된 바와 같은 TSOP(Thin Small Outlead Package)은 그 제작을 위해 신규투자가 많이 필요할 뿐만 아니라, 웨이퍼를 매우 얇게 그라인딩해야 하는 바, 제조 공정이 복잡한 단점을 갖는다.In addition, as shown in FIG. 1, the TSOP (Thin Small Outlead Package) requires not only a lot of new investment for its fabrication but also requires very thin grinding of the wafer, and thus has a complicated manufacturing process.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 간단하게 제조 가능한 칩 스택 패키지를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a chip stack package that can be easily manufactured, which is devised to solve the above problems.

또한, 본 발명은 제조 공정의 단순화 및 제조비용을 절감할 수 있는 칩 스택 패키지를 제공함에 그 다른 목적이 있다.It is another object of the present invention to provide a chip stack package that can simplify the manufacturing process and reduce the manufacturing cost.

도 1은 종래의 칩 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional chip stack package.

도 2는 본 발명의 제1실시예에 따른 칩 스택 패키지를 도시한 단면도.2 is a cross-sectional view showing a chip stack package according to a first embodiment of the present invention.

도 3 내지 도 6은 본 발명의 제2 내지 제5실시예에 따른 칩 스택 패키지들을 도시한 단면도.3 to 6 are cross-sectional views illustrating chip stack packages according to second to fifth embodiments of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 제1반도체 칩 22 : 제2반도체 칩21: first semiconductor chip 22: second semiconductor chip

23 : LOC 테이프 24 : 리드프레임23: LOC tape 24: leadframe

25 : 제1금속와이어 26 : 접착제25: first metal wire 26: adhesive

27 : 제2금속와이어 28 : 봉지제27: second metal wire 28: sealing agent

29 : 접착 테이프 31 : B-스테이지용 물질막29 adhesive tape 31 material film for B-stage

상기와 같은 목적을 달성하기 위하여, 본 발명은, 와이어 본딩이 이루어질 팁(Tip) 부분을 포함하여 이중으로 다운세트된 리드프레임; 상기 리드프레임의 팁 다운세트 부분의 하부에 부착된 제1반도체 칩; 상기 제1반도체 칩의 본딩패드와 팁 다운세트된 리드프레임 부분을 전기적으로 연결하는 제1금속와이어; 상기 리드프레임 상에 부착된 제2반도체 칩; 상기 제2반도체 칩과 리드프레임을 전기적으로 연결하는 제2금속와이어; 및 상기 제1반도체 칩의 후면을 제외한 상기 제1 및 제2반도체 칩과 제1 및 제2금속와이어 및 리드프레임의 일부분을 포함한 공간적 영역을 밀봉하는 봉지제를 포함하는 칩 스택 패키지를 제공한다.In order to achieve the above object, the present invention, a lead frame including a tip (tip) portion to be wire bonding is downset double; A first semiconductor chip attached to a lower portion of the tip downset portion of the leadframe; A first metal wire electrically connecting a bonding pad of the first semiconductor chip to a tip downset lead frame portion; A second semiconductor chip attached to the lead frame; A second metal wire electrically connecting the second semiconductor chip and the lead frame; And an encapsulant for encapsulating a spatial region including the first and second semiconductor chips, the first and second metal wires, and a portion of the lead frame, except for the rear surface of the first semiconductor chip.

여기서, 상기 제1반도체 칩은 LOC 테이프에 의해 부착된다. 상기 제2반도체 칩은 접착제에 의해 부착되며, 상기 접착제는 제2반도체 칩과 제1반도체 칩 사이 공간 전체에 충진되거나, 또는, 제2반도체 칩과 리드프레임 사이에만 개재된다. 또한, 상기 제2반도체 칩은 접착테이프에 의해 부착될 수 있다.Here, the first semiconductor chip is attached by LOC tape. The second semiconductor chip is attached by an adhesive, and the adhesive is filled in the entire space between the second semiconductor chip and the first semiconductor chip or interposed only between the second semiconductor chip and the lead frame. In addition, the second semiconductor chip may be attached by an adhesive tape.

한편, 상기한 본 발명의 칩 스택 패키지는 제1반도체 칩이 LOC 테이프가 아닌 B-스테이지용 물질막에 의해 부착될 수 있다.Meanwhile, in the chip stack package of the present invention, the first semiconductor chip may be attached by a material film for B-stage rather than a LOC tape.

또한, 상기한 본 발명의 칩 스택 패키지는 리드프레임의 팁 부분이 다운세트됨이 없이 상대적으로 얇은 두께를 갖도록 디자인될 수 있다.In addition, the chip stack package of the present invention can be designed to have a relatively thin thickness without the tip portion of the lead frame is downset.

본 발명에 따르면, 일반적인 LOC 구조의 리드프레임을 사용하여 칩 스택 패키지를 제조하므로 그 제조공정을 단순화시킬 수 있으며, 또한, 제조공정을 단순화시키면서 저가의 리드프레임을 사용하는 것과 관련해서 제조비용을 낮출 수 있다.According to the present invention, a chip stack package is manufactured by using a lead frame having a general LOC structure, thereby simplifying the manufacturing process and lowering manufacturing costs associated with using a low cost lead frame while simplifying the manufacturing process. Can be.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 제1실시예에 따른 칩 스택 패키지를 도시한 단면도이다.2 is a cross-sectional view illustrating a chip stack package according to a first embodiment of the present invention.

도시된 바와 같이, 칩 중앙부에 2열로 패드가 나열된 센터 패드형의 제1반도체 칩(21)은 팁 다운세트(Tip Down Set)된 전형적인 LOC(Lead On Chip) 구조, 즉, 와이어 본딩이 이루어지는 인너리드의 팁 부분이 다운세트된 리드프레임(23)에 그의 패드 형성면이 LOC 테이프(23)에 의해 부착되어져 있고, 상기 제1반도체 칩(21)의 본딩패드(도시안됨)와 다운세트된 리드프레임(24)의 팁(Tip) 부분은 제1금속와이어(25)에 의해 전기적으로 상호 연결되어져 있다.As shown, the center pad type first semiconductor chip 21 in which the pads are arranged in two rows at the center of the chip has a typical lead on chip (LOC) structure in which a tip down is set, that is, inner wire bonding is performed. The pad forming surface thereof is attached to the lead frame 23 in which the tip portion of the lead is set down by the LOC tape 23, and the lead set down with the bonding pad (not shown) of the first semiconductor chip 21. The tip portion of the frame 24 is electrically interconnected by the first metal wire 25.

또한, 칩 중앙부에 2열로 패드가 나열된 센터 패드형의 제2반도체 칩(22)은 접착제(26)에 의해 상기 리드프레임(24) 상에 그의 후면이 부착되어져 있고, 그의 본딩패드(도시안됨)와 상기 리드프레임(24)의 소정 부분은 제2금속와이어(27)에 의해 상호 연결되어져 있다. 이때, 상기 접착제(26)는 몰딩 공정에서 발생 가능한 내부 보이드(void)가 원천적으로 제거되도록 제2반도체 칩(22)과 제1반도체 칩(21) 사이의 공간 전체에 충진된다.In addition, the second semiconductor chip 22 of the center pad type in which the pads are arranged in two rows at the center of the chip is attached to its rear surface on the lead frame 24 by an adhesive 26 and its bonding pad (not shown). And a predetermined portion of the lead frame 24 are interconnected by a second metal wire 27. In this case, the adhesive 26 is filled in the entire space between the second semiconductor chip 22 and the first semiconductor chip 21 so that internal voids, which may occur in the molding process, are removed.

그리고, 반도체 칩들(21, 22)과 리드프레임(24) 및 금속와이어(25, 27)를 포함한 공간적 영역은 상기 리드프레임(24)의 소정 길이만큼이 외측으로 돌출되게 봉지제(28)로 밀봉되어져 있으며, 상기 봉지제(28)로부터 돌출된 리드프레임 부분은 외부 회로기판에의 실장을 위해 소정 형상으로 포밍되어져 있다. 이때, 상기 봉지제(28)는 몰딩 공정의 작업성 향상과 패키지의 열방출 능력을 향상시키기 위해 제1반도체 칩(21)의 후면을 노출시키는 형태로 형성된다.The spatial region including the semiconductor chips 21 and 22, the lead frame 24, and the metal wires 25 and 27 is sealed with the encapsulant 28 such that the predetermined length of the lead frame 24 protrudes outward. The lead frame portion protruding from the encapsulant 28 is formed into a predetermined shape for mounting on an external circuit board. In this case, the encapsulant 28 is formed to expose the rear surface of the first semiconductor chip 21 in order to improve the workability of the molding process and the heat dissipation ability of the package.

이와 같은 구조를 갖는 본 발명의 칩 스택 패키지 제조방법은 다음과 같다.The chip stack package manufacturing method of the present invention having such a structure is as follows.

먼저, 팁 다운세트를 포함하여 이중으로 다운세트된 리드프레임(24)에 LOC 다이 본더를 이용해서 LOC 테이프(23)로 제1반도체 칩(21)을 부착시킨다. 그런다음, 와이어 본딩 공정을 통해 상기 제1반도체 칩(21)의 본딩패드와 리드프레임(24)의 팁 부분을 제1금속와이어(25)로 연결한다.First, the first semiconductor chip 21 is attached to the LOC tape 23 using a LOC die bonder to a double downset lead frame 24 including a tip downset. Then, the bonding pad of the first semiconductor chip 21 and the tip portion of the lead frame 24 are connected to the first metal wire 25 through a wire bonding process.

다음으로, 제1반도체 칩(21)의 표면 및 리드프레임(24)의 인너리브 부분 상에 접착제(26)를 도포한다. 그런다음, 접착제(26) 상에 제2반도체 칩(22)을 부착한 후, 상기 접착제(26)를 경화시킨다. 이어서, 와이어 본딩 공정을 통해 제2반도체 칩(22)의 본딩패드와 리드프레임(24)의 소정 부분을 제2금속와이어(27)로 연결한다. 여기서, 리드프레임(24)은 스티치 본딩(stitch bonding)을 위해 스티치 본딩 영역에 은(Ag), 금(Au) 또는 팔라듐(Pd) 등의 도금을 행하여 제작함이 바람직하다.Next, an adhesive 26 is applied on the surface of the first semiconductor chip 21 and the inner rib portion of the lead frame 24. Then, after attaching the second semiconductor chip 22 on the adhesive 26, the adhesive 26 is cured. Subsequently, a bonding pad of the second semiconductor chip 22 and a predetermined portion of the lead frame 24 are connected to the second metal wire 27 through a wire bonding process. Here, the lead frame 24 is preferably manufactured by plating silver (Ag), gold (Au), or palladium (Pd) on the stitch bonding region for stitch bonding.

그 다음, 제1반도체 칩(21)의 후면을 제외한 나머지 부재들을 포함한 공간적 영역을 봉지제(28)로 밀봉한다.Then, the spatial region including the members other than the rear surface of the first semiconductor chip 21 is sealed with the encapsulant 28.

이후, 공지의 후속 어셈블리(assembly) 공정, 즉, 레이져 마킹, 트림, 도금및 포밍을 차례로 행하여 본 발명의 칩 스택 패키지를 제조한다.Thereafter, a known subsequent assembly process, that is, laser marking, trimming, plating, and forming are performed in sequence to produce the chip stack package of the present invention.

전술한 바와 같은 본 발명의 칩 스택 패키지에 따르면, 이중 다운세트를 준 기존 LOC 구조의 리드프레임을 이용하여 제조하므로, 기존의 TSOP 생산설비를 그대로 이용할 수 있는 것과 관련해서, 현재 잘 알려진 센터 패드 칩 스택 구조에 비해 그 제조공정의 단순화 및 이에 따른 제조비용의 절감을 얻을 수 있다.According to the chip stack package of the present invention as described above, since it is manufactured by using a lead frame of the existing LOC structure with a double downset, in relation to the existing TSOP production equipment can be used as it is, the currently known center pad chip Compared with the stack structure, the manufacturing process can be simplified and the manufacturing cost can be reduced.

또한, 제1반도체 칩의 후면을 패키지 외부로 노출시킨 것과 관련해서, 고속동작 소자에서 열방출 능력을 향상시킬 수 있음은 물론 몰딩 공정에서 칩 틸트, 바닥 보이드 발생 등의 소지를 원천적으로 제거할 수 있다.In addition, in connection with exposing the rear surface of the first semiconductor chip to the outside of the package, the heat dissipation capability can be improved in the high-speed operation device, and the source of chip tilt and bottom void generation can be removed in the molding process. have.

도 3 내지 도 6은 본 발명의 다른 실시예들에 따른 칩 스택 패키지들을 도시한 단면도들로서, 이를 설명하면 다음과 같다. 여기서, 각 도면에 대한 설명은 도 2와 상이한 부분에 대해서만 하도록 한다.3 to 6 are cross-sectional views illustrating chip stack packages according to other embodiments of the present invention. Here, the description of each drawing will be made only for the portion different from FIG.

도 3을 참조하면, 본 발명의 제2실시예에 따른 칩 스택 패키지는 전술한 제1실시예에 따른 그것과 비교해서 리드프레임(24) 상에 제2반도체 칩(22)을 부착하기 위한 접착제(26)의 도포시 제1반도체 칩(21)과 리드프레임(24) 사이에만 개재되도록 한다. 이 경우, 접착제의 사용을 줄임으로써 생산성을 높일 수 있고, 또한, 제조비용을 절감할 수 있다.Referring to FIG. 3, the chip stack package according to the second embodiment of the present invention is an adhesive for attaching the second semiconductor chip 22 on the leadframe 24 as compared with that according to the first embodiment described above. At the time of application of 26, only the first semiconductor chip 21 and the lead frame 24 are interposed. In this case, productivity can be improved by reducing the use of an adhesive agent, and manufacturing cost can be reduced.

도 4를 참조하면, 본 발명의 제3실시예에 따른 칩 스택 패키지는 전술한 제1실시예에 따른 그것과 비교해서 리드프레임(24) 상에 제2반도체 칩(22)을 부착하기 위한 접착제 대신에 접착 테이프(30)를 사용한다. 이 경우, 접착제 도포후의 경화 과정이 필요없으므로, 공정 단순화의 잇점을 갖는다.4, the chip stack package according to the third embodiment of the present invention is an adhesive for attaching the second semiconductor chip 22 on the lead frame 24 as compared with that according to the first embodiment described above. Instead, adhesive tape 30 is used. In this case, there is no need for a curing process after applying the adhesive, which has the advantage of simplifying the process.

도 5를 참조하면, 본 발명의 제4실시예에 따른 칩 스택 패키지는 전술한 제1실시예에 따른 그것과 비교해서 제1반도체 칩(21)의 부착시 상기 제1반도체 칩(21) 상에 B-스테이지용 물질막(31)을 도포한 후, 이러한 B-스테이지용 물질막(31)을 이용해서 리드프레임(24)에 부착시킨다. 이 경우, 상기 제1반도체 칩(21)의 리드프레임(24)에의 부착시에 고가의 LOC 테이프를 사용하지 않으므로, 그에 해당하는 만큼의 비용 절감을 얻을 수 있다.Referring to FIG. 5, the chip stack package according to the fourth embodiment of the present invention is on the first semiconductor chip 21 when the first semiconductor chip 21 is attached in comparison with that according to the first embodiment described above. After the B-stage material film 31 is applied, the B-stage material film 31 is attached to the lead frame 24 using the B-stage material film 31. In this case, an expensive LOC tape is not used when the first semiconductor chip 21 is attached to the lead frame 24, so that a corresponding cost reduction can be obtained.

도 6을 참조하면, 본 발명의 제5실시예에 따른 칩 스택 패키지는 전술한 제1실시예에 따른 그것과 비교해서 와이어본딩이 이루어지는 리드프레임(24)의 일단이 팁 다운세트됨이 없이, 예컨데, 하프 식각(half etching) 또는 코이닝(coining) 처리를 통해 상대적으로 얇게 두께를 갖도록 디자인된다.Referring to FIG. 6, in the chip stack package according to the fifth embodiment of the present invention, one end of the lead frame 24 in which wire bonding is performed is compared with that according to the first embodiment described above without tip downsetting. For example, it is designed to have a relatively thin thickness through half etching or coining.

한편, 도시하지 않았지만, 본 발명의 다른 실시예로서 봉지제 외부로 노출된 제1반도체 칩의 후면에 소정의 보호테이프를 부착할 수 있으며, 이 경우에는 물리적인 데미지 및 정전기로부터 제1반도체 칩을 보호할 수 있다.Although not shown, a protective tape may be attached to the rear surface of the first semiconductor chip exposed to the outside of the encapsulant, and in this case, the first semiconductor chip may be removed from physical damage and static electricity. I can protect it.

또한, 본 발명의 또 다른 실시예로서 제1반도체 칩의 보호를 위해 그 후면을 외부로 노출시키지 않는 형태로도 제조 가능하다.In addition, as another embodiment of the present invention can be manufactured in a form that does not expose the rear surface to the outside for the protection of the first semiconductor chip.

이상에서와 같이, 본 발명은 일반적인 LOC 구조의 리드프레임을 사용하여 칩 스택 패키지를 제조하기 때문에 기존의 칩 스택 패키지의 제조와 비교해서 그 제조공정을 단순화시킬 수 있다.As described above, since the present invention manufactures a chip stack package using a lead frame having a general LOC structure, the manufacturing process can be simplified as compared with the manufacture of a conventional chip stack package.

또한, 본 발명은 제조공정의 단순화를 이룰 수 있으면서 저가의 리드프레임을 사용하는 것과 관련해서 제조비용을 낮출 수 있다.In addition, the present invention can simplify the manufacturing process while lowering the manufacturing cost associated with using a low cost leadframe.

게다가, 본 발명은 제1반도체 칩의 후면을 봉지제로부터 노출시키므로, 몰딩 공정에서 발생될 수 있는 문제를 원천적으로 제거할 수 있음은 물론 열방출 능력을 향상시킬 수 있다.In addition, since the present invention exposes the rear surface of the first semiconductor chip from the encapsulant, it is possible to eliminate problems that may occur in the molding process and improve heat dissipation capability.

부가해서, 칩 크기가 커질수록 스택 작없이 용이해지므로, 큰 크기의 칩을 적용할 경우 칩 크기 패키지 수준의 칩 크기/패키지 크기 비율을 구현할 수 있다.In addition, the larger the chip size, the easier it becomes without stacking. When a large chip is applied, a chip size / package size ratio of the chip size package level can be realized.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (8)

와이어 본딩이 이루어질 팁(Tip) 부분을 포함하여 이중으로 다운세트된 리드프레임;A leadframe dually downset including a tip portion to which wire bonding is to be made; 상기 리드프레임의 팁 다운세트 부분의 하부에 부착된 제1반도체 칩;A first semiconductor chip attached to a lower portion of the tip downset portion of the leadframe; 상기 제1반도체 칩의 본딩패드와 팁 다운세트된 리드프레임 부분을 전기적으로 연결하는 제1금속와이어;A first metal wire electrically connecting a bonding pad of the first semiconductor chip to a tip downset lead frame portion; 상기 리드프레임 상에 부착된 제2반도체 칩;A second semiconductor chip attached to the lead frame; 상기 제2반도체 칩과 리드프레임을 전기적으로 연결하는 제2금속와이어; 및A second metal wire electrically connecting the second semiconductor chip and the lead frame; And 상기 제1반도체 칩의 후면을 제외한 상기 제1 및 제2반도체 칩과 제1 및 제2금속와이어 및 리드프레임의 일부분을 포함한 공간적 영역을 밀봉하는 봉지제를 포함하는 것을 특징으로 하는 칩 스택 패키지.And an encapsulant for encapsulating a spatial region including the first and second semiconductor chips, the first and second metal wires, and a portion of the lead frame, except for the rear surface of the first semiconductor chip. 제 1 항에 있어서, 상기 제1반도체 칩은 LOC 테이프에 의해 부착된 것을 특징으로 하는 칩 스택 패키지.The chip stack package of claim 1, wherein the first semiconductor chip is attached by LOC tape. 제 1 항에 있어서, 상기 제2반도체 칩은 접착제에 의해 부착된 것을 특징으로 하는 칩 스택 패키지.The chip stack package of claim 1, wherein the second semiconductor chip is attached by an adhesive. 제 3 항에 있어서, 상기 접착제는 제2반도체 칩과 제1반도체 칩 사이 공간전체에 충진된 것을 특징으로 하는 칩 스택 패키지.The chip stack package of claim 3, wherein the adhesive is filled in the entire space between the second semiconductor chip and the first semiconductor chip. 제 3 항에 있어서, 상기 접착제는 제2반도체 칩과 리드프레임 사이에만 개재된 것을 특징으로 하는 칩 스택 패키지.The chip stack package of claim 3, wherein the adhesive is interposed only between the second semiconductor chip and the leadframe. 제 1 항에 있어서, 상기 제2반도체 칩은 접착테이프에 의해 부착된 것을 특징으로 하는 칩 스택 패키지.The chip stack package of claim 1, wherein the second semiconductor chip is attached by an adhesive tape. 와이어 본딩이 이루어질 팁(Tip) 부분을 포함하여 이중으로 다운세트된 리드프레임; 상기 리드프레임의 하부에 B-스테이지용 물질막에 의해 부착된 제1반도체 칩; 상기 제1반도체 칩의 본딩패드와 리드프레임의 팁 부분을 전기적으로 연결하는 제1금속와이어; 상기 리드프레임 상에 접착제에 의해 부착된 제2반도체 칩; 상기 제2반도체 칩과 리드프레임을 전기적으로 연결하는 제2금속와이어; 및 상기 제1반도체 칩의 후면을 제외한 상기 제1 및 제2반도체 칩과 제1 및 제2금속와이어 및 리드프레임의 일부분을 포함한 공간적 영역을 밀봉하는 봉지제를 포함하는 것을 특징으로 하는 칩 스택 패키지.A leadframe dually downset including a tip portion to which wire bonding is to be made; A first semiconductor chip attached to the lower part of the lead frame by a material film for B-stage; A first metal wire electrically connecting the bonding pad of the first semiconductor chip and the tip portion of the lead frame; A second semiconductor chip attached to the lead frame by an adhesive; A second metal wire electrically connecting the second semiconductor chip and the lead frame; And an encapsulant for encapsulating a spatial region including the first and second semiconductor chips, the first and second metal wires, and a portion of the lead frame, except for the rear surface of the first semiconductor chip. . 와이어 본딩이 이루어질 팁(Tip) 부분이 상대적으로 얇은 두께를 갖도록 디자인된 다운세트된 리드프레임; 상기 리드프레임의 팁 부분의 하부에 부착된 제1반도체 칩; 상기 제1반도체 칩의 본딩패드와 리드프레임의 팁 부분을 전기적으로 연결하는 제1금속와이어; 상기 리드프레임 상에 부착된 제2반도체 칩; 상기 제2반도체 칩과 리드프레임을 전기적으로 연결하는 제2금속와이어; 및 상기 제1반도체 칩의 후면을 제외한 상기 제1 및 제2반도체 칩과 제1 및 제2금속와이어 및 리드프레임의 일부분을 포함한 공간적 영역을 밀봉하는 봉지제를 포함하는 것을 특징으로 하는 칩 스택 패키지.A downset leadframe designed such that a tip portion where wire bonding is to be made has a relatively thin thickness; A first semiconductor chip attached to a lower portion of the tip portion of the lead frame; A first metal wire electrically connecting the bonding pad of the first semiconductor chip and the tip portion of the lead frame; A second semiconductor chip attached to the lead frame; A second metal wire electrically connecting the second semiconductor chip and the lead frame; And an encapsulant for encapsulating a spatial region including the first and second semiconductor chips, the first and second metal wires, and a portion of the lead frame, except for the rear surface of the first semiconductor chip. .
KR1020030041580A 2003-06-25 2003-06-25 Chip stack package KR20050000972A (en)

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