KR20050000968A - method for fabricating metal line - Google Patents

method for fabricating metal line Download PDF

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Publication number
KR20050000968A
KR20050000968A KR1020030041576A KR20030041576A KR20050000968A KR 20050000968 A KR20050000968 A KR 20050000968A KR 1020030041576 A KR1020030041576 A KR 1020030041576A KR 20030041576 A KR20030041576 A KR 20030041576A KR 20050000968 A KR20050000968 A KR 20050000968A
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KR
South Korea
Prior art keywords
metal
contact hole
wafer
forming
selectively
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KR1020030041576A
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Korean (ko)
Inventor
이성훈
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주식회사 하이닉스반도체
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Priority to KR1020030041576A priority Critical patent/KR20050000968A/en
Publication of KR20050000968A publication Critical patent/KR20050000968A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Abstract

PURPOSE: A method for forming a metal interconnection is provided to avoid a metal layer CMP(chemical mechanical polishing) process by selectively depositing a metal layer only in a contact hole through an electroplating process. CONSTITUTION: A conductive pattern(11) of a predetermined type is formed on a wafer(10). An insulation layer(12) is formed on the wafer including the conductive pattern. The insulation layer is selectively etched to form a contact hole(13) exposing a part of the conductive pattern. An electroplating process is performed on the wafer including the contact hole to form a metal interconnection(14) for selectively filling the contact hole.

Description

금속배선 형성 방법{method for fabricating metal line}Method for fabricating metal line

본 발명은 반도체소자의 제조 방법에 관한 것으로, 보다 구체적으로는 절연막 사이의 전도체 패턴에 전기화학적으로 금속을 선택적으로 증착할 수 있는 금속 배선을 형성하는 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a metal wiring forming method for forming a metal wiring capable of selectively depositing a metal electrochemically in the conductor pattern between the insulating film.

반도체 소자의 다마신 금속 배선 형성 공정은 금속배선이 형성될 절연막의 소정 부분에 CVD(Chemical Vapor Deposition), PVD(Physical Vapor Deposition) 또는 전기도금(electroplating) 공정을 통해 금속막을 증착하고, 상기 금속막에 금속배선의 격리를 위해 CMP(Chemical Mechnical Polishing:이하, 씨엠피라 칭함)를 실시함으로서 형성된다.In the damascene metal wiring forming process of a semiconductor device, a metal film is deposited through a chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating process on a predetermined portion of the insulating film on which the metal wiring is to be formed. It is formed by performing CMP (Chemical Mechnical Polishing) (hereinafter referred to as CMP) to isolate the metal wiring.

도 1a 내지 도 1d는 종래 기술에 따른 금속 배선 형성 방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a metal wiring according to the prior art.

종래 기술에 따른 금속 배선 형성 방법은, 도 1에 도시된 바와 같이, 웨이퍼(1) 위에 웨이퍼 소정 부위에 잔류되는 전도체 패턴(2)을 형성한 다음, 상기 구조 전면에 절연막(3)을 형성한다. 이어, 도 1b에 도시된 바와 같이, 상기 절연막(3) 위에 전도체 패턴(2)과 대응된 부분을 일부 노출시키는 감광막 패턴(6)을 형성하고 나서, 상기 감광막 패턴(6)을 마스크로 하여 상기 절연막을 식각하여 콘택홀(4)을 형성한다.In the metal wire forming method according to the related art, as shown in FIG. 1, the conductor pattern 2 remaining on a predetermined portion of the wafer is formed on the wafer 1, and then the insulating film 3 is formed on the entire structure. . Subsequently, as shown in FIG. 1B, a photosensitive film pattern 6 is formed on the insulating film 3 to partially expose a portion corresponding to the conductor pattern 2, and then the photosensitive film pattern 6 is used as a mask. The insulating film is etched to form the contact hole 4.

그런 다음, 감광막 패턴을 제거하고 나서, 도 1c에 도시된 바와 같이, 상기 결과물 전면에 CVD 또는 PVD 공정을 진행시켜 금속막(5)을 형성한다.Then, after removing the photoresist pattern, the metal film 5 is formed by performing a CVD or PVD process on the entire surface of the resultant, as shown in FIG.

이 후, 도 1d에 도시된 바와 같이, 상기 금속막에 씨엠피 공정을 진행하여 콘택홀(4)을 매립시키는 금속 배선(5a)을 형성한다.Thereafter, as shown in FIG. 1D, the CMP process is performed on the metal film to form the metal wiring 5a for filling the contact hole 4.

그러나, 종래의 기술에서는 CVD 또는 PVD 공정을 적용하여 금속막을 형성할 경우, 금속막이 콘택홀 내부 뿐만 아니라 절연막의 상부 일정부분까지 증착되어지게 되므로, 절연막의 상부 일정 부분에 형성된 금속막을 제거하기 위해, 필수적으로 금속막 씨엠피 공정이 수반된다. 따라서, 금속막 씨엠피 공정 추가로 인해 공정이 복잡해지고 생산 원가가 증가되는 문제점이 있었다.However, in the related art, when a metal film is formed by applying a CVD or PVD process, the metal film is deposited not only inside the contact hole but also to an upper portion of the insulating layer. Essentially a metal film CMP process is involved. Therefore, there is a problem in that the process is complicated and the production cost is increased due to the addition of the metal film CMP process.

따라서, 상술한 종래 기술에 따른 문제점을 해결하고자, 본 발명의 목적은 전기도금 공정을 적용시켜 금속막을 선택적으로 콘택홀 내부에만 증착함으로써, 별도의 금속막 씨엠피 공정이 불필요한 금속배선 형성 방법을 제공하려는 것이다.Accordingly, in order to solve the above problems according to the related art, an object of the present invention is to apply a electroplating process to selectively deposit a metal film only inside the contact hole, thereby providing a method for forming a metal wiring, which does not require a separate metal film CMP process. I will.

도 1a 내지 도 1d는 종래 기술에 따른 금속 배선 형성 방법을 설명하기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of forming a metal wiring according to the prior art.

도 2a 내지 도 2c는 본 발명의 일실시예로서, 전기 도금 공정을 적용하여 선택적으로 금속 배선을 형성 방법을 설명하기 위한 공정단면도.2A to 2C are cross-sectional views illustrating a method of selectively forming a metal wiring by applying an electroplating process as an embodiment of the present invention.

도 3은 전기도금장치의 단면도.3 is a cross-sectional view of the electroplating apparatus.

도 4는 전기도금 공정에 의해 웨이퍼의 콘택홀에 선택적으로 금속을 증착시킨 것을 보인 웨이퍼 단면도.4 is a cross-sectional view of the wafer showing that the metal is selectively deposited in the contact hole of the wafer by the electroplating process.

상기 목적을 달성하고자, 본 발명에 따른 금속배선 형성 방법은 웨이퍼 위에 소정 형상의 전도체 패턴을 형성하는 단계와, 전도체 패턴을 포함한 웨이퍼 상에 절연막을 형성하는 단계와, 절연막을 선택 식각하여 상기 전도체 패턴의 일부를 노출시키는 콘택홀을 형성하는 단계와, 콘택홀을 포함한 웨이퍼에 전기도금 공정을 실시하여 선택적으로 콘택홀을 매립시키는 금속배선을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, the metallization method according to the present invention comprises the steps of forming a conductive pattern of a predetermined shape on the wafer, forming an insulating film on the wafer including a conductor pattern, and selectively etching the insulating film to the conductor pattern And forming a contact hole exposing a portion of the contact hole, and forming a metal wiring to selectively fill the contact hole by performing an electroplating process on the wafer including the contact hole.

이때, 상기 전기도금 공정은, 웨이퍼에 금속을 증착하되 콘택홀의 일정 높이까지 증착하는 단계와, 금속 증착이 완료된 웨이퍼를 회전시키는 단계를 추가한다.In this case, the electroplating process, the deposition of the metal on the wafer, the step of depositing to a certain height of the contact hole, and the step of adding the metal deposition is completed, the step of rotating the wafer is added.

(실시예)(Example)

도 2a 내지 도 2c는 본 발명의 일실시예로서, 전기 도금 공정을 적용하여 선택적으로 금속 배선을 형성 방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of selectively forming a metal wiring by applying an electroplating process as an embodiment of the present invention.

또한, 도 3은 전기도금장치의 단면도이며, 도 4는 전기도금 공정에 의해 웨이퍼의 콘택홀에 선택적으로 금속을 증착시킨 것을 보인 웨이퍼 단면도이다.3 is a cross sectional view of an electroplating apparatus, and FIG. 4 is a cross sectional view of a wafer in which a metal is selectively deposited in a contact hole of a wafer by an electroplating process.

본 발명의 일 실시예에 따른 금속배선 형성 방법은, 먼저, 도 2a에 도시된 바와 같이, 웨이퍼(10) 위에 웨이퍼 소정 부위에 잔류되는 전도체 패턴(11)을 형성한 다음, 상기 구조 전면에 절연막(12)을 형성한다.In the method for forming metal wirings according to an embodiment of the present invention, as shown in FIG. (12) is formed.

이어, 도 2b에 도시된 바와 같이, 상기 절연막(12) 위에 전도체 패턴(11)과 대응된 부분을 노출시키는 감광막 패턴(15)을 형성하고, 상기 감광막 패턴(15)을 마스크로 절연막을 식각하여 콘택홀(13)을 형성한다.Subsequently, as shown in FIG. 2B, a photosensitive film pattern 15 is formed on the insulating film 12 to expose a portion corresponding to the conductor pattern 11, and the insulating film is etched using the photosensitive film pattern 15 as a mask. The contact hole 13 is formed.

그런 다음, 감광막 패턴을 제거하고 나서, 도 2c에 도시된 바와 같이, 전기도금 공정을 실시하여 콘택홀(13)을 매립시키는 금속 배선(14)을 형성한다.Then, after removing the photoresist pattern, as shown in FIG. 2C, an electroplating process is performed to form the metal wiring 14 to fill the contact hole 13.

이하에서, 전기 도금 공정에 의해 금속 배선(14)이 증착되는 과정을 상세하게 설명하기로 한다.Hereinafter, the process of depositing the metal wire 14 by the electroplating process will be described in detail.

도 3에 도시된 바와 같이, 먼저 실리콘 웨이퍼(10)를 작업 셀(20)에 장착시킨 다음, 작업 셀(20)에 기준 전극(22)과 상대전극(23)을 각각 설치한다. 이때, 기준전극(22)으로는 수소기준전극을 들 수 있으며, 상대전극(23)으로는 백금전극을 들 수 있다. 상기 작업셀(20)은 금속 양이온(M+)이 포함되어 있는 전해질(21)이 저장되어 있는 용기를 의미한다. 또한, 웨이퍼(10) 하부에는 웨이퍼를 회전시킬 수 있는 장치가 부착되어 있다.As shown in FIG. 3, the silicon wafer 10 is first mounted on the work cell 20, and then the reference electrode 22 and the counter electrode 23 are respectively installed in the work cell 20. In this case, the reference electrode 22 may include a hydrogen reference electrode, and the counter electrode 23 may include a platinum electrode. The working cell 20 refers to a container in which an electrolyte 21 containing metal cations (M +) is stored. Further, a device capable of rotating the wafer is attached to the lower portion of the wafer 10.

이어, 전해질(21) 내의 금속 양이온(M+)이 웨이퍼(10) 상의 절연막(12) 사이로 노출된 전도체 패턴(11) 부분에서 금속으로 환원될 수 있는 환원전위 만큼 인가한다. 상기 전위를 인가함에 따라, 절연막(12) 사이의 전도체 패턴(11) 부분에 금속이 증착되기 시작하며, 상기 금속이 절연막(12)의 상부 일정부분까지 증착되어지면 실리콘 웨이퍼를 회전시킨다. 이때, 상기 웨이퍼를 회전시키게 되면, 도 4에 도시된 바와 같이, 웨이퍼 표면에 전해질의 흐름(flux)이 생기고, 상기 전해질의 유속에 따라 절연막 사이에 소용돌이(vortex)(30)가 발생하게 된다. 이러한소용돌이(30)는 절연막(12) 사이에 증착된 금속막에 수직 방향으로 발생하면서 그 깊이에 따라 전해질 유속의 크기가 달라지게 된다. 이렇게 발생하는 깊이에 따른 유속의 차이는전도체 패턴(11) 부분에 전달되는 전해질 속의 금속이온의 농도 차이를 유발하게 되고, 소용돌이(30)의 중심부에서는 전해질의 흐름이 없게 되어 전달되는 금속이온의 농도가 제로(zero)가 되는 지점(31)이 나타나게 된다.Subsequently, the metal cations M + in the electrolyte 21 are applied as much as the reduction potential that can be reduced to the metal in the portion of the conductor pattern 11 exposed between the insulating films 12 on the wafer 10. As the potential is applied, metal begins to be deposited on portions of the conductor pattern 11 between the insulating layers 12, and when the metal is deposited to a predetermined portion of the upper surface of the insulating layer 12, the silicon wafer is rotated. At this time, when the wafer is rotated, as shown in FIG. 4, a flux of electrolyte is generated on the surface of the wafer, and a vortex 30 is generated between the insulating layers according to the flow rate of the electrolyte. The whirlpool 30 is generated in a direction perpendicular to the metal film deposited between the insulating films 12, and the size of the electrolyte flow rate varies according to its depth. The difference in flow rate according to the depth generated in this way causes a difference in the concentration of metal ions in the electrolyte delivered to the conductor pattern 11 portion, and the concentration of the metal ions delivered due to the absence of electrolyte flow in the central portion of the vortex 30. A point 31 at which zero becomes zero will appear.

따라서, 금속이온의 농도가 제로가 되는 지점(31)에서는 전기화학적으로 반응할 수있는 반응물의 농도가 제로가 되므로, 더 이상 금속증착이 일어나지 않는다.Therefore, since the concentration of the reactants capable of reacting electrochemically becomes zero at the point 31 where the concentration of the metal ions becomes zero, metal deposition no longer occurs.

이처럼, 금속이온의 농도가 제로가 되는 지점(31)은 웨이퍼 표면에 형성되는 전해질 유속과, 금속이 증착되어지는 절연막 사이의 간격, 전해질 속의 금속이온의 농도에 의해 결정되어지므로, 상기 3가지 요소를 조절하면 원하고자 하는 지점까지 금속을 증착시킬 수 있다.As such, the point 31 at which the concentration of the metal ions becomes zero is determined by the flow rate of the electrolyte formed on the wafer surface, the interval between the insulating film on which the metal is deposited, and the concentration of the metal ions in the electrolyte. By adjusting, the metal can be deposited to the desired point.

이상에서와 같이, 본 발명은 금속도금 공정을 적용시켜 선택적으로 콘택홀을 매립시키는 금속배선을 형성함으로써, 별도의 금속막 씨엠피 공정이 불필요하게 된다. 즉, 본 발명에서는 금속이 콘택홀 내부에만 선택적으로 증착됨으로써, 기존의 절연막의 상부 일정 부분에 형성된 금속막을 제거하기 위해, 필수적으로 수반되는 금속막 씨엠피 공정이 불필요하게 된다.As described above, the present invention applies a metal plating process to form a metal wiring to selectively fill the contact holes, so that a separate metal film CMP process is unnecessary. That is, in the present invention, since the metal is selectively deposited only inside the contact hole, in order to remove the metal film formed on the upper portion of the existing insulating film, the metal film CMP process, which is essentially required, is unnecessary.

따라서, 본 발명은 금속막 씨엠피 공정이 생략되어 전체 공정이 단순화되고, 생산 원가가 절감되는 이점이 있다.Therefore, the present invention has the advantage that the metal film CMP process is omitted, thereby simplifying the overall process and reducing the production cost.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

웨이퍼 위에 소정 형상의 전도체 패턴을 형성하는 단계와,Forming a conductive pattern of a predetermined shape on the wafer, 상기 전도체 패턴을 포함한 웨이퍼 상에 절연막을 형성하는 단계와,Forming an insulating film on the wafer including the conductor pattern; 상기 절연막을 선택 식각하여 상기 전도체 패턴의 일부를 노출시키는 콘택홀을 형성하는 단계와,Selectively etching the insulating layer to form a contact hole exposing a portion of the conductor pattern; 상기 콘택홀을 포함한 웨이퍼에 전기도금 공정을 실시하여 선택적으로 콘택홀을 매립시키는 금속배선을 형성하는 단계를 포함한 것을 특징으로 하는 금속배선 형성 방법.And forming a metal wiring to selectively fill the contact hole by performing an electroplating process on the wafer including the contact hole. 제 1항에 있어서, 상기 전기도금 공정은,The method of claim 1, wherein the electroplating process, 상기 웨이퍼에 금속을 증착하되, 상기 콘택홀의 일정 높이까지 증착하는 단계와,Depositing a metal on the wafer, and depositing a metal to a predetermined height of the contact hole; 상기 금속 증착이 완료된 웨이퍼를 회전시키는 단계를 추가하는 것을 특징으로 하는 금속배선 형성 방법.And rotating the wafer on which the metal deposition is completed.
KR1020030041576A 2003-06-25 2003-06-25 method for fabricating metal line KR20050000968A (en)

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