KR20040072454A - Single Electron Spin Controllable Nanodevice - Google Patents
Single Electron Spin Controllable Nanodevice Download PDFInfo
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- KR20040072454A KR20040072454A KR1020030008961A KR20030008961A KR20040072454A KR 20040072454 A KR20040072454 A KR 20040072454A KR 1020030008961 A KR1020030008961 A KR 1020030008961A KR 20030008961 A KR20030008961 A KR 20030008961A KR 20040072454 A KR20040072454 A KR 20040072454A
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- 238000000034 method Methods 0.000 claims abstract description 31
- 239000002096 quantum dot Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 239000012212 insulator Substances 0.000 claims abstract description 3
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 3
- 239000003302 ferromagnetic material Substances 0.000 claims description 5
- 238000000609 electron-beam lithography Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000001914 filtration Methods 0.000 claims 1
- 238000001338 self-assembly Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 230000005291 magnetic effect Effects 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 241000549556 Nanos Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7613—Single electron transistors; Coulomb blockade devices
Abstract
Description
최근 들어 거대자기저항(Giant Magneto Resistance) 현상을 이용한 자기 다층막 구조가 하드디스크 드라이브에 사용되는 자기저항 헤드나 MRAM(Magnetoresistive Random Access Memory) 같은 고속 정보 처리가 요구되는 디바이스에 응용이 활발하게 진행되고 있다. 이러한 디바이스들은 외부 자기장의 변화에 따라 다층막 내부의 저항이 변하는 현상을 이용하고 있으며, 이것을 자기저항(Magneto Resistance, MR) 이라고 한다. 이 거대 자기저항현상은 다층막 또는 granular 구조를 가진 재료에서 스핀 의존 산란 의해 발생된다고 이해되고 있다. 거대자기저항(GMR) 재료는 구조에 따라 스핀 밸브구조, 인공 초격자 구조, granular, 터널형 자기 저항 구조로 나눌 있다. 인공 초격자 구조나 granular 구조의 경우는 자기 저항비는 크지만 포화자계가 커서 실용화하기에는 더 연구가 필요하다. 스핀밸브 구조의 경우 포화자계가 작아서 재생헤드로 적용이 가능하지만 memory 재료로 사용하기에는 MR비가 작다. 이와는 다른 형태의 자기저항 현상을La1/3Ca2/3MnO3 와 같은 망간계 perovskites에서 볼 수 있는데, 이를 초거대자기저항(Colossal Magnetoresistance, CMR)이라 부른다. CMR 현상은 수백% 이상의 높은 자기 저항비를 보이지만 포화자장이 매우 크고 온도의존성이 큰 단점을 보이고 있다. 터널형 자기저항(Tunneling Magneto-Resistance, TMR). TMR 현상은 GMR의 발견보다 앞선 1975년 Julliere에 의해 발견되어 연구되었지만 상온 자기 저항비를 나타내지 못하다가 1995년 Moodera가 열 진공증착 방법으로 제작한 CoFe/Al2O3/Co 구조의 터널접합에서 18%의 상온 자기저항을 발표하였으며 절연층 형성시 처음으로 플라즈마 산화법을 사용하였다. 비슷한 시기에 Miyazaki[7]는 Fe/Al2O3/Fe 구조에서 Al을 대기중에서 산화시켜 18%의 자기저항을 얻었으며, 이들의 발표이후 여러 연구자들에 의해 터널자기저항 현상이 연구되어오고 있다.Recently, the magnetic multilayer structure using the Giant Magneto Resistance phenomenon has been actively applied to devices requiring high-speed information processing such as magnetoresistive heads and magnetoresistive random access memory (MRAM) used in hard disk drives. . These devices use a phenomenon in which the resistance inside the multilayer film changes according to the change of the external magnetic field, and this is called a magnetoresistance (MR). This large magnetoresistance is understood to be caused by spin-dependent scattering in multi-layer or granular materials. Giant magnetoresistance (GMR) materials are divided into spin valve structure, artificial superlattice structure, granular and tunnel type magnetoresistance structure according to their structure. In the case of artificial superlattice and granular structures, the magnetoresistance ratio is large, but the saturation magnetic field is large, and further studies are needed to make it practical. In the case of spin valve structure, the saturation magnetic field is small so that it can be used as a playhead, but the MR ratio is small for use as a memory material. Another type of magnetoresistance can be seen in manganese perovskites such as La1 / 3Ca2 / 3MnO3, which is called Colossal Magnetoresistance (CMR). Although the CMR phenomenon shows a high magnetoresistance ratio of more than several hundred%, the saturation magnetic field is very large and the temperature dependency is high. Tunneling Magneto-Resistance (TMR). The TMR phenomenon was discovered and studied by Julliere in 1975 before GMR, but it did not show the room temperature magneto-resistance ratio. The magnetoresistance was announced and the first plasma oxidation was used to form the insulating layer. At the same time, Miyazaki [7] oxidized Al in the atmosphere in Fe / Al2O3 / Fe structure to obtain 18% magnetoresistance, and tunneling magnetoresistance has been studied by several researchers since their publication.
위와 같은 강자성체 및 최근 시도되고 있는 magnetic semiconductor의 적용에 의한 저온 내지는 상온 저항비는 현재 고밀도 하드디스크 드라이브나 MRAM등의 성공적인 상업화내지는 최종개발단계에까지 이르고 있으나, 이러한 적용은 본질적으로 CMOS 공정에 부가적이거나 추가적인 공정 및 장비의 개발이라는 어려운 점이 있다.The low to room temperature resistance ratios due to the application of ferromagnetic materials and magnetic semiconductors, which have been recently attempted, have reached the stage of successful commercialization of high-density hard disk drives and MRAMs. The challenge is the development of additional processes and equipment.
이에 대해 본 출원에서는 상기한 강자성체등 기존의 CMOS공정에 새로운 강자성체 물질의 적용을 통한 스핀전도도 천이현상에 의존하지 않고, 실리콘 전도영역이 단전자 소자의 영역만큼 국소화(양자점, Quantum Dot)될 때 나타나는 전자의 양자화 현상과 개개 전자의 스핀분극의 제어를 통해 종래와 구조적, 개념적인 면에서 획기적으로 다른 새로운 단일전자 스핀을 제어 할 수 있는 나노 스케일 소자의 작동방법을 제시한다.On the other hand, in the present application, spin conduction through the application of a new ferromagnetic material to the conventional CMOS process such as the ferromagnetic material does not depend on the transition phenomenon, and appears when the silicon conduction region is localized (quantum dot, quantum dot) as the region of a single electronic device. This paper presents a method of operating a nanoscale device that can control the novel single-electron spin, which is dramatically different from the conventional and structurally and conceptually through the control of electron quantization and control of spin polarization of individual electrons.
본 발명은 상기와 같은 기술적 요구에 대응하고 대용량, 저 전력, 초고집적의 단일전자 스핀제어 나노소자를 개발하기 위해서는 다음과 같은 기술적 성취가 필수적이다. CMOS공정과 전자빔 리소그래피법을 응용, 수십 나노미터폭 의 전도채널 양쪽측면으로 수십 나노미터 간격과 수직방향의 측면게이트를 형성시키는 공정과, 양자점1 과 양자점2 내부의 전자들의 스핀을 독립적으로 조절하기 위해 요구되어지는 상층게이트를 전자빔 리소그래피법을 적용 계산되어진 적절한 간격으로 양자점과 이격시켜 형성하는 공정 과 전도채널에 국소적으로 형성될 양자점을 제외한 나머지 측면게이트 및 소오스 드레인을 선택적으로 도핑하는 적절한 매개변수 및 공정이 필수적으로 요구되어진다.The present invention is required to meet the technical requirements as described above and to develop a large-capacity, low-power, ultra-high density single-electron spin control nanodevice as follows. Applying CMOS process and electron beam lithography to form side gates of several tens of nanometers in intervals and vertical directions on both sides of a conducting channel of several tens of nanometers in width, and to independently control the spin of electrons in quantum dots 1 and 2 The process of forming the upper gate required by the electron beam lithography method and spaced apart from the quantum dots at appropriate intervals calculated, and the appropriate parameters for selectively doping the remaining side gate and source drain except the quantum dots to be locally formed in the conduction channel. And processes are necessary.
도 1은 본 발명에 의한 단일전자 스핀제어 나노소자 전체의 개략도를 나타내 보인 사시도 이며,1 is a perspective view showing a schematic diagram of an entire single-electron spin control nanodevice according to the present invention,
도 2는 본 발명에 의한 단일전자 스핀제어 나노소자의 측면게이트의 작동시 양자점이 형성되어지는 부분을 개념적으로 나타낸 사시도 이고,FIG. 2 is a perspective view conceptually illustrating a portion where a quantum dot is formed during operation of a side gate of a single electron spin control nano device according to the present invention; FIG.
도 3은 본 발명에 의한 단일전자 스핀제어 나노소자의 상층제어게이트가 완성되어진 사시도이다.3 is a perspective view of the upper layer control gate of the single electron spin control nano device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
1: 실리콘 기판1: silicon substrate
2: 실리콘 산화막2: silicon oxide film
3: 소오스3: source
4: 드레인4: drain
5: 전도채널5: conduction channel
6: 측면게이트6: side gate
7: 양자점17: QD1
8: 양자점28: QD2
9: 게이트산화막9: gate oxide film
10: 상층게이트110: upper gate 1
11: 상층게이트211: upper gate 2
12: 층간절연막12: interlayer insulating film
13: 제어게이트13: control gate
본 발명의 단일전자스핀제어 나노소자는 SOI(Silicon on Insulator)기판 위에 형성되며 본 소자의 구조는 실리콘 기판(1)위 실리콘 이중산화막(2) 위의 위층 실리콘층에 소오스(3) 및 드레인(4)이 수십 나노 넓이의 전도채널(5)로 연결되어 있으며, 동일 평면상에 전도채널과 수직방향으로 측면게이트(6)에 인가된 음의 전기적 척력으로 전도채널에 양자점(7,8)이 형성되어지며, 이후 게이트 산화막(9)이 적층되어있으며, 2개 양자점의 전기적 포텐샬을 독립적으로 조절하는 상층게이트(10,11)가 양자점과 적절한 간격으로 위치하고, 이후 층간절연막(12)이 적층되며, 마지막으로 전도채널에 이차원 전자 개스층을 유발하는 제어게이트(13)가 형성되면, 본 발명의 목적인 단일전자 스핀제어 나노소자의 완성이 이루어진다.The single-electron spin control nanodevice of the present invention is formed on a silicon on insulator (SOI) substrate, and the structure of the device is a source (3) and a drain (3) in an upper silicon layer on a silicon double oxide film (2) on a silicon substrate (1). 4) are connected to the conduction channel 5 of several tens of nanometers wide, and the quantum dots 7 and 8 are formed on the conduction channel by the negative electrical repulsive force applied to the side gate 6 in the direction perpendicular to the conduction channel on the same plane. After that, the gate oxide film 9 is stacked, and the upper gates 10 and 11 which independently control the electrical potential of the two quantum dots are positioned at appropriate intervals with the quantum dots, and then the interlayer insulating film 12 is stacked. Finally, when the control gate 13 to induce the two-dimensional electron gas layer is formed in the conduction channel, the completion of the single-electron spin control nano device of the present invention.
본 발명의 단일전자스핀제어 나노소자의 제조방법을 첨부된 도면을 참조하여 보다 자세히 설명하면 다음과 같다.Referring to the accompanying drawings, a method for manufacturing a single electronic spin control nano device of the present invention will be described in detail as follows.
SOI 기판에서 단일전자스핀제어 나노소자 제작 시 사용되는 부분은 적절한 두께의 위층실리콘으로서,The part used in the fabrication of single electron spin-controlled nanodevices in SOI substrate is upper layer silicon of appropriate thickness.
먼저 전자선 직접 묘화(electron-beam direct writing)법으로 소오스(3), 드레인(4) 및 수 내지 수십 나노 넓이의 전도채널(5)에 대해 수십 나노 간격, 수직방향의 측면게이트(6)를 패터닝한 후,First, patterning dozens of nano-spaced, vertical side gates 6 for the source 3, drain 4 and conduction channels 5 of several to tens of nanos wide by electron-beam direct writing. After
반응성 이온 식각(RIE)을 이용해 나머지 위층실리콘을 모두 제거한다(도2).Reactive ion etching (RIE) is used to remove all remaining upper silicon (Figure 2).
이후 양자점(7,8)이 형성될 전도채널 중앙부분을 제외한 나머지 위층실리콘층을 도핑하기위해 네거티브 전자빔 레지스트 및 리소그래피법으로 전도채널 중앙부분을 패터닝 및 현상하여 도핑마스크로 사용, 적절한 매개 변수에 의한 도핑공정을 실시한다(도2),Subsequently, the doping mask is patterned and developed using a negative electron beam resist and lithography method to dope the remaining silicon layer except for the center portion of the conductive channel where the quantum dots (7,8) are to be formed and used as a doping mask. Doping process is performed (Fig. 2).
이후 절적한 두께 수 나노미터의 게이트 산화막(9) 적층공정을 실시한다,After that, the lamination process of the gate oxide film 9 having a suitable thickness of several nanometers is performed.
상기공정 후 상층게이트(10,11)를 형성하게 될 폴리실리콘층을 적절한 두께수 나노미터로 적층한 다음, 전자빔 리소그래피법을 사용하여 상층게이트를 양자점과 적절한 간격에 위치시키며 동시에 패터닝한다, (도3)After the above process, the polysilicon layers, which will form the upper gates 10 and 11, are laminated with an appropriate thickness of several nanometers, and then the upper gates are positioned at appropriate intervals from the quantum dots using an electron beam lithography method. 3)
이후 RIE공정을 시행하여 상층게이트 이외의 나머지 폴리실리콘층을 제거한다,After that, the RIE process is performed to remove the remaining polysilicon layers other than the upper gate.
상기공정 후 통상적인 도핑공정을 실시하여 상층게이트(10,11)의 금속화 공정을 완료한 후,After completing the metallization process of the upper gates (10, 11) by performing a conventional doping process after the above step,
층간절연막(12)을 적절한 방법으로 적층한 후,After the interlayer insulating film 12 is laminated in an appropriate manner,
제어게이트(13)를 포토리소그래피법을 이용, 2개의 양자점을 덮을 만큼 충분한 크기로 패터닝한 후, 기타 적절한 방법에 의한 식각공정 및 금속화 공정을 실시한다, 이후 통상적 CMOS공정이 이루어지면 본 단일전자 스핀제어 나노소자의 완성이 이루어진다.(도1)The control gate 13 is patterned to a size sufficient to cover the two quantum dots using a photolithography method, followed by etching and metallization by other suitable methods. The spin control nanodevice is completed (Fig. 1).
본 단일전자 스핀제어 나노소자의 공정 및 작동의 특성은 통상적인 CMOS공정에 준하며, 전자 하나 하나의 스핀을 의도된바 제어할 수 있으며 따라서 드레인 으로 나가는 전자의 스핀을 의도된바 필터링 할 수 있는 동작 특성을 보인다. 이는 현재까지의 스핀트로닉스의 기반이 되는 거대 자기저항(Giant Magneto Resistance) 현상에 의한 전자들의 스핀일치에 의한 전도도의 변화에 기반을 두는 것이 아니라, 매우 국소화된 양자점의 에너지 준위에 있어서의 전자의 스핀의존채움 현상을 이용함으로써 가능해진다. 이는 또한 강자성 물질의 도입 및 별도공정이 요구되지 않아 기존의 CMOS공정을 그대로 활용할 수 있다는 장점이 크게 부각된다고 할 수 있다. 아울러 본 단일전자 스핀제어 나노소자는 기본 소자의 단위가 전자 한개 이므로 향후 차세대 초고집적 저전력 소자로 각광받을 것으로 예상되는 단전자트랜지스터의 장점을 그대로 활용할 뿐만 아니라 본 소자의 기능만으로도 현재의 2진번 연산에 전자의 스핀 블락케이트를 활용, 3진법 연산이 가능하게 되며, 또한 본소자의 구조를 필요한 요구에 따라 여러 가지로 구조를 변경 및 활용할 수 있다는 점에서 매우큰 가치를 지니고 있다.The process and operation characteristics of the single-electron spin control nanodevice are similar to those of a conventional CMOS process, and the operation of the spin of electrons intended to control the spin of each electron to the drain can be controlled as desired. Show characteristics. This is not based on the change in conductivity due to spin-matching of electrons caused by the Giant Magneto Resistance phenomenon, which has been the basis of spintronics to date, but the spin of electrons at highly localized quantum dot energy levels. This can be done by using the dependency filling phenomenon. In addition, the introduction of the ferromagnetic material and the separate process is not required, it can be said that the advantage that the existing CMOS process can be used as it is. In addition, this single-electron spin-controlled nanodevice has only one electron unit, so it will not only utilize the advantages of single-electron transistors, which are expected to be spotlighted as the next-generation ultra-high-density low-power devices. The use of the spin block of the former makes it possible to perform a ternary operation, and also has great value in that the structure of the device can be changed and utilized in various ways according to the required requirements.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100650416B1 (en) * | 2005-04-02 | 2006-11-27 | 한국과학기술연구원 | Hybrid type ferromagnet/ semiconductor nano wire spin device and fabrication method thereof |
| KR100697779B1 (en) * | 2005-03-05 | 2007-03-20 | 한국과학기술연구원 | Hybrid ferromagnet/si semiconductor spin device using silicon on insulator soi and its fabrication method |
| KR100765962B1 (en) * | 2005-12-30 | 2007-10-11 | 서울시립대학교 산학협력단 | Fabrication method of In-plane-gate Quantum Dot Transistor |
| KR100796281B1 (en) * | 2006-02-28 | 2008-01-21 | 서울시립대학교 산학협력단 | Spin Dependent Single Electron Transistor |
| KR100884525B1 (en) * | 2007-09-19 | 2009-02-18 | 한국표준과학연구원 | Single electron transistor for spin quibit dection and fabrication method thereof |
| CN108428627A (en) * | 2018-03-28 | 2018-08-21 | 中国科学技术大学 | A kind of method of automatically controlled GaAs/AlGaAs semiconductor-quantum-points potential well |
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| KR100926773B1 (en) | 2007-10-24 | 2009-11-16 | 서울시립대학교 산학협력단 | Control inverted gate and logic circuit including the same |
| KR100997274B1 (en) | 2008-08-26 | 2010-11-29 | 서울시립대학교 산학협력단 | Control of electron spin in quantum structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100697779B1 (en) * | 2005-03-05 | 2007-03-20 | 한국과학기술연구원 | Hybrid ferromagnet/si semiconductor spin device using silicon on insulator soi and its fabrication method |
| KR100650416B1 (en) * | 2005-04-02 | 2006-11-27 | 한국과학기술연구원 | Hybrid type ferromagnet/ semiconductor nano wire spin device and fabrication method thereof |
| KR100765962B1 (en) * | 2005-12-30 | 2007-10-11 | 서울시립대학교 산학협력단 | Fabrication method of In-plane-gate Quantum Dot Transistor |
| KR100796281B1 (en) * | 2006-02-28 | 2008-01-21 | 서울시립대학교 산학협력단 | Spin Dependent Single Electron Transistor |
| KR100884525B1 (en) * | 2007-09-19 | 2009-02-18 | 한국표준과학연구원 | Single electron transistor for spin quibit dection and fabrication method thereof |
| CN108428627A (en) * | 2018-03-28 | 2018-08-21 | 中国科学技术大学 | A kind of method of automatically controlled GaAs/AlGaAs semiconductor-quantum-points potential well |
| CN108428627B (en) * | 2018-03-28 | 2021-03-09 | 中国科学技术大学 | Method for electrically controlling GaAs/AlGaAs semiconductor quantum dot potential well |
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