KR20040058975A - 확산방지막 형성방법 및 이를 이용한 반도체 소자의금속배선 형성방법 - Google Patents
확산방지막 형성방법 및 이를 이용한 반도체 소자의금속배선 형성방법 Download PDFInfo
- Publication number
- KR20040058975A KR20040058975A KR1020020085497A KR20020085497A KR20040058975A KR 20040058975 A KR20040058975 A KR 20040058975A KR 1020020085497 A KR1020020085497 A KR 1020020085497A KR 20020085497 A KR20020085497 A KR 20020085497A KR 20040058975 A KR20040058975 A KR 20040058975A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- diffusion barrier
- forming
- depositing
- tin
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 71
- 238000009792 diffusion process Methods 0.000 title claims abstract description 32
- 230000004888 barrier function Effects 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims description 22
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 11
- 230000009977 dual effect Effects 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000005137 deposition process Methods 0.000 claims description 9
- 239000002243 precursor Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 2
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 claims description 2
- 230000006378 damage Effects 0.000 claims 1
- 230000002265 prevention Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 39
- 239000011229 interlayer Substances 0.000 abstract description 13
- 238000005240 physical vapour deposition Methods 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 4
- 239000011800 void material Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 78
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052731 fluorine Inorganic materials 0.000 description 8
- 239000011737 fluorine Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910020177 SiOF Inorganic materials 0.000 description 3
- 229910021426 porous silicon Inorganic materials 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
- (a) 비아가 형성된 반도체 기판을 제공하는 단계;(b) CVD 방식을 이용한 증착공정을 실시하여 상기 비아의 내부면을 따라 TiN막을 증착하는 단계; 및(c) 이온화된 PVD 방식을 이용한 증착공정을 실시하여 상기 TiN막 상에 Ta막을 증착하는 단계를 포함하는 것을 특징으로 하는 확산방지막 형성방법.
- 제 1 항에 있어서,상기 CVD 방식은 TiCl4, TDMAT, TDEAT 및 TEMAT의 전구체들 중 어느 하나의 전구체를 0.1초 내지 1분 동안 10 내지 1000sccm의 유량으로 공급하고, 200 내지 700℃의 온도에서 0.5 내지 2Torr의 압력으로 실시하는 것을 특징으로 하는 확산방지막 형성방법.
- 제 1 항에 있어서,상기 TiN막은 5 내지 200Å의 두께로 형성하는 것을 특징으로 하는 확산 방지막 형성방법.
- 제 1 항에 있어서,상기 이온화된 PVD 방식은 상기 CVD 공정후 진공 파괴없이 실시하는 것을 특징으로 하는 확산방지막의 형성방법.
- 제 1 항에 있어서,상기 이온화된 PVD 방식은 40 내지 60℃의 온도에서 5 내지 7mTorr의 압력과 10 내지 20kW의 전력으로 실시하되, Ar 가스의 유입량을 100 내지 120sccm으로 하여 실시하는 것을 특징으로 하는 확산 방지막 형성방법.
- 제 1 항에 있어서,상기 Ta막은 1 내지 50Å의 두께로 형성하는 것을 특징으로 하는 확산방지막 형성방법.
- 제 1 항에 있어서,상기 Ta막은 0.1 내지 5%의 정도의 질소를 더 포함하는 것을 특징으로 하는확산방지막 형성방법.
- (a) 싱글 다마신 공정 또는 듀얼 다마신 공정을 실시하여 다마신 패턴이 형성된 반도체 기판을 제공하는 단계;(b) CVD 방식을 이용한 증착공정을 실시하여 상기 다마신 패턴의 내부면을 따라 TiN막을 증착하는 단계; 및(c) 이온화된 PVD 방식을 이용한 증착공정을 실시하여 상기 TiN막 상에 Ta막을 증착하고, 이로 인해 상기 TiN막과 상기 Ta막으로 이루어진 이중막의 확산방지막을 형성하는 단계;(d) 상기 다마신 패턴을 갭 필링하도록 전체 구조 상부에 금속막을 증착하는 단계; 및(e) 상기 금속막을 평탄화하여 상기 다마신 패턴을 매립하도록 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 금속배선 형성방법.
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KR10-2002-0085497A KR100475529B1 (ko) | 2002-12-27 | 2002-12-27 | 확산방지막 형성방법 및 이를 이용한 반도체 소자의금속배선 형성방법 |
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KR10-2002-0085497A KR100475529B1 (ko) | 2002-12-27 | 2002-12-27 | 확산방지막 형성방법 및 이를 이용한 반도체 소자의금속배선 형성방법 |
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KR20040058975A true KR20040058975A (ko) | 2004-07-05 |
KR100475529B1 KR100475529B1 (ko) | 2005-03-10 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100642908B1 (ko) * | 2004-07-12 | 2006-11-03 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
KR101198937B1 (ko) * | 2005-12-28 | 2012-11-07 | 매그나칩 반도체 유한회사 | 반도체 장치의 금속배선 형성방법 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20210036113A (ko) | 2019-09-25 | 2021-04-02 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
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- 2002-12-27 KR KR10-2002-0085497A patent/KR100475529B1/ko active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100642908B1 (ko) * | 2004-07-12 | 2006-11-03 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
KR101198937B1 (ko) * | 2005-12-28 | 2012-11-07 | 매그나칩 반도체 유한회사 | 반도체 장치의 금속배선 형성방법 |
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Publication number | Publication date |
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KR100475529B1 (ko) | 2005-03-10 |
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