KR20040056111A - Method of forming a metal line in a semiconductor device - Google Patents
Method of forming a metal line in a semiconductor device Download PDFInfo
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- KR20040056111A KR20040056111A KR1020020082660A KR20020082660A KR20040056111A KR 20040056111 A KR20040056111 A KR 20040056111A KR 1020020082660 A KR1020020082660 A KR 1020020082660A KR 20020082660 A KR20020082660 A KR 20020082660A KR 20040056111 A KR20040056111 A KR 20040056111A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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Abstract
Description
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 하부 배선 상부에 천이 금속 및 이들의 산화물 또는 절연물을 이용하여 확산 방지막을 형성하고, 전체 구조 상부에 층간 절연막을 형성한 후 층간 절연막의 소정 영역을 패터닝하여 다마신 패턴을 형성하며, 플라즈마 공정에 의해 클리닝 공정을 실시하는 동시에 확산 방지막을 리스퍼터링시켜 다마신 패턴 측벽에 증착되도록 함으로써 취약한 사이드월의 스텝커버러지를 향상시킬 수 있어 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, wherein a diffusion barrier film is formed on a lower wiring by using a transition metal and oxides or insulators thereof, an interlayer insulating film is formed on an entire structure, and a predetermined region of the interlayer insulating film is formed. Patterning to form damascene pattern, and cleaning process by plasma process and resputtering diffusion prevention film to be deposited on damascene pattern sidewall to improve step coverage of vulnerable sidewalls and improve wiring reliability. A metal wiring formation method of a semiconductor element which can be improved.
반도체 소자의 배선 재료로서 알루미늄 대신에 구리를 사용하는데, 그 이유는 구리의 낮은 비저항, EM(electromigration) 특성 향상, RC 딜레이 감소 등으로 알려져 있다. 또한, 배선폭이 점차 감소됨에 따라 배선의 신뢰성을 평가하는 항목인 EM 특성이 매우 중요하게 되는데, 구리의 고융점(1085℃)은 초기에 막연하게 구리의 EM 특성이 좋을 것이라는 기대를 낳았다. 그러나, 실제로는 공정에 따라서 이와는 매우 상반된 결과를 보이는 것으로 보고하고 있다. 즉, 알루미늄의 경우에는 표면에 매우 안정된 산화막이 형성되어 있어 소자의 구동시 다량의 전자 이동에 의한 원자의 이동이 주로 그레인 바운더리를 따라 일어나므로 그레인 바운더리를 줄이면 EM 특성이 향상됨을 기대할 수 있었다. 그런데, 구리의 경우는 표면에 안정된 산화막이 형성되지 않으므로 구리와 확산 방지막의 계면이 매우 취약하게 된다. 현재 확산 방지막으로 사용되는 SiN 또는 SiC 등은 구리와의 접착 특성이 좋지 않으므로 EM 평가시 대부분의 보이드가 이들 계면에서 발생한다. 또한, 확산 방지막을 형성하기 이전에 구리 상부에 형성된 산화막을 제거하기 위하여 Ar 스퍼터링을 이용한 클리닝 공정을 실시한다. 그런데, 이때 구리의 리스퍼터링(resputtering)에 의해 절연막이 오염되고 오염 물질이 패턴내의 사이드월에 응집되기 때문에 후속 확산 방지막의 스텝커버러지에 악영향을 미치는 문제점등이 있다.Copper is used instead of aluminum as a wiring material for semiconductor devices, because of low resistivity of copper, improvement of EM (electromigration) characteristics, reduction of RC delay, and the like. In addition, as the wiring width gradually decreases, the EM characteristic, which is an item for evaluating the reliability of the wiring, becomes very important. The high melting point (1085 ° C.) of copper initially gave an expectation that the EM characteristic of copper was vaguely good. In practice, however, the results show very contradictory results. That is, in the case of aluminum, a very stable oxide film is formed on the surface, and thus, the movement of atoms due to the large amount of electron movement during driving of the device mainly occurs along the grain boundary, and thus, the EM characteristic can be expected to be improved by reducing the grain boundary. However, in the case of copper, since a stable oxide film is not formed on the surface, the interface between copper and the diffusion barrier is very weak. SiN or SiC, which is currently used as a diffusion barrier, has poor adhesion properties with copper, so most voids occur at these interfaces during EM evaluation. In addition, a cleaning process using Ar sputtering is performed to remove the oxide film formed on the upper portion of the copper before forming the diffusion barrier. However, at this time, since the insulating film is contaminated by copper resputtering and the contaminants are aggregated on the sidewall in the pattern, there is a problem that adversely affects the step coverage of the subsequent diffusion barrier.
본 발명의 목적은 기존의 SiC 또는 SiN보다 접착성이 우수한 전이 금속 및 이들의 산화물 또는 질화물을 확산 방지막으로 이용함으로써 보이드의 발생을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of preventing the generation of voids by using a transition metal having better adhesion than conventional SiC or SiN and oxides or nitrides thereof as a diffusion barrier.
본 발명의 다른 목적은 확산 방지막으로 이용하는 전이 금속 및 이들의 산화물 또는 질화물을 리스퍼터링시켜 패턴의 사이드월에 증착되도록 함으로써 스텝커버러지를 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can improve step coverage by resputtering a transition metal and an oxide or nitride thereof used as a diffusion barrier and depositing the same on a sidewall of a pattern.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 제 1 층간 절연막11 semiconductor substrate 12 first interlayer insulating film
13 : 제 1 구리층 14 : 제 1 확산 방지막13 first copper layer 14 first diffusion barrier film
15 : 제 2 층간 절연막 16 : 제 2 확산 방지막15: second interlayer insulating film 16: second diffusion barrier film
17 : 제 3 확산 방지막 18 : 제 2 구리층17 third diffusion barrier film 18 second copper layer
본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 소정의 구조가 형성된 반도체 기판 상부에 제 1 층간 절연막을 형성한 후 상기 제 1 층간 절연막의 소정 영역을 식각하여 다마신 패턴을 형성하는 단계와, 상기 다마신 패턴이 매립되도록 제 1 구리층을 형성하여 하부 배선을 형성하는 단계와, 상기 하부 배선 상부에 제 1 확산 방지막을 형성하는 단계와, 전체 구조 상부에 제 2 층간 절연막을 형성한 후 상기 제 2 층간 절연막의 소정 영역을 식각하여 상기 제 1 확산 방지막을 노출시키는 다마신 패턴을 형성하는 단계와, 플라즈마 공정을 실시하여 상기 다마신 패턴을 클리닝하는 동시에 상기 제 1 확산 방지막을 리스퍼터링시켜 상기 패턴의 사이드월에 제 2 확산 방지막을 형성하는 단계와, 전체 구조 상부에 제 3 확산 방지막 및 시드층을 형성한 후 상기 다마신 패턴이 매립되도록 제 2 구리층을 형성하는 단계와, 상기 제 2 구리층 및 상기 제 3 확산 방지막을 연마하여 상부 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In the method of forming a metal wiring of a semiconductor device according to the present invention, forming a damascene pattern by etching a predetermined region of the first interlayer insulating film after forming a first interlayer insulating film on a semiconductor substrate having a predetermined structure; Forming a first copper layer to fill the damascene pattern, forming a lower wiring, forming a first diffusion barrier layer on the lower wiring, and forming a second interlayer insulating film on the entire structure, and then Etching a predetermined region of the second interlayer insulating film to form a damascene pattern exposing the first diffusion barrier layer; and performing a plasma process to clean the damascene pattern, while simultaneously resputtering the first diffusion barrier layer. Forming a second diffusion barrier layer on the sidewalls of the semiconductor layer, and forming a third diffusion barrier layer and a seed layer on the entire structure Polishing the second comprising the steps of: forming a copper layer, the barrier film and the second copper layer and said third diffusion such that the embedded pattern damascene group will be characterized by comprising a step of forming the upper wiring.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 제 1 층간 절연막(12)을 형성한다. 제 1 층간 절연막(12)의 소정 영역을 패터닝하여 다마신 패턴을 형성한다. 다마신 패턴이 매립되도록 전체 구조 상부에 제 1 구리층(13)을 형성한 후 CMP 공정을 실시하여 하부 배선을 형성한다. 이때, 제 1 구리층(13)의 상부에는 구리 산화막이 형성되는데, RF 플라즈마를 이용하여 제거함으로써 이후 공정에서 제 1 확산 방지막의 접착력을 향상시킨다. RF 플라즈마 공정은 Ar 또는 He등의 불활성 기체에 H2또는 NH3등의 환원성 기체를 혼합한 기체를 1mTorr∼10Torr의 압력에서 50∼1000W의 RF 플라즈마 파워를 인가하여 실시한다. 이때, 불활성 기체와 환원성 기체의 혼합 비율은 1:1∼1:100으로 한다.Referring to FIG. 1A, a first interlayer insulating layer 12 is formed on a semiconductor substrate 11 on which a predetermined structure is formed. A predetermined region of the first interlayer insulating film 12 is patterned to form a damascene pattern. The first copper layer 13 is formed on the entire structure to fill the damascene pattern, and then a lower wiring is formed by performing a CMP process. At this time, a copper oxide film is formed on the upper part of the first copper layer 13, and by using RF plasma, the adhesion of the first diffusion barrier layer is improved in a subsequent process. The RF plasma process is performed by applying 50-1000 W of RF plasma power to a gas in which a reducing gas such as H 2 or NH 3 is mixed with an inert gas such as Ar or He at a pressure of 1 mTorr to 10 Torr. At this time, the mixing ratio of the inert gas and the reducing gas is 1: 1 to 1: 100.
도 1(b)를 참조하면, 전체 구조 상부에 제 1 확산 방지막(14)을 형성한 후 제 1 구리층(13) 상부에만 잔류하도록 패터닝한다. 이때, 제 1 확산 방지막(14)은 Ta, TaN, TaC, WN, TiW, WBN, WC, TiN, TiN(Si)등의 천이 금속 및 그들의 산화물 또는 질화물 계열을 이용하여 20∼1000Å의 두께로 형성한다. 이들은 기존의 SiC 또는 SiN에 비하여 접착성이 매우 우수하다.Referring to FIG. 1B, the first diffusion barrier layer 14 is formed on the entire structure, and then patterned to remain only on the first copper layer 13. At this time, the first diffusion barrier 14 is formed to a thickness of 20 to 1000 kW using a transition metal such as Ta, TaN, TaC, WN, TiW, WBN, WC, TiN, TiN (Si), and oxides or nitrides thereof. do. They have very good adhesion compared to conventional SiC or SiN.
도 1(c)를 참조하면, 전체 구조 상부에 제 2 층간 절연막(15)을 형성한 후 제 2 층간 절연막(15)의 소정 영역을 패터닝하여 제 1 구리층(13) 상부의 제 1 확산 방지막(14)을 노출시키는 다마신 패턴을 형성한다. 다마신 패턴은 싱글 다마신 패턴 및 듀얼 다마신 패턴으로 형성할 수 있다. 그리고, 다마신 패턴을 형성하기 위한 식각 공정에서 발생된 불순물을 제거하기 위한 클리닝 공정을 Ar, N2, He 등의 기체를 이용한 플라즈마를 이용하여 실시한다. 그런데, 이러한 플라즈마 공정에 의해 제 1 확산 방지막(14)이 리스퍼터링되어 비아홀 측벽의 소정 영역에 제 2 확산 방지막(16)이 증착된다. 이러한 제 1 확산 방지막(14)의 리스퍼터링에 의해 형성된 제 2 확산 방지막(16)에 의해 다마신 패턴의 취약한 사이드월의 스텝커버러지 특성을 향상시킬 수 있다. 이때, Ar, N2, He 등을 이용한 플라즈마 공정은1mTorr∼10Torr의 압력에서 50∼1000W의 RF 플라즈마 파워를 인가하여 실시한다.Referring to FIG. 1C, after forming the second interlayer insulating layer 15 over the entire structure, a predetermined region of the second interlayer insulating layer 15 is patterned to form a first diffusion barrier layer on the first copper layer 13. A damascene pattern exposing (14) is formed. The damascene pattern may be formed of a single damascene pattern and a dual damascene pattern. In addition, a cleaning process for removing impurities generated in an etching process for forming a damascene pattern is performed using plasma using a gas such as Ar, N 2 , or He. However, the first diffusion barrier 14 is resputtered by the plasma process, and the second diffusion barrier 16 is deposited on a predetermined region of the sidewall of the via hole. The step diffusion characteristic of the weak sidewall of the damascene pattern can be improved by the second diffusion barrier film 16 formed by the resputtering of the first diffusion barrier film 14. At this time, the plasma process using Ar, N 2 , He and the like is carried out by applying a RF plasma power of 50 ~ 1000W at a pressure of 1mTorr ~ 10Torr.
도 1(d)를 참조하면, 전체 구조 상부에 제 3 확산 방지막(17) 및 시드층을 형성한 후 다마신 패턴이 매립되도록 전체 구조 상부에 제 2 구리층(18)을 형성한다. 그리고, 200∼500℃의 온도에서 10초∼30분동안 열처리 공정을 실시한 후 CMP 공정으로 제 2 구리층(18) 및 제 3 확산 방지막(17)을 연마하여 상부 배선을 형성한다. 여기서, 제 3 확산 방지막(16)은 Ta, TaN, TaC, WN, TiW, WBN, WC, TiN, TiN(Si)등의 천이 금속 및 그들의 산화물 또는 질화물 계열을 이용하여 20∼1000Å의 두께로 형성한다. 그리고, 시드층은 PVD 방법 또는 CVD 방법을 이용하여 50∼1500Å의 두께로 형성하고, 제 2 구리층(18)은 무전해 도금법, 전해 도금법, PVD 방법 또는 CVD 방법을 이용하여 형성한다.Referring to FIG. 1D, after forming the third diffusion barrier layer 17 and the seed layer on the entire structure, the second copper layer 18 is formed on the entire structure so that the damascene pattern is embedded. After the heat treatment is performed for 10 seconds to 30 minutes at a temperature of 200 to 500 ° C., the second copper layer 18 and the third diffusion barrier film 17 are polished by a CMP process to form an upper wiring. Here, the third diffusion barrier layer 16 is formed to a thickness of 20 to 1000 GPa using a transition metal such as Ta, TaN, TaC, WN, TiW, WBN, WC, TiN, TiN (Si), and oxides or nitrides thereof. do. The seed layer is formed to a thickness of 50 to 1500 kV using the PVD method or the CVD method, and the second copper layer 18 is formed using the electroless plating method, the electrolytic plating method, the PVD method, or the CVD method.
상술한 바와 같이 본 발명에 의하면 하부 배선 상부에 Ta, TaN, TaC, WN, TiW, WBN, WC, TiN, TiN(Si)등의 천이 금속 및 이들의 산화물 또는 절연물을 이용하여 확산 방지막을 형성하고, 전체 구조 상부에 층간 절연막을 형성한 후 층간 절연막의 소정 영역을 패터닝하여 다마신 패턴을 형성하며, 플라즈마 공정에 의해 클리닝 공정을 실시하는 동시에 확산 방지막을 리스퍼터링시켜 다마신 패턴 측벽에 증착되도록 함으로써 취약한 사이드월의 스텝커버러지를 향상시킬 수 있어 배선의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, a diffusion barrier is formed on the lower wiring by using transition metals such as Ta, TaN, TaC, WN, TiW, WBN, WC, TiN, TiN (Si), and oxides or insulators thereof. After the interlayer insulating film is formed over the entire structure, a predetermined region of the interlayer insulating film is patterned to form a damascene pattern. The cleaning process is performed by a plasma process, and the diffusion barrier is resputtered to be deposited on the damascene pattern sidewall. The step coverage of the weak sidewall can be improved, thereby improving the reliability of the wiring.
Claims (10)
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| KR1020020082660A KR20040056111A (en) | 2002-12-23 | 2002-12-23 | Method of forming a metal line in a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100967130B1 (en) * | 2008-01-02 | 2010-07-05 | 주식회사 하이닉스반도체 | Metal wiring of semiconductor device and method of manufacturing the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100967130B1 (en) * | 2008-01-02 | 2010-07-05 | 주식회사 하이닉스반도체 | Metal wiring of semiconductor device and method of manufacturing the same |
| US7855456B2 (en) | 2008-01-02 | 2010-12-21 | Hynix Semiconductor Inc. | Metal line of semiconductor device without production of high resistance compound due to metal diffusion and method for forming the same |
| US8159069B2 (en) | 2008-01-02 | 2012-04-17 | Hynix Semiconductor Inc. | Metal line of semiconductor device without production of high resistance compound due to metal diffusion and method for forming the same |
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