KR20040039982A - Method of manufacturing capacitor for semiconductor device - Google Patents
Method of manufacturing capacitor for semiconductor device Download PDFInfo
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- KR20040039982A KR20040039982A KR1020020068245A KR20020068245A KR20040039982A KR 20040039982 A KR20040039982 A KR 20040039982A KR 1020020068245 A KR1020020068245 A KR 1020020068245A KR 20020068245 A KR20020068245 A KR 20020068245A KR 20040039982 A KR20040039982 A KR 20040039982A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 claims description 34
- 229910003071 TaON Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000010926 purge Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 8
- 239000006200 vaporizer Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 4
- 230000005284 excitation Effects 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 230000008016 vaporization Effects 0.000 claims description 3
- 239000002070 nanowire Substances 0.000 claims 1
- 238000000231 atomic layer deposition Methods 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 91
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 Ru와 같은 금속막을 하부전극으로 하는 MIM 구조의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor having a MIM structure having a metal film such as Ru as a lower electrode.
일반적으로, 메모리셀에 사용되는 캐패시터는 스토리지(storage)용 하부 전극, 유전막, 및 플레이트(plate)용 상부전극으로 이루어지며, 제한된 면적 내에서큰 커패시턴스를 얻기 위해서는 얇은 유전체막 두께를 확보하거나, 3차원적인 캐패시터의 구조를 통해서 유효 면적을 증가시키거나, Ta2O5와 같은 고유전율의 유전막을 적용하는 등의 몇 가지 조건이 만족되어야만 한다.In general, a capacitor used in a memory cell is composed of a lower electrode for storage, a dielectric film, and an upper electrode for a plate, and in order to obtain a large capacitance within a limited area, a thin dielectric film thickness is obtained, or 3 Several conditions must be satisfied, such as increasing the effective area through the dimensional capacitor structure, or applying a high dielectric constant dielectric film such as Ta2O5.
한편, 하부전극이 폴리실리콘으로 이루어진 MIS(Metal/Insulator/ Polysilicon) 구조에 Ta2O5를 유전막으로 적용하게 되면, Ta2O5 형성 후 수행되는 고온의 열처리 공정시 폴리실리콘의 산화로 인하여 유효유전막 두께가 두꺼워져서 캐패시터 용량이 저하될 뿐만 아니라, MIS 구조 캐패시터의 자체의 비대칭 전류-전압 특성으로 인한 전류값의 변동에 의해 우수한 전기적 특성을 확보하기가 어렵다.On the other hand, if Ta2O5 is applied as a dielectric film to the MIS (Metal / Insulator / Polysilicon) structure made of polysilicon, the effective dielectric film thickness becomes thick due to oxidation of polysilicon during the high temperature heat treatment process performed after Ta2O5 formation. Not only is the capacity deteriorated, but also excellent electrical characteristics are difficult to secure due to the variation of the current value due to the asymmetric current-voltage characteristic of the MIS structure capacitor itself.
따라서, 예컨대 0.1㎛ 이하의 기술에서는 폴리실리콘 대신 하부전극 물질로서 Ru와 같은 금속막을 적용한 MIM(Metal/ Insulator/Metal) 구조를 채용하고 있다.Therefore, for example, technology of 0.1 μm or less employs a MIM (Metal / Insulator / Metal) structure in which a metal film such as Ru is applied as a lower electrode material instead of polysilicon.
그러나, Ru막은 캐패시터 산화막과의 부착력(adhesion)이 우수하지 못하여 Ru막과 캐패시터 산화막 사이의 계면에서 리프팅(lifting)을 유발하고, Ru막 내에 존재하는 산소 및 탄소 등에 의해 후속 열공정시 뭉침 현상 등을 야기시킴으로써 캐패시터의 형성을 어렵게 할 뿐만 아니라 캐패시터의 전기적 특성을 저하시키게 된다. 이를 해결하기 위하여, Ru막을 형성하기 전에 부착막으로서 TiN막, Ta2O5막, Al2O3막 등의 박막을 형성하거나, Ru막을 고온에서 증착하여 부착력을 향상시키는 방법 등에 대한 연구가 진행되고 있으나 실제 적용하는 데에는 아직 여러 가지 어려움이 있다.However, the Ru film does not have good adhesion to the capacitor oxide film, causing lifting at the interface between the Ru film and the capacitor oxide film, and causing agglomeration during subsequent thermal processes due to oxygen and carbon present in the Ru film. This makes the formation of the capacitor difficult and also degrades the electrical characteristics of the capacitor. In order to solve this problem, before forming a Ru film, a thin film such as a TiN film, a Ta2O5 film, an Al2O3 film, or the like is formed, or a method of improving the adhesion by depositing a Ru film at a high temperature has been studied. There are still many difficulties.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, Ru막을 하부전극으로 하는 MIM 구조의 캐패시터 제조시, 캐패시터 산화막과 Ru막 사이의 부착력을 향상시키고 Ru막의 막질을 개선하여 캐패시터 형성을 용이하게 함과 동시에 캐패시터의 전기적 특성을 향상시킬 수 있는 반도체 소자의 캐패시터제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, when manufacturing a capacitor of the MIM structure having the Ru film as the lower electrode, to improve the adhesion between the capacitor oxide film and the Ru film and to improve the film quality of the Ru film to form a capacitor It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device that can facilitate the improvement and improve the electrical characteristics of the capacitor.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 캐패시터 산화막10 semiconductor substrate 11 capacitor oxide film
12 : TaN막 13 : Ru막12: TaN film 13: Ru film
14 : Ta2O5막 15 : 제 2 금속막14 Ta2O5 film 15 Second metal film
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 소정의 공정이 완료된 반도체 기판 상에 캐패시터 산화막을 형성하는 단계; 캐패시터 산화막 상부에 부착막을 형성하는 단계; 부착막 상부에 하부전극용 제 1 금속막을 형성하는 단계; 제 1 금속막 상에 고유전율의 유전막을 형성하는 단계; 유전막을 열처리하는 단계; 및 유전막 상에 상부전극용 제 2 금속막을 형성하는 단계를 포함하고, 부착막은 TaN막으로 형성하고, 제 1 금속막은 ALD법에 의한 Ru막으로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the above object of the present invention comprises the steps of forming a capacitor oxide film on a semiconductor substrate is completed a predetermined process; Forming an adhesion layer on the capacitor oxide layer; Forming a first metal film for the lower electrode on the adhesion layer; Forming a dielectric film of high dielectric constant on the first metal film; Heat treating the dielectric film; And forming a second metal film for the upper electrode on the dielectric film, wherein the adhesion film is formed of a TaN film, and the first metal film is formed of a Ru film by an ALD method. Can be achieved by
여기서, TaN막은 TaON막을 증착한 후 이 TaON막을 환원하여 형성하는데, TaON막의 증착은 170 내지 190℃로 유지되는 기화기에서 소오스 개스인 Ta(OC2H5)5를 기상상태로 만든 후, 기상상태로 만들어진 소오스 개스와 반응개스인 NH3개스를 사용하여 반응로의 압력을 0.1 내지 2torr로 유지하면서 상기 기판이 300 내지 400℃로 가열된 상태에서 수행하고, 이때 NH3 개스의 유량은 10sccm 내지 5slm 정도로 조절한다. 또한, TaON막의 환원은 NH3 개스를 이용하여 RTP 나 노를 이용한 열처리로 수행하는데, RTP는 500 내지 700℃의 온도에서 30초 내지 20분 동안 수행하고, 이때 NH3 개스의 유량은 1000sccm 내지 10slm으로 조절한다.Here, the TaN film is formed by depositing a TaON film and then reducing the TaON film. The deposition of the TaON film is a source gas made of gaseous state Ta (OC2H5) 5 in a gaseous state in a vaporizer maintained at 170 to 190 ° C and then in a gaseous state. The substrate is heated to 300 to 400 ° C. while maintaining the pressure of the reactor at 0.1 to 2 torr using gas and NH 3 gas, which is a reaction gas, wherein the flow rate of the NH 3 gas is adjusted to about 10 sccm to 5 slm. In addition, the reduction of the TaON film is carried out by heat treatment using RTP nanostructure using NH3 gas, RTP is carried out for 30 seconds to 20 minutes at a temperature of 500 to 700 ℃, the flow rate of NH3 gas is adjusted to 1000sccm to 10slm do.
또한, ALD에 의한 Ru막의 형성시 기판의 온도는 200 내지 300℃로 조절하고 반응로의 압력은 0.2 내지 10torr로 유지한다. 바람직하게, ALD에 의한 Ru막의 형성은 소오스 개스인 Ru(od)3를 200 내지 230℃의 온도로 유지되는 기화기에서 기상상태로 만들어서 반응로로 0.1 내지 10초 동안 플로우시키는 제 1 공정과, 반응로를 제 1 퍼지하는 제 2 공정과, NH3 플라즈마를 여기시키는 제 3 공정과, 미반응 개스를 제거하기 위해 상기 반응로를 제 2 퍼지하는 제 4 공정과, 제 1 내지 제 4 공정을 소정 두께가 될 때까지 반복수행하는 제 5 공정으로 이루어진다. 바람직하게, 제 3 공정의 NH3 플라즈마 여기는 NH3 개스의 양을 10 내지 500sccm으로 조절하여 30 내지 500W의 R.F.전력과 0.2 내지 10torr의 압력에서 0.1 내지 10초 동안 수행하며, 제 1 및 제 2 퍼지는 1 내지 10 초 동안 N2 퍼지로 각각 수행한다.In addition, when the Ru film is formed by ALD, the temperature of the substrate is adjusted to 200 to 300 ° C. and the pressure of the reactor is maintained at 0.2 to 10 torr. Preferably, the formation of the Ru film by ALD reacts with a first process of flowing a source gas of Ru (od) 3 into a gaseous state in a vaporizer maintained at a temperature of 200 to 230 ° C. and flowing it into the reactor for 0.1 to 10 seconds. A second thickness of the first purge of the furnace, a third process of exciting the NH3 plasma, a fourth process of second purging the reactor to remove unreacted gas, and first to fourth processes It consists of a 5th process which repeats until it turns to. Preferably, the NH3 plasma excitation of the third process is performed for 0.1 to 10 seconds at an RF power of 30 to 500 W and a pressure of 0.2 to 10 torr by adjusting the amount of NH3 gas to 10 to 500 sccm, and the first and second purges are 1 to 2. Perform each with N2 purge for 10 seconds.
또한, 유전막은 Ta2O5막으로 형성하고, 유전막의 열처리는 650 내지 700℃의 온도에서 1 내지 30분 동안 수행하며, 제 2 금속막은 TiN막 또는 Ru막으로 형성한다.In addition, the dielectric film is formed of a Ta2O5 film, the heat treatment of the dielectric film is performed for 1 to 30 minutes at a temperature of 650 to 700 ℃, the second metal film is formed of a TiN film or Ru film.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 트랜지스터, 비트라인, 및 캐패시터의 스토리지 노드 콘택 등의 소정의 공정이 완료된 반도체 기판(10) 상에 캐패시터 산화막(11)을 형성한다. 여기서, 캐패시터 산화막(11)은 도시되지는 않았지만 컨캐이브(concave) 또는 실린더 구조의 캐패시터용 홀을 구비한다. 그 다음, 캐패시터 산화막(11) 상부에 이후 형성될 Ru막과 캐패시터 산화막과의 부착력을 향상시키기 위하여 부착막으로서 TaN막(12)을 형성한다. 여기서, TaN막(12)은 TaON막을 증착한 다음 이 TaON막을 환원시켜 형성한다. 더 상세하게, TaON막의 증착은 170 내지 190℃로 유지되는 기화기에서 소오스 개스인 Ta(OC2H5)5를 기상상태로 만든 후, 기상상태로 만들어진 소오스 개스와 반응개스인 NH3개스를 사용하여 반응로의 압력을 0.1 내지 2torr로 유지하면서 웨이퍼(기판)가 300 내지 400℃로 가열된 상태에서 수행한다. 바람직하게, NH3 개스의 유량은 10sccm 내지 5slm 정도로 조절한다. 또한, TaON막의 환원은 NH3 개스를 이용하여 급속열처리(Rapid Thermal Processing; RTP)나 노(furnace)를 이용한 열처리로 수행하는데, RTP 수행시에는 NH3 개스의 유량을 1000sccm 내지 10slm으로 조절하고, 500 내지 700℃의 온도에서 30초 내지 20분 동안 수행한다.Referring to FIG. 1A, a capacitor oxide layer 11 is formed on a semiconductor substrate 10 on which a predetermined process such as a transistor, a bit line, and a storage node contact of a capacitor is completed. Here, although not shown, the capacitor oxide film 11 includes a capacitor hole of a concave or cylinder structure. Next, a TaN film 12 is formed on the capacitor oxide film 11 as an adhesion film in order to improve the adhesion between the Ru film to be formed later and the capacitor oxide film. Here, the TaN film 12 is formed by depositing a TaON film and then reducing the TaON film. More specifically, the deposition of the TaON film is made by vaporizing the source gas Ta (OC2H5) 5 in the vapor phase in a vaporizer maintained at 170 to 190 ° C, and then using the source gas made in the vapor phase and NH3 gas as the reaction gas. The wafer (substrate) is heated to 300 to 400 ° C. while maintaining the pressure at 0.1 to 2 torr. Preferably, the flow rate of the NH 3 gas is adjusted to about 10 sccm to 5 slm. In addition, the reduction of the TaON film is carried out by heat treatment using Rapid Thermal Processing (RTP) or furnace using NH 3 gas. During RTP, the flow rate of NH 3 gas is adjusted to 1000 sccm to 10 slm, and 500 to It is carried out for 30 seconds to 20 minutes at a temperature of 700 ℃.
도 1b를 참조하면, TaN막(12) 상부에 캐패시터의 하부전극용 제 1 금속막으로서 Ru막(13)을 원자층증착(Atomic Layer Deposition; ALD)으로 형성하는데, 이때 웨이퍼(기판)의 온도는 200 내지 300℃로 조절하고 반응로의 압력은 0.2 내지10torr로 유지하도록 한다. 또한, ALD에 의한 Ru막(13)의 형성은 소오스 개스인 Ru(od)3를 200 내지 230℃의 온도로 유지되는 기화기에서 기상상태로 만들어서 반응로로 0.1 내지 10초 동안 플로우시키는 제 1 공정과, 반응로를 1 내지 10 초 동안 N2 퍼지(purge)하는 제 2 공정과, Ru막 내의 불순물을 제거하기 위해 NH3 플라즈마를 여기시키는 제 3 공정과, 미반응 개스를 제거하기 위해 반응로를 1 내지 10 초 동안 N2 퍼지하는 제 4 공정과, 제 1 내지 제 4 공정을 소정 두께가 될 때까지 반복수행하는 제 5 공정으로 이루어진다. 여기서, 제 3 공정의 NH3 플라즈마 여기는 NH3 개스의 양을 10 내지 500sccm으로 조절하여 30 내지 500W의 R.F.전력과 0.2 내지 10torr의 압력에서 0.1 내지 10초 동안 수행한다.Referring to FIG. 1B, the Ru film 13 is formed by atomic layer deposition (ALD) on the TaN film 12 as the first metal film for the lower electrode of the capacitor, wherein the wafer (substrate) temperature is formed. Is adjusted to 200 to 300 ℃ and the pressure of the reactor to maintain 0.2 to 10 torr. In addition, the formation of the Ru film 13 by ALD is the first step of making the source gas Ru (od) 3 into a gaseous state in a vaporizer maintained at a temperature of 200 to 230 ° C and flowing it into the reactor for 0.1 to 10 seconds. A second process of purging the N2 reactor for 1 to 10 seconds, a third process of exciting the NH3 plasma to remove impurities in the Ru film, and a reactor to remove unreacted gas. And a fourth step of purging N2 for 10 seconds and a fifth step of repeatedly performing the first to fourth steps until a predetermined thickness is obtained. Here, the NH3 plasma excitation of the third process is performed for 0.1 to 10 seconds at an R.F. power of 30 to 500 W and a pressure of 0.2 to 10 torr by adjusting the amount of NH3 gas to 10 to 500 sccm.
도 1c를 참조하면, Ru막(13) 상부에 캐패시터의 유전막으로서 고유전율의 Ta2O5막(14)을 형성한다. Ta2O5막(14)의 증착은, 먼저 Ta(OC2H5)5를 170 내지 190℃로 유지되는 기화기에서 기상상태로 만들고, 기상상태로 만들어진 소오스 개스와 반응개스인 O2 개스를 사용하여 반응로의 압력을 0.1 내지 2torr로 유지하면서 웨이퍼(기판)가 300 내지 450℃로 가열된 상태에서 수행한다. 바람직하게, O2 개스의 유량은 10 내지 1000sccm 정도로 조절한다. 그 다음, Ta2O5막(14)의 결정화 및 막질개선을 위하여 N2 분위기로 650 내지 700℃의 온도에서 1 내지 30분 동안 열처리를 수행한다.Referring to FIG. 1C, a Ta 2 O 5 film 14 having a high dielectric constant is formed on the Ru film 13 as a dielectric film of a capacitor. The deposition of the Ta 2 O 5 film 14 first makes Ta (OC 2 H 5) 5 in a vapor phase in a vaporizer maintained at 170 to 190 ° C., and then pressurizes the pressure of the reactor using O 2 gas, which is a source gas and a reaction gas. It is performed while the wafer (substrate) is heated to 300 to 450 캜 while maintaining at 0.1 to 2 torr. Preferably, the flow rate of the O 2 gas is adjusted to about 10 to 1000 sccm. Then, heat treatment is performed for 1 to 30 minutes at a temperature of 650 to 700 ° C. in an N 2 atmosphere for crystallization and film quality improvement of the Ta 2 O 5 film 14.
그리고 나서, 도 1d에 도시된 바와 같이, Ta2O5막(14) 상부에 상부전극용 제 2 금속막(15)을 형성하여 MIM 구조의 캐패시터를 형성한다. 바람직하게, 제 2 금속막(15)은 TiN막 또는 Ru막으로 캐패시터의 상부전극(15)을 형성함으로써 MIM 구조의 캐패시터를 형성한다.Then, as shown in FIG. 1D, the second metal film 15 for the upper electrode is formed on the Ta 2 O 5 film 14 to form a capacitor having a MIM structure. Preferably, the second metal film 15 is a TiN film or a Ru film to form the upper electrode 15 of the capacitor to form a capacitor of the MIM structure.
상기 실시예에 의하면, Ru막과 캐패시터 산화막 사이에 TaN막을 형성하여 Ru막과 캐패시터 산화막 사이의 부착력을 향상시킴으로써 계면 사이에서의 리프팅을 방지할 수 있게 된다. 또한, Ru막을 ALD로 증착하여 형성함에 따라 증착시 Ru막 내에 존재하는 불순물을 제거함으로써 후속 열공정시 Ru막 내의 뭉침 현상 등을 효과적으로 방지할 수 있게 된다. 이에 따라, MIM 구조의 캐패시터 형성이 용이해질 뿐만 아니라, 캐패시터의 전기적 특성이 향상된다.According to the above embodiment, the TaN film is formed between the Ru film and the capacitor oxide film to improve the adhesion between the Ru film and the capacitor oxide film, thereby preventing lifting between the interfaces. In addition, since the Ru film is formed by depositing the ALD, it is possible to effectively prevent agglomeration in the Ru film during the subsequent thermal process by removing impurities present in the Ru film during deposition. As a result, not only the formation of the capacitor of the MIM structure is easy, but also the electrical characteristics of the capacitor are improved.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 Ru막을 하부전극으로 하는 MIM 구조의 캐패시터 제조시, 캐패시터 산화막과 Ru막 사이의 부착력을 향상시키고 Ru막의 막질을 개선함으로써 캐패시터 형성을 용이하게 함과 동시에 캐패시터의 전기적 특성을 향상시킬 수 있다.The present invention described above improves the adhesion between the capacitor oxide film and the Ru film and improves the film quality of the Ru film when the capacitor is manufactured with the MIM structure having the Ru film as the lower electrode, thereby facilitating the formation of the capacitor and at the same time improving the electrical characteristics of the capacitor. Can be.
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KR100869343B1 (en) * | 2007-08-31 | 2008-11-19 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor in semiconductor device |
US8298909B2 (en) | 2006-12-27 | 2012-10-30 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
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US8298909B2 (en) | 2006-12-27 | 2012-10-30 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
KR100869343B1 (en) * | 2007-08-31 | 2008-11-19 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor in semiconductor device |
US7816202B2 (en) | 2007-08-31 | 2010-10-19 | Hynix Semiconductor Inc. | Method for fabricating capacitor in semiconductor device |
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