KR20040039018A - Method for forming the Isolation Layer of Semiconductor Device - Google Patents
Method for forming the Isolation Layer of Semiconductor Device Download PDFInfo
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- KR20040039018A KR20040039018A KR1020020066635A KR20020066635A KR20040039018A KR 20040039018 A KR20040039018 A KR 20040039018A KR 1020020066635 A KR1020020066635 A KR 1020020066635A KR 20020066635 A KR20020066635 A KR 20020066635A KR 20040039018 A KR20040039018 A KR 20040039018A
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- trench
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- 238000002955 isolation Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 37
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000004544 sputter deposition Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 229910052786 argon Inorganic materials 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 abstract description 6
- 238000003486 chemical etching Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 보다 상세하게얕은 트렌치 소자격리(Shallow Trench Isolation; 이하 "STI"라고 한다)공정에 의해 소자분리막 프로파일(profile)을 구현하는 과정에서, 트렌치가 형성된 실리콘기판에 케미컬 식각 특성에 의해 오버 식각하여 트렌치 상부 모서리 영역에 기울기 60~70°의 슬로프진 실리콘기판 표면을 형성한 다음, 슬로프진 실리콘기판의 표면에 아르곤 가스를 스퍼터링 함으로써, 트렌치 상부 모서리의 라운딩 특성을 향상시킬 수 있고, 모우트 발생을 방지하여 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있도록 하는 소자분리막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a device isolation film of a semiconductor device, and more particularly, in a process of implementing a device isolation film profile by a shallow trench isolation (STI) process, Over-etched on the formed silicon substrate by chemical etching to form a sloped silicon substrate surface having a slope of 60 to 70 ° in the upper corner region of the trench, and then sputtering argon gas on the surface of the sloped silicon substrate, thereby The present invention relates to a device isolation film manufacturing method capable of improving rounding characteristics and preventing occurrence of moat to improve characteristics and reliability of semiconductor devices.
일반적으로 반도체 장치에서 널리 이용되는 선택산화에 의한 소자분리 방법 중 하나인종래의 국부산화막 (LOCal Oxidation of Silicon : 이하 "LOCOS"라 한다) 공정은 소자가 형성되는 실리콘기판에 먼저 패드산화막을 성장시키고 그 위에 산화방지마스크 물질인 패드질화막을 증착한 후 마스크를 이용한 노광 및 식각공정을 거쳐 소자분리막이 형성되는 지역을 설정하고 고온에서 습식 및 건식산화방식으로 두꺼운 산화막을 성장시켜 이 산화막을 소자분리막으로 사용하는 기술이다.The conventional LOCal Oxidation of Silicon (LOCOS) process, which is one of the device isolation methods by selective oxidation, which is widely used in semiconductor devices, is first grown on a silicon substrate on which a device is formed. After depositing a pad nitride film as an anti-oxidation mask material, the area where the device isolation film is formed is formed through an exposure and etching process using a mask, and a thick oxide film is grown by wet and dry oxidation at a high temperature to convert the oxide film into a device isolation film. It is a technique to use.
LOCOS 공정 방식에 있어서 측면산화에 의한 버드 빅 (Bird's beak)현상, 열 공정으로 유발되는 버퍼 층 응력에 의한 기판실리콘의 결정결함 및 채널저지를 위해 이온 주입된 불순물의 재 분포 등으로 인해서 반도체 소자의 전기적 특성 및 고집적화 추세에 문제가 되고 있어, LOCOS공정 방식 대체로 STI공정 방식을 도입하여 소자분리 방법에 적용하였다.In the LOCOS process, due to the phenomenon of bird's beak due to lateral oxidation, crystal defect of substrate silicon due to buffer layer stress caused by thermal process, and redistribution of impurities implanted for channel blocking, Due to the problem of electrical characteristics and high integration trend, STI process method is generally applied to device isolation method in place of LOCOS process method.
STI공정 또한 트렌치 후 프로파일에 가장자리 부위가 라운드하지 못하고 뾰족한 각을 가지는 프로파일이 되며 이 부위는 전자 영역이나 열에 의한 손상을 가장 많이 받으며 누설과 결함 발생의 원인이 된다.In the STI process, the edge of the profile after the trench is not rounded, but the profile has a sharp angle, which is the most damaged by the electronic region or the heat and causes leakage and defects.
이하, 첨부한 도면을 참고로 하여, 상기와 같은 종래 기술의 문제점을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings, it will be described in detail the problems of the prior art as described above.
도 1a 내지 도 1c는 종래 기술에 의한 소자분리막 제조방법을 나타내는 공정 순서도이다.1A to 1C are process flowcharts illustrating a method of manufacturing a device isolation film according to the prior art.
상기 종래 기술에 의한 소자분리막 제조방법에 따르면, 우선, 도 1a에 도시된 바와 같이, 실리콘 기판(10) 상에 패드산화막(20)과 소정의 두께를 갖고서 절연을 하도록 패드질화막(30)을 순차적으로 적층한 다음, 식각공정을 진행하여 트렌치(40)를 형성하였다.According to the device isolation film manufacturing method according to the related art, first, as shown in FIG. 1A, the pad nitride film 30 is sequentially insulated from the pad oxide film 20 on the silicon substrate 10 with a predetermined thickness. After stacking, the etching process was performed to form the trench 40.
그리고, 도 1b에 도시된 바와 같이, 상기 트렌치(40)가 형성된 부분에 전계효과(Field Effect) 집중으로 인한 누설전류를 방지하기 위하여 트렌치(40)의 내벽면을 산화 성장시켜 희생산화막(50)을 형성한 후, 상기 트렌치(40) 내부에 HDP 산화막을 갭필산화막(60)으로 이용하여 트렌치(40)를 매립하였다.As shown in FIG. 1B, the sacrificial oxide film 50 may be oxidized and grown on the inner wall surface of the trench 40 to prevent leakage current due to concentration of field effects in the portion where the trench 40 is formed. After forming the trench, the trench 40 was buried in the trench 40 using the HDP oxide film as the gap fill oxide film 60.
그 후, 도 1c에 도시된 바와 같이, 상기 결과물을 패드질화막(30)까지 화학기계적 연마공정을 진행하여 평탄화한 후, 인산용액으로 습식식각하여 패드질화막(30)을 제거함으로써 소자분리막(70)이 형성되었다.After that, as shown in FIG. 1C, the resultant is flattened by performing a chemical mechanical polishing process to the pad nitride layer 30, and then wet-etched with a phosphate solution to remove the pad nitride layer 30. Was formed.
그러나, 상기와 같은 종래 기술을 이용하게 되면, 트렌치 형성 시, 건식식각 공정에 의해 트렌치를 형성하기 때문에 실리콘기판 측벽 식각에 의한 손상을 입게되는 문제점이 있었다.However, when using the prior art as described above, since the trench is formed by a dry etching process during the trench formation, there is a problem that the silicon substrate sidewall etching is damaged.
또한, 상기와 같은 문제점을 해결하기 위해 트렌치의 내벽면을 산화 성장시켜 희생산화막을 형성하며, 이때, 희생산화막을 형성하기 전보다는 트렌치 양끝이 라운딩되나 라운딩 효과가 크지 않아서 라운딩처리로 인해 예상되는 효과에 비해 나타나는 효과가 미약하여 소자구동시 소자분리막 모서리 부분에 전기적 집중현상(fringing field)이 유발되어서 소자의 전기적 열화가 발생될 뿐만 아니라 험프(hump)로 인한 문전접압의 변화 현상이 발생되는 문제점이 있었다.In addition, in order to solve the above problems, the inner wall surface of the trench is oxidized and grown to form a sacrificial oxide film. At this time, both ends of the trench are rounded, but the rounding effect is not large, rather than before the sacrificial oxide film is formed. Compared to the weaker effect of the device, the electrical field of the device is induced at the corners of the device isolation layer, causing electrical deterioration of the device, as well as a change in the gate contact voltage due to the hump. there was.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 STI 공정을 이용한 소자분리막 형성 공정에 있어서, 트렌치가 형성된 실리콘기판에 케미컬 식각 특성에 의해 실리콘기판을 등방성으로 오버 식각하여 트렌치 상부 모서리 영역에 기울기 60~70°의 슬로프진 실리콘기판 표면을 형성한 다음, 아르곤 가스를 스퍼터링 함으로써, 트렌치 상부 모서리의 라운딩 특성을 향상시키며 모우트 발생을 방지하도록 하는 반도체소자의 소자분리막 제조방법을 제공하는 것이다.The present invention has been made to solve the above problems, an object of the present invention in the device isolation film forming process using the STI process, by isotropically over-etching the silicon substrate by the chemical etching characteristics on the silicon substrate formed trench Method of manufacturing a device isolation film of a semiconductor device to form a silicon substrate surface with a slope of 60 ~ 70 ° in the upper corner region of the trench, and then sputtering argon gas to improve the rounding characteristics of the upper corner of the trench and prevent the occurrence of moat To provide.
도 1a 내지 도 1c는 종래 반도체소자의 소자분리막 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of manufacturing a device isolation film of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체소자의 소자분리막을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.2A through 2C are cross-sectional views sequentially illustrating the device isolation film of the semiconductor device according to the embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 실리콘기판 110 : 패드산화막100: silicon substrate 110: pad oxide film
120 : 감광막 패턴 130 : 트렌치120: photoresist pattern 130: trench
140 : 아르곤 스퍼터링140: Argon Sputtering
상기 목적을 달성하기 위하여, 본 발명은 소자분리막 제조 공정에 있어서, 패드산화막이 증착된 실리콘기판 상에 소자분리영역을 정의하는 감광막 패턴을 형성하고 이를 식각마스크로 식각공정을 진행하여 트렌치를 형성하는 단계와, 상기트렌치가 형성된 실리콘 기판을 감광막 패턴을 식각마스크로 등방성 식각공정을 진행하여 트렌치 상부 모서리 영역에 슬로프진 실리콘기판 표면을 형성하는 단계와, 상기 감광막 패턴을 제거한 다음 결과물 전체에 아르곤 스퍼터링을 진행하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 소자분리막 제조방법을 제공한다.In order to achieve the above object, the present invention, in the device isolation film manufacturing process, forming a photoresist pattern defining the device isolation region on the silicon substrate on which the pad oxide film is deposited and proceeds the etching process with an etching mask to form a trench And isotropic etching the silicon substrate on which the trench is formed by using a photoresist pattern as an etch mask to form a surface of the silicon substrate in the upper corner region of the trench, removing the photoresist pattern, and then argon sputtering over the entire product. It provides a device isolation film manufacturing method of a semiconductor device, characterized in that it comprises a step of proceeding.
상기 본 발명에 의한 소자분리막 제조방법에 있어서, 상기 슬로프진 실리콘기판의 슬로프는 등방성 식각에 의해 약 60 ~ 70°의 기울기를 갖도록 하는 것이 바람직하다.In the device isolation film manufacturing method according to the present invention, it is preferable that the slope of the sloped silicon substrate to have a slope of about 60 ~ 70 ° by isotropic etching.
즉, 상기 본 발병에 의한 소자분리막 형성방법에 의하면, 상기 트렌치가 형성된 실리콘기판의 트렌치 상부 모서리면을 등방성 식각에 의해 스퍼터링 수율이 높은 60 ~ 70°기울기로 슬로프지게 형성한 다음, 슬로프진 실리콘표면에 아르곤 스퍼터링을 가함으로써, 최종 형성된 트렌치의 프로파일의 트렌치 상부 모서리의 라운딩을 최대화하도록 하는 것이다.That is, according to the method of forming the isolation layer according to the present invention, the trench upper edge surface of the silicon substrate on which the trench is formed is formed to be sloped with a 60 to 70 ° slope having a high sputtering yield by isotropic etching, and then the sloped silicon surface Applying argon sputtering to maximizes the rounding of the trench upper edge of the profile of the finally formed trench.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체소자의 소자분리막을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.2A through 2C are cross-sectional views sequentially illustrating the device isolation film of the semiconductor device according to the embodiment of the present invention.
우선, 도 2a에 도시된 바에 있어서, 패드산화막이 증착된 실리콘기판(100) 상에 감광막을 도포한 다음, 노광 및 현상공정을 진행하여 소자분리영역이 정의되도록 감광막을 패터닝한다. 그리고, 상기 패터닝된 감광막을 식각마스크로 이용하여 패드산화막과 실리콘기판을 순차적으로 건식식각하여 실리콘기판 내에 트렌치를 형성한다. 이때, 상기 트렌치(140)는 실리콘기판(100) 표면으로부터 약 3500Å의 깊이로 식각하여 형성한다.First, as shown in FIG. 2A, the photoresist film is coated on the silicon substrate 100 on which the pad oxide film is deposited, and then the photoresist film is patterned to define an isolation region by performing exposure and development processes. The pad oxide film and the silicon substrate are sequentially dry-etched using the patterned photoresist as an etching mask to form trenches in the silicon substrate. At this time, the trench 140 is formed by etching to a depth of about 3500Å from the surface of the silicon substrate 100.
이어서, 도 2b에 도시된 바와 같이, 상기 트렌치가 형성된 실리콘기판 상부의 감광막을 식각마스크로 케미컬 식각 특성을 이용하여 실리콘기판을 등방성으로 오버 식각하여 트렌치 상부 모서리 영역에 기울기 60~70°의 슬로프진 실리콘기판 표면을 형성한다. 즉, 이는 케미컬 식각 특성으로 클로린(Cl2)이 주로 포함된 식각가스에 첨가되는 질소가스(N2)의 비율을 조절하여 발생되는 폴리머의 양을 조절하여 트렌치 상부 모서리 영역에 기울기 60~70°의 슬로프진 실리콘기판 표면을 형성한다. 이때, 상기 60 ~70°로 슬로프진 실리콘기판 표면은 한 개의 이온이 식각될 물질에 입사될 경우 스퍼터링에 의해서 튀어나오는 타겟(Target) 물질의 비율 즉, 스퍼터링 수율이 높다.Subsequently, as shown in FIG. 2B, an isotropic over-etch of the silicon substrate is performed using the chemical etching characteristic of the photoresist film on the silicon substrate on which the trench is formed as an etch mask to incline a slope of 60 to 70 ° in the upper corner region of the trench. The silicon substrate surface is formed. In other words, this is a chemical etching characteristic of the slope of 60 to 70 ° slope in the upper corner region of the trench by adjusting the amount of polymer generated by adjusting the ratio of nitrogen gas (N2) added to the etching gas mainly containing chlorine (Cl2) The true silicon substrate surface is formed. At this time, the surface of the silicon substrate sloped at 60 to 70 ° has a high ratio of the target material, that is, the sputtering yield that is caused by sputtering when one ion is incident on the material to be etched.
그리고, 도 2c에 도시된 바와 같이, 상기 패터닝된 감광막(미도시함)을 제거한 다음, 아르곤(Ar) 가스를 이용하여 결과물 전체에 스퍼터링을 진행한다. 이때, 상기 결과물의 표면 중 트렌치 상부 모서리 영역의 실리콘기판 표면이 스퍼터링 수율이 높은 60 ~70°의 기울기로 형성되어 있어 트렌치 상부 모서리 영역의 실리콘기판 표면을 쉽게 라운딩시킨다.As shown in FIG. 2C, the patterned photoresist (not shown) is removed, and then sputtering is performed on the entire product using argon (Ar) gas. At this time, the silicon substrate surface of the trench upper corner region of the resultant surface is formed with a slope of 60 ~ 70 ° with a high sputtering yield to easily round the silicon substrate surface of the trench upper corner region.
그 후, 결과물 전체에 갭필산화막(160)을 증착하여 트렌치를 매립함으로써, 소자분리막을 형성한다.Thereafter, the gap fill oxide film 160 is deposited on the entire resultant to fill the trench, thereby forming a device isolation film.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 소자분리막 제조방법을 이용하게 되면, STI 공정을 이용한 소자분리막 형성 공정에 있어서, 트렌치가 형성된 실리콘기판에 케미컬 식각 특성을 이용하여 실리콘기판을 오버 식각하여 트렌치 상부 모서리 영역에 기울기 60~70°의 슬로프진 실리콘기판 표면을 형성한 다음, 아르곤 가스를 스퍼터링 함으로써, 트렌치 상부 모서리의 라운딩 특성이 향상될 수 있으며, 모우트의 발생을 방지할 수 있게 된다.Therefore, as described above, when the device isolation film manufacturing method of the semiconductor device according to the present invention is used, in the device isolation film forming process using the STI process, the silicon substrate is overlaid by using the chemical etching property on the silicon substrate having the trench formed therein. By etching to form a sloped silicon substrate surface having a slope of 60 to 70 ° in the upper corner region of the trench, and then sputtering argon gas, the rounding property of the upper corner of the trench can be improved, and the occurrence of moat can be prevented. do.
그 결과, 소자분리막 모서리에 험프(hump) 및 전계집중현상 등이 발생되는 것을 방지되어 반도체 소자의 특성, 신뢰성을 개선시키고 그에 따른 반도체 소자의 수율을 향상시키는 효과가 있다.As a result, the hump and the field concentration phenomenon are prevented from occurring at the edge of the device isolation layer, thereby improving the characteristics and reliability of the semiconductor device and thereby improving the yield of the semiconductor device.
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