KR20040008649A - Method of forming gate for semiconductor device - Google Patents
Method of forming gate for semiconductor device Download PDFInfo
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- KR20040008649A KR20040008649A KR1020020042317A KR20020042317A KR20040008649A KR 20040008649 A KR20040008649 A KR 20040008649A KR 1020020042317 A KR1020020042317 A KR 1020020042317A KR 20020042317 A KR20020042317 A KR 20020042317A KR 20040008649 A KR20040008649 A KR 20040008649A
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- film
- gate
- wsi
- layer
- polysilicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 239000010937 tungsten Substances 0.000 claims abstract description 27
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 27
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 26
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 36
- 230000002093 peripheral effect Effects 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 13
- 239000010408 film Substances 0.000 description 105
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 마이크로로딩효과(micro-loading effect)에 의한 영향을 최소화할 수 있는 반도체 소자의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device capable of minimizing an effect caused by a micro-loading effect.
반도체 소자의 고집적화에 따른 동작속도를 확보하기 위하여, 게이트 물질인 폴리실리콘막 상부에 텅스텐실리사이드(WSix)막을 적층한 폴리사이드 구조나 폴리실리콘(Polysilicon; Poly)막 상부에 텅스텐(W)막이 적층된 텅스텐/폴리실리콘 구조로 게이트를 형성하고 있다.In order to secure the operation speed according to the high integration of the semiconductor device, a tungsten silicide (WSix) film is laminated on the polysilicon film as a gate material, or a tungsten (W) film is stacked on the polysilicon (Polysilicon) poly film. The gate is formed with a tungsten / polysilicon structure.
이중 폴리사이드 구조는 117㎚ 및 130㎚의 100㎚ 이상의 고집적 반도체 소자의 제조시 적용하고, 텅스텐/폴리실리콘 구조는 폴리사이드 구조보다 고온에서의 열안정성이 우수하고 비저항이 더 낮기 때문에 100㎚ 이하의 고집적 반도체 소자의 제조시 적용하고 있다.The double polyside structure is applied in the fabrication of high-density semiconductor devices of 100 nm or more of 117 nm and 130 nm, and the tungsten / polysilicon structure is less than 100 nm because of better thermal stability and lower resistivity at high temperature than the polyside structure. It is applied in the manufacture of highly integrated semiconductor devices.
도 1a 및 도 1b는 이러한 폴리사이드 구조나 텅스텐/폴리실리콘 구조를 적용한 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a gate forming method of a semiconductor device to which the polyside structure or the tungsten / polysilicon structure is applied.
도 1a를 참조하면, 셀영역(C1) 및 주변영역(P1)이 정의된 반도체 기판(10) 상에 게이트 절연막(11)을 형성하고, 게이트 절연막(11) 상에 게이트용 하부물질막으로서 폴리실리콘막(12)을 형성한 후, 폴리실리콘막(12) 상에 게이트용 상부물질막(13)을 형성한다. 바람직하게, 상부물질막(13)은 텅스텐막이나 텅스텐실리사이드막으로 형성한다. 그 다음, 상부물질막(13) 상에 포토리소그라피 및 식각공정으로 절연막의 하드 마스크(14A, 14B)를 형성한다. 이때, 주변영역(P1) 상의 하드 마스크(14B)가 셀영역(C1)의 하드 마스크(14A) 보다 큰 선폭으로 형성되며, 이러한 셀영역(C1)에 비해 상대적으로 넓은 주변영역(P1)의 패턴 간격으로 인하여, 하드마스크(14A, 14B) 형성을 위한 식각시 식각속도차이에 의해 마이크로로딩 효과가 발생하여 주변영역(P1)의 상부물질막(13)이 소정 두께("A") 만큼 식각된다.Referring to FIG. 1A, a gate insulating layer 11 is formed on a semiconductor substrate 10 in which a cell region C1 and a peripheral region P1 are defined, and a poly-layer material as a gate lower material layer is formed on the gate insulating layer 11. After the silicon film 12 is formed, the gate upper material film 13 is formed on the polysilicon film 12. Preferably, the upper material film 13 is formed of a tungsten film or a tungsten silicide film. Next, the hard masks 14A and 14B of the insulating layer are formed on the upper material layer 13 by photolithography and etching processes. In this case, the hard mask 14B on the peripheral area P1 is formed to have a larger line width than the hard mask 14A of the cell area C1, and the pattern of the peripheral area P1 that is relatively wider than the cell area C1 is formed. Due to the spacing, the microloading effect occurs due to the difference in etching speed during etching for forming the hard masks 14A and 14B, so that the upper material film 13 of the peripheral region P1 is etched by a predetermined thickness ("A"). .
이에 따라, 하드 마스크(14A, 14B)를 식각마스크로하여 하부의 상부물질막 (13)을 식각하게 되면, 도 1b에 도시된 바와 같이, 이때에도 마이크로로딩 효과에 의해 셀영역(P1)에서는 상부물질막(13)과 일부 폴리실리콘막(12)만이 식각되는 반면, 주변영역(P1)에서는 상부물질막(13) 뿐만 아니라 하부의 폴리실리콘막(12)도 거의 식각된다.Accordingly, when the lower upper material layer 13 is etched using the hard masks 14A and 14B as an etch mask, as shown in FIG. 1B, the upper portion of the cell region P1 may be formed due to the microloading effect. Only the material layer 13 and some of the polysilicon layers 12 are etched, whereas in the peripheral region P1, not only the upper material layer 13 but also the lower polysilicon layer 12 is almost etched.
이에 따라, 도시되지는 않았지만, 셀영역(C1) 및 주변영역(P1)의 폴리실리콘막(12)을 완전히 식각하기 위하여 추가식각을 수행하게 되면, 주변영역(P1)에서 기판 손상 등이 유발되어 누설전류를 야기시키게 된다. 한편, 이러한 주변영역(P1)의 기판손상을 방지하기 위하여 추가식각 시간을 감소시키게 되면, 셀영역(C1)의 폴리실리콘막(12)이 완전히 제거되지 않고 남게 되고, 이러한 현상은 특히 활성영역과 비활성영역의 경계지역인 모트(moat) 영역에서 더 크게 발생하여 소자의 동작에 치명적인 결과를 가져오게 된다.Accordingly, although not shown, additional etching may be performed to completely etch the polysilicon layer 12 of the cell region C1 and the peripheral region P1, resulting in damage to the substrate in the peripheral region P1. It causes leakage current. On the other hand, if the additional etching time is reduced in order to prevent damage to the substrate of the peripheral region P1, the polysilicon film 12 of the cell region C1 remains without being completely removed. It occurs larger in the moat region, which is the boundary of the inactive region, resulting in fatal operation of the device.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 마이크로로딩효과에 의한 영향을 최소화하여 기판의 손상 및 모트 영역에서의 폴리실리콘막 잔류 등의 현상을 방지할 수 있는 반도체 소자의 게이트 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, by minimizing the effect of the microloading effect of the semiconductor device that can prevent the phenomenon such as damage to the substrate and the polysilicon film remaining in the mote region Its purpose is to provide a gate forming method.
도 1a 및 도 1b는 종래의 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a gate forming method of a conventional semiconductor device.
도 2a 및 도 2b는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도.2A and 2B are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
20 : 반도체 기판 21 : 게이트 절연막20 semiconductor substrate 21 gate insulating film
22 : 폴리실리콘막 23 : 게이트용 상부물질막22 polysilicon film 23 upper gate material film
24A, 24B : 하드마스크 100 : 게이트24A, 24B: Hardmask 100: Gate
C2 : 셀영역 P2 : 주변영역C2: Cell Area P2: Peripheral Area
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 본 발명의 목적은 반도체 기판 상에 게이트 절연막을 형성하는 단계; 게이트 절연막 상에 게이트용 하부물질막으로서 폴리실리콘막을 형성하는 단계; 폴리실리콘막 상에 게이트용 상부물질막을 형성하는 단계; 및 상부물질막 및 폴리실리콘막을 순차적으로 식각하여 게이트를 형성하는 단계를 포함하고, 게이트용 상부물질막은 텅스텐막과 텅스텐실리사이드막의 적층막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is to form a gate insulating film on a semiconductor substrate; Forming a polysilicon film on the gate insulating film as a lower material film for the gate; Forming a gate upper material film on the polysilicon film; And forming a gate by sequentially etching the upper material film and the polysilicon film, wherein the upper material film for the gate is formed by a laminated film of a tungsten film and a tungsten silicide film. Can be.
바람직하게, 상부물질막은 WSi/W막, WSi/W/WSi막, W/WSi/W막, WiSi/W/WSi/W막, WSi/W/WSi/W/WSi막, 및 W/WSi/W/WSi/W막 중 선택되는 하나의 막으로 형성한다.Preferably, the upper material film is a WSi / W film, WSi / W / WSi film, W / WSi / W film, WiSi / W / WSi / W film, WSi / W / WSi / W / WSi film, and W / WSi / It is formed of one film selected from among W / WSi / W films.
또한, 상부물질막의 텅스텐실리사이드막은 주요 식각개스로서 Cl2/O2를 이용하여 식각하고, 텅스텐막은 식각개스로서 F를 기본으로 하는 개스, 바람직하게 CF4, NF3또는 SF6개스를 이용하는 식각하고, 폴리실리콘막은 식각개스로서 HBr/O2, Cl2/O2, 또는 HBr/Cl2/O2를 이용하여 식각한다.In addition, the tungsten silicide film of the upper material film is etched using Cl 2 / O 2 as the main etching gas, the tungsten film is etched using F-based gas, preferably CF 4 , NF 3 or SF 6 gas as the etching gas. , Polysilicon film is etched using HBr / O 2 , Cl 2 / O 2 , or HBr / Cl 2 / O 2 as an etching gas.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 2a 및 도 2b는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.2A and 2B are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 2a를 참조하면, 셀영역(C2) 및 주변영역(P2)이 정의된 반도체 기판(10) 상에 게이트 절연막(21)을 형성하고, 게이트 절연막(21) 상에 게이트용 하부물질막으로서 폴리실리콘막(22)을 형성한다. 그 다음, 폴리실리콘막(22) 상에 게이트용 상부물질막(23)을 형성한다.Referring to FIG. 2A, a gate insulating film 21 is formed on a semiconductor substrate 10 in which a cell region C2 and a peripheral region P2 are defined, and a poly material as a lower material film for a gate is formed on the gate insulating film 21. The silicon film 22 is formed. Next, the gate upper material film 23 is formed on the polysilicon film 22.
여기서, 상부물질막(23)은 텅스텐(W)막과 텅스텐실리사이드(WSi)막의 적층막으로 형성하여 이들의 식각선택비를 이용함으로써, 이후 식각시 마이크로로딩 효과를 최소화한다. 바람직하게, 상부물질막(23)은 텅스텐(W)막 상부에 박막의 텅스텐실리사이드(WSi)막을 적층한 WSi/W막, 제 1 텅스텐실리사이드막 상부에 박막의 제 1 텅스텐막과 제 2 텅스텐실리사이드막이 적층된 WSi/W/WSi막, 제 1 텅스텐막 상부에 박막의 제 1 텅스텐실리사이드막 및 제 2 텅스텐막을 순차적으로 적층한 W/WSi/W막, 제 1 텅스텐막 상부에 박막의 텅스텐실리사이드막, 제 2 텅스텐막 및 제 2 텅스텐실리사이드막을 순차적으로 적층한 WiSi/W/WSi/W막, 제 1 텅스텐실리사이드막 상부에 박막의 제 1 텅스텐막, 제 2 텅스텐실리사이드막, 제 2 텅스텐막 및 제 3 텅스텐실리사이드막을 순차적으로 적층한 WSi/W/WSi/W/WSi막, 및 제 1 텅스텐막 상부에 박막의 제 1 텅스텐실리사이드막, 제 2 텅스텐막, 제 2 텅스텐실리사이드막 및 제 3 텅스텐막을 순차적으로 적층한 W/WSi/W/WSi/W막 중 선택되는 하나의 막으로 형성한다.Here, the upper material layer 23 is formed of a laminated film of a tungsten (W) film and a tungsten silicide (WSi) film to use their etching selectivity, thereby minimizing the microloading effect during etching. Preferably, the upper material film 23 is a WSi / W film in which a thin tungsten silicide (WSi) film is laminated on a tungsten (W) film, and the first tungsten film and the second tungsten silicide of a thin film on the first tungsten silicide film. WSi / W / WSi film in which the film is laminated, W / WSi / W film in which the first tungsten silicide film and the second tungsten film are sequentially stacked on the first tungsten film, and the tungsten silicide film of the thin film on the first tungsten film , A WiSi / W / WSi / W film in which a second tungsten film and a second tungsten silicide film are sequentially stacked; a first tungsten film, a second tungsten silicide film, a second tungsten film and a first thin film on the first tungsten silicide film A WSi / W / WSi / W / WSi film in which three tungsten silicide films are sequentially stacked, and a first tungsten silicide film, a second tungsten film, a second tungsten silicide film, and a third tungsten film on the first tungsten film W / WSi / W / WSi / W Film It is formed into one film which is chosen.
또한, 상부물질막(23)은 텅스텐실리사이드막 대신 텅스텐나이트라이드(WN)막을 적용하여 텅스텐막과 텅스텐나이트라이드막의 적층막으로도 형성할 수 있고, 별도의 텅스텐나이트라이드막을 추가하여 텅스텐막, 텅스텐나이트라이드막 및 텅스텐실리사이드막의 적층막으로도 형성할 수 있다. 바람직하게는, 상부물질막(23)을 WN/W막, WN/WSi/W막, WSi/WN/W막, WSi/W/WN/W막, 및 WSi/WN/WSi/W막 중 선택되는 하나의 막으로도 형성할 수 있다.In addition, the upper material film 23 may be formed as a laminated film of a tungsten film and a tungsten nitride film by applying a tungsten nitride (WN) film instead of a tungsten silicide film. It can also be formed from a laminated film of a nitride film and a tungsten silicide film. Preferably, the upper material film 23 is selected from among WN / W film, WN / WSi / W film, WSi / WN / W film, WSi / W / WN / W film, and WSi / WN / WSi / W film. It can also be formed from a single film.
그 다음, 상부물질막(23) 상에 포토리소그라피 및 식각공정으로 절연막의 하드 마스크(24A, 24B)를 형성한다. 여기서, 주변영역(P2) 상의 하드 마스크(24B)가 셀영역(C2)의 하드 마스크(24A) 보다 큰 선폭으로 형성되는데, 이때 상부물질막(23)의 텅스텐과 텅스텐실리사이드의 식각선택비에 의해 마이크로로딩 효과가 최소화되어 셀영역(C2)과 주변영역(P2)에서 균일하게 식각이 이루진다.Next, the hard masks 24A and 24B of the insulating layer are formed on the upper material layer 23 by photolithography and etching processes. Here, the hard mask 24B on the peripheral region P2 is formed to have a line width larger than that of the hard mask 24A of the cell region C2, wherein the etching selectivity of tungsten and tungsten silicide of the upper material layer 23 is increased. Since the micro loading effect is minimized, etching is uniformly performed in the cell region C2 and the peripheral region P2.
도 2b를 참조하면, 하드(24A, 24B)를 식각마스크로하여 하부의 상부물질막(23)을 식각한다. 이때에도 상기와 마찬가지로 상부물질막(23)의 텅스텐과 텅스텐실리사이드의 식각선택비에 의해 마이크로로딩 효과가 최소화되어 셀영역(C2)과 주변영역(P2)에서 균일하게 식각이 이루어진다. 여기서, 상부물질막(23)의 식각시 텅스텐실리사이드막은 주요 식각개스로서 Cl2/O2를 이용하여 식각을 수행하고, 텅스텐막은 식각개스로서 F를 기본으로 하는 개스, 바람직하게 CF4, NF3또는 SF6개스를 이용하여 식각을 수행한다. 그 후, 추가식각으로 폴리실리콘막 (22)을 식각하여 게이트(100)를 형성한다. 여기서, 폴리실리콘막(22)의 식각은 식각개스로서 HBr/O2, Cl2/O2, 또는 HBr/Cl2/O2를 이용하여 수행함으로써, 게이트 프로파일 특성을 개선함과 동시에 모트 등에 잔류하는 폴리실리콘막(22)의 잔막 등을 효과적으로 제거한다.Referring to FIG. 2B, the upper upper material layer 23 is etched using the hard 24A and 24B as an etching mask. In this case, as described above, the microloading effect is minimized by the etching selectivity of the tungsten and tungsten silicide of the upper material layer 23, so that etching is uniformly performed in the cell region C2 and the peripheral region P2. Here, when etching the upper material film 23, the tungsten silicide film is etched using Cl 2 / O 2 as the main etching gas, the tungsten film is a gas based on F as the etching gas, preferably CF 4 , NF 3 Alternatively, etching is performed using SF 6 gas. Thereafter, the polysilicon film 22 is etched by additional etching to form the gate 100. Here, the etching of the polysilicon film 22 is performed by using HBr / O 2 , Cl 2 / O 2 , or HBr / Cl 2 / O 2 as an etching gas, thereby improving the gate profile characteristics and remaining in the mort or the like. The remaining film or the like of the polysilicon film 22 can be effectively removed.
상기 실시예에 의하면, 폴리실리콘막 상부에 게이트용 상부물질막을 식각선택비를 갖는 텅스텐막과 텅스텐실리사이드막의 적층막으로 형성함으로써 후속 식각공정시 마이크로로딩 효과를 최소화할 수 있다.According to the above embodiment, the microloading effect may be minimized during the subsequent etching process by forming the gate upper material layer on the polysilicon layer as a laminated film of tungsten film and tungsten silicide film having an etching selectivity.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 게이트 형성시 마이크로로딩효과에 의한 영향을 최소화하여 셀영역과 주변영역의 식각균일도를 향상시킴으로써, 주변영역의 기판 손상 및 셀영역의 폴리실리콘 잔류 등을 방지할 수 있으므로, 결국 소자의 전기적 특성을 향상시킬 수 있다.As described above, the present invention minimizes the effect of the microloading effect on the gate formation to improve the etching uniformity of the cell region and the peripheral region, thereby preventing damage to the substrate and polysilicon remaining in the cell region. It can improve the electrical characteristics.
Claims (6)
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