KR20040007873A - Method of planarlazing semiconductor device - Google Patents
Method of planarlazing semiconductor device Download PDFInfo
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- KR20040007873A KR20040007873A KR1020020040473A KR20020040473A KR20040007873A KR 20040007873 A KR20040007873 A KR 20040007873A KR 1020020040473 A KR1020020040473 A KR 1020020040473A KR 20020040473 A KR20020040473 A KR 20020040473A KR 20040007873 A KR20040007873 A KR 20040007873A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000005498 polishing Methods 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 평탄화 방법에 관한 것으로, CMP 공정의 마진을 확보하기 위하여 버퍼막을 도입하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and more particularly, to a method of introducing a buffer film to secure a margin of a CMP process.
최근, 대부분의 대용량 고집적 반도체 소자의 제작에 있어서 초미세 공정, 예를 들어 0.13 ㎛ 이하의 공정을 도입하여 양산단계에 접어들고 있는 실정이다. 이 경우, CMP(Chemical Mechanical Polishing)공정을 이용한 평탄화를 통한 소자분리막 형성 공정을 도입하면서, 기판 전체를 균일하게 분리시키는 것이 어려운 문제점이 있다.Recently, in the manufacture of most large-capacity, high-density semiconductor devices, an ultra-fine process, for example, 0.13 μm or less, has been introduced to mass production. In this case, it is difficult to uniformly separate the entire substrate while introducing a device isolation film forming process through planarization using a chemical mechanical polishing (CMP) process.
특히, CMP 공정중 하부막에 폴리실리콘과 옥사이드계열의 절연층이 형성되어 있는 경우, 제거되는 비율의 차이와 단차문제로 인하여 잔류하는 폴리실리콘의 양이 부위별로 달라질 수 있어 후속되는 모니터링 공정에서 어려움이 있었다.In particular, when the polysilicon and the oxide-based insulating layer is formed on the lower layer during the CMP process, the amount of remaining polysilicon may vary from site to site due to the difference in the removal rate and the step difference, which is difficult in the subsequent monitoring process. There was this.
상술한 바와 같은 문제점을 해결하기 위하여, 본 발명의 목적은 CMP 공정시 연마대상막의 상부에 버퍼막을 형성하여 기형성된 단차를 높은 영역부터 큰 연마율을 가지고 연마될 수 있게 하여 단차문제를 해결하여 반도체 소자의 신뢰성을 향상시키는 것이다.In order to solve the above problems, an object of the present invention is to form a buffer layer on top of the film to be polished during the CMP process so that the formed step can be polished with a high polishing rate from a high region to solve the step problem. It is to improve the reliability of the device.
도 1a 내지 도 1g는 본 발명의 바람직한 실시예에 따른 반도체 소자의 평탄화 방법을 도시한 도면들이다.1A to 1G illustrate a planarization method of a semiconductor device according to an exemplary embodiment of the present invention.
*도면의 주요부분에 대한 간단한* Brief about the main parts of the drawing
10 : 반도체 기판 12 : 패드산화막10 semiconductor substrate 12 pad oxide film
14 : 패드 질화막 16 : HDP 산화막14 pad nitride film 16 HDP oxide film
18: 폴리실리콘막 20 : 버퍼막18: polysilicon film 20: buffer film
상술한 목적을 해결하기 위하여, 본 발명은 반도체 구조물상의 소정 부위에 볼록 형상으로 돌출된 실리콘 산화막층을 형성하는 단계, 실리콘 산화막층을 포함하는 전체 구조상에 연마 대상층을 형성하는 단계, 연마 대상층 상부에 절연층의 연마 버퍼층을 형성하는 단계 및 CMP 공정을 실시하는 단계를 포함하는 반도체 소자의 평탄화 방법을 제공한다.In order to solve the above object, the present invention is to form a silicon oxide film layer protruding convexly in a predetermined portion on the semiconductor structure, forming a polishing target layer on the entire structure including the silicon oxide film layer, on the polishing target layer It provides a method of planarizing a semiconductor device comprising the step of forming a polishing buffer layer of the insulating layer and performing a CMP process.
바람직하게는, 연마 버퍼층은 150 내지 500 Å 두께의 실리콘 질화막, 300 내지 500 ℃ 온도에서 500 내지 1000 Å로 형성된 HDP 실리콘 산화막, 200 내지500 Å 두께의 LPCVD 산화막 또는 보론 도펀트는 3.2 내지 4.3wt%, 인도펀트는 3.5 내지 4.6wt%인 BPSG막이다.Preferably, the polishing buffer layer is a silicon nitride film having a thickness of 150 to 500 kPa, an HDP silicon oxide film formed at 500 to 1000 kPa at a temperature of 300 to 500 ° C., an LPCVD oxide film or a boron dopant having a thickness of 200 to 500 kPa, 3.2 to 4.3 wt%, The indopant is a BPSG film with 3.5 to 4.6 wt%.
이하, 본 발명의 일실시예에 따른 반도체 소자의 평탄화 방법을 도 1a 내지 도 1g를 참조하여 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전 하도록 하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, a planarization method of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1G. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments are to make the disclosure of the present invention complete and to those skilled in the art the scope of the invention It is provided for complete information.
도 1a 내지 도 1g는 본 발명의 바람직한 실시예에 따른 반도체 소자의 평탄화 방법을 설명하기 위하여 도시한 단면도들이다.1A to 1G are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(10)에 대하여 전처리 세정공정(예를 들어, DHF(Diluted HF; 50:1의 비율로 H20로 희석된 HF용액)로 세정한 후 SC-1(NH4OH/H2O2/H2O 용액이 소정 비율로 혼합된 용액)로 세정하거나, BOE(Buffer Oxide Etchant; 100:1 또는 300:1의 비율로 H2O로 희석된 HF와 NH4F의 혼합용액[1:4 내지 1:7])로 세정한 후 SC-1로 세정)을 한 후, 패드산화막(12)과 패드 질화막(14)을 형성한다. 이때, 패드산화막(12)은 반상부표면의 결정결함 또는 표면처리를 위하여, 예컨대 750 내지 800℃의 온도범위에서 건식 또는 습식산화방식으로 산화공정을 실시하여 약 70 내지 100Å의 두께로 형성할 수 있고, 패드질화막(14)은 후속공정을 통해 형성되는 소자분리막(미도시)의 높이를 최대한 증가시키기 위해 LPCVD방식으로 증착공정을 실시하여 최대한 높게 형성한다. 그러나, 소자의 집적화와 신뢰성을고려하여 예를 들어 900 내지 2000Å의 두께로 형성한다.Referring to FIG. 1A, the semiconductor substrate 10 is cleaned with a pretreatment cleaning process (for example, DHF (Diluted HF; HF solution diluted with H 2 0 at a ratio of 50: 1)) and then SC-1 (NH). HF and NH 4 diluted with 4 OH / H 2 O 2 / H 2 O solution in a predetermined ratio) or BOE (Buffer Oxide Etchant) diluted with H 2 O at a ratio of 100: 1 or 300: 1 And a pad oxide film 12 and a pad nitride film 14 are formed after washing with SC mixed solution [1: 4 to 1: 7]. In this case, the pad oxide film 12 may be formed to have a thickness of about 70 to about 100 kPa by performing an oxidation process by dry or wet oxidation in a temperature range of, for example, 750 to 800 ° C., for crystal defects or surface treatment of the upper surface. In addition, the pad nitride film 14 is formed as high as possible by performing a deposition process by the LPCVD method to increase the height of the device isolation film (not shown) formed through a subsequent process to the maximum. However, in consideration of the integration and reliability of the device, it is formed to a thickness of, for example, 900 to 2000Å.
도 1b를 참조하면, 도 1a의 전체 구조 상부에 포토레지스트 패턴을 형성하고 이를 식각마스크로 이용하여, 패드질화막(14), 패드산화막(12)을 포함한 반도체 기판(10)의 소정 부위를 식각한다. 이 때, 예를 들어 MERI(Magnetically Enhanced Reactive Ion) 타입의 플라즈마 소오스(Plasma source)를 가진 식각장비(Etcher)(이하, 'MERIE'라 함)를 이용한 식각공정을 실시한다.Referring to FIG. 1B, a predetermined portion of the semiconductor substrate 10 including the pad nitride layer 14 and the pad oxide layer 12 is etched by forming a photoresist pattern on the entire structure of FIG. 1A and using the photoresist pattern as an etching mask. . At this time, for example, an etching process using an etching apparatus (hereinafter referred to as 'MERIE') having a plasma source of a magnetically enhanced reactive ion (MERI) type is performed.
다음으로, 도 1c를 참조하면, 상기 전체 구조 상부에 트렌치용 절연막으로 사용가능한 HDP(High Density Plasma) 산화막(16)을 예를 들어 5000 내지 10000 Å의 두께로 형성한다.Next, referring to FIG. 1C, an HDP (High Density Plasma) oxide film 16 that can be used as an insulating film for trenches is formed on the entire structure to have a thickness of, for example, 5000 to 10000 kPa.
다음으로, 패드 질화막(14)을 식각정지층(etch stopper)로 이용하여 연마공정, 예컨대 CMP(Chemical Mechanical Polishing) 공정을 이용하여 패드 질화막(14)의 상부표면이 노출될 때 까지 HDP 산화막(16)을 연마한다(도 1d).Next, using the pad nitride film 14 as an etch stopper, the HDP oxide film 16 is exposed until the upper surface of the pad nitride film 14 is exposed using a polishing process, for example, a chemical mechanical polishing (CMP) process. ) Is polished (FIG. 1D).
다음으로, 패드 질화막(14) 상부 표면에 잔존할 수 있는 HDP 산화막(16)을 제거하기 위하여 HF 또는 BOE를 이용한 전처리 세정공정을 실시한 후, 질화막 계열의 물질과 산화막 계열의 물질 간의 식각비(Etch ratio)를 이용하여 패드 산화막(12)을 식각 정지층으로 하여, 예를 들어 인산(H3PO4) 딥 아웃(Dip out)을 이용한 스트립공정을 통해 패드 질화막(14)을 식각한다(도 1e).Next, after the pretreatment cleaning process using HF or BOE to remove the HDP oxide film 16 that may remain on the upper surface of the pad nitride film 14, the etching ratio between the nitride film material and the oxide film material (Etch) By using the pad oxide film 12 as an etch stop layer, the pad nitride film 14 is etched through a strip process using, for example, phosphoric acid (H 3 PO 4 ) dip out (FIG. 1E). ).
다음으로, 전체 구조 상부에 SiH4또는 Si2H6와 PH3가스를 이용하고, 580 내지 620℃의 온도범위와, 0.1 내지 3Torr의 낮은 압력범위의 조건을 이용한 LP-CVD방식으로 그레인 사이즈(Grain size)가 최소화되도록 1500 내지 2000Å의 두께로 폴리실리콘(Poly-silicon)막을 증착한다. 이후, 폴리실리콘막에 대해 P 농도를 1.5E20 내지 3.0E20 atoms/cc 정도의 도핑 레벨(Doping level)을 부여하여 도프트(Doped) 폴리실리콘막(18)을 형성한다. 그 후, 폴리실리콘막(18) 상에 버퍼막(20)을 형성한다(도 1f).Next, using the SiH 4 or Si 2 H 6 and PH 3 gas on the whole structure, the grain size (LP-CVD method using a temperature range of 580 to 620 ℃, low pressure range of 0.1 to 3 Torr) In order to minimize grain size, a polysilicon film is deposited to a thickness of 1500 to 2000 microns. Thereafter, a doped polysilicon film 18 is formed by giving a doping level of about 1.5E20 to 3.0E20 atoms / cc to the polysilicon film. Thereafter, a buffer film 20 is formed on the polysilicon film 18 (FIG. 1F).
버퍼막(20)으로 형성 가능한 물질은 특별히 한정되지 않고 다양한 절연물질이 가능하며, 예를 들어 150 내지 500 Å 두께의 실리콘 질화막, 300 내지 500 ℃ 온도에서 500 내지 1000 Å 형성된 HDP 실리콘 산화막, 200 내지 500 Å 두께의 LPCVD 산화막 및 보론 도펀트는 3.2 내지 4.3wt%, 인도펀트는 3.5 내지 4.6wt%, 두께는 500 내지 1000 Å의 BPSG막 등이다. BPSG막의 경우, 바람직하게는, 폴리실리콘막(18)의 CMP 이전에 리플로우 특성을 이용하여 RTA 공정으로 열처리하고, 어닐링 온도는 650 내지 800℃ 이다.The material that can be formed as the buffer film 20 is not particularly limited, and various insulating materials are possible. For example, a silicon nitride film having a thickness of 150 to 500 kPa, an HDP silicon oxide film formed at 500 to 1000 kPa at a temperature of 300 to 500 ° C., and 200 to The LPCVD oxide film and boron dopant having a thickness of 500 kV is 3.2 to 4.3 wt%, the BPSG film at 3.5 to 4.6 wt%, and the thickness of 500 to 1000 kPa. In the case of the BPSG film, preferably, the polysilicon film 18 is heat-treated by an RTA process using reflow characteristics before CMP, and the annealing temperature is 650 to 800 ° C.
이와 같은 버퍼막(20)은 폴리실리콘층 CMP 공정을 통한 평탄화시 소자분리막을 형성할 때, 기판 전체에서 불균일하게 CMP되는 문제점을 해결할 수 있는 역할 을 수행한다. 특히, 실리콘 질화막을 이용하여 버퍼막(20)을 형성하는 경우는, 옥사이드 계열의 물질을 이용할 때 발생하는 옥사이드 계열 물질과 폴리실리콘의 선택적인 제거비(removal rate) 차이로 인해 기판의 중심부와 가장자리 사이의 두께 차이를 발생하는 현상을 현저하게 완화시킬 수 있다. 또한, 후단 공정으로 진행될 수 있는 ONO(Oxide/Nitride/Oxide) 식각시 다이별 두께 변화롤 인한 모니터링의 얼려움, 후소고디는 SAE(Self Aligned Etch)시의 폴리실리콘 잔류문제 등을 해결할수 있다.Such a buffer film 20 serves to solve the problem of uneven CMP in the entire substrate when forming the device isolation film during the planarization through the polysilicon layer CMP process. In particular, in the case of forming the buffer layer 20 using the silicon nitride layer, the difference between the center and the edge of the substrate due to the selective removal rate difference between the oxide-based material and polysilicon generated when the oxide-based material is used. The phenomenon causing the difference in thickness of can be remarkably alleviated. In addition, during the ONO (Oxide / Nitride / Oxide) etching process, which may proceed to the post-stage process, the difficulty of monitoring due to the change of thickness by die, Fuso Godi can solve the problem of polysilicon remaining during SAE (Self Aligned Etch). .
특히, 상술한 바와 같이, CMP시 폴리실리콘층과 제거율 차이가 많이 나는 ㅇ버퍼막을 연마대상막 상부에 형성하여 CMP를 실시함으로써, 연마특성상 이미 형성된 단차의 높은 부위부터 큰 연마율을 가지고 연마되기 때문에 단차 문제를 어느정도 해결할 수 있게 된다. 따라서, 이러한 구성을 통해서 웨이퍼간, 다이간 변동폭도 개선할 수 있어 후단 공정에서 신뢰성 높은 공정을 진행할 수 있게 된다.In particular, as described above, by forming a buffer film having a large difference in removal rate from the polysilicon layer at the time of CMP, and performing CMP, since the polishing property is polished with a large polishing rate from a high portion of the step already formed, This will solve the step problem to some extent. Therefore, the variation between the wafers and the dies can be improved through such a configuration, so that a reliable process can be performed in the subsequent step.
다음으로, 트랜치 산화막(16)을 기준으로 하여 폴리실리콘막(18)이 완전히 분리되도록 CMP를 이용한 연마공정을 실시하여 700 내지 1500Å의 두께로 균일한 두께로 플로팅 게이트을 형성한다. 한편, 유전체막 및 컨트롤 게이트 제조방법에 대한 설명은 종래 기술에서 구현되는 방법 모두 적용 가능함에 따라 이하에서는 이에 대한 설명은 생략하기로 한다.Next, a polishing process using CMP is performed to completely separate the polysilicon film 18 based on the trench oxide film 16 to form a floating gate with a uniform thickness of 700 to 1500 mW. In the meantime, the description of the method of manufacturing the dielectric film and the control gate is applicable to all methods implemented in the prior art, and the description thereof will be omitted below.
상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 구성을 통하여, CMP공정시 균일성 문제를 극복할 수 있는 공정개선 효과 및 후속공정에서의 신뢰성 향상등의 효과가 있다.Through the above-described configuration, there are effects such as process improvement that can overcome the uniformity problem in the CMP process and reliability improvement in the subsequent process.
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