KR20040001459A - Method for forming via hole of semiconductor device - Google Patents
Method for forming via hole of semiconductor device Download PDFInfo
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- KR20040001459A KR20040001459A KR1020020036675A KR20020036675A KR20040001459A KR 20040001459 A KR20040001459 A KR 20040001459A KR 1020020036675 A KR1020020036675 A KR 1020020036675A KR 20020036675 A KR20020036675 A KR 20020036675A KR 20040001459 A KR20040001459 A KR 20040001459A
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- via hole
- forming
- stop layer
- etch stop
- layer
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 디바이스의 고집적화에 따른 층간배선과 비아홀사이의 오버레이 마진이 줄어 들어 생기는 보더리스 비아홀(borderless via hole)의 경우에 과도식각의 마진을 확보할 수 있는 하드마스크를 이용한 비아홀 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to secure a margin of excessive etching in a borderless via hole caused by a reduction in overlay margin between interlayer wiring and via holes due to high integration of devices. The present invention relates to a via hole forming method using a hard mask.
디바이스가 고집적화됨에 따라 층간배선과 비아홀사이의 오버레이 마진이 부족하거나 금속배선의 크기가 비아홀의 크기보다 작게 경우에, 도 1에 도시된 바와같이, 보더리스 비아홀(borderless via)이 형성된다.As the device becomes more integrated, borderless via holes are formed as shown in FIG. 1 when the overlay margin between the interlayer wiring and the via holes is insufficient or the size of the metal wiring is smaller than the size of the via holes.
반도체소자의 비아홀 제조공정을 참조하여 설명하면, 먼저 반도체기판(11)상에 절연막(13)을 형성한후 절연막(13)내에 콘택홀을 형성하여 그 내부에 플러그(15)를 형성한다.Referring to the process of manufacturing a via hole of a semiconductor device, first, an insulating film 13 is formed on a semiconductor substrate 11, and then a contact hole is formed in the insulating film 13 to form a plug 15 therein.
그다음, 상기 플러그(15)상에 금속배선(17)을 형성한후 전체 구조의 상면에 층간절연막(19)을 형성하고 이어 추가 절연막(21)을 증착한후 평탄화시킨다.Next, after the metal wiring 17 is formed on the plug 15, an interlayer insulating film 19 is formed on the upper surface of the entire structure, and then an additional insulating film 21 is deposited and planarized.
이어서, 상기 추가절연막(21)과 층간절연막(19)을 순차적으로 제거하여 상기 금속배선(17)을 노출시키는 비아홀(23)을 형성한후 비아홀내에 도전성플러그(25)을 형성하여 상기 금속배선(17)과 접촉되도록한다. 이때, 상기 금속배선(17)의 크기가 비아홀(23)의 크기보다 작은 경우에, 도1의 A와 같이, 보더리스 비아가 형성된다.Subsequently, the additional insulating film 21 and the interlayer insulating film 19 are sequentially removed to form a via hole 23 exposing the metal wiring 17, and then a conductive plug 25 is formed in the via hole to form the metal wiring ( 17). In this case, when the size of the metal wiring 17 is smaller than the size of the via hole 23, as shown in FIG. 1A, borderless vias are formed.
이와 같은 보더리스 비아의 경우, 금속배선과의 접촉면적이 넓어 저항측면에서는 양호해질 수 있으나, 일반적인 비아홀에 비해 상대적으로 과도식각측면에서는 불리할 수 있다. 즉, 종래기술에 따른 도 2에 도시된 B 및 도 3와 같이, 과도식각를 과도하게 할 경우 비아홀(43)이 하부 금속, 또는 기판부근까지 형성될 수가 있다. 여기서, 종래기술에 따른 비아홀 형성공정은 도 1과 동일한 공정순으로 진행되기때문에 여기서는 생략하기로 한다.Such a borderless via may have a large contact area with the metal wiring, which may be favorable in terms of resistance, but may be disadvantageous in terms of transient etching in comparison with general via holes. That is, as shown in B and 3 of FIG. 2 according to the related art, when the excessive etching is excessive, the via hole 43 may be formed up to the lower metal or near the substrate. Here, since the via hole forming process according to the prior art proceeds in the same process order as in FIG. 1, it will be omitted here.
이와 같은 경우, 비아홀(43) 형성시에 발생한 폴리머 등이 홀내부에 잔존할 가능성이 높아지고, 하부 금속배선과 접촉하게 될 경우 쇼트를 유발할 수 있으며, 텅스텐 플러그 공정 진행시에 배리어 금속이나 텅스텐 증착이 원활하게 이루어지지 않아 보이드가 형성되어 디바이스의 신뢰성을 떨어 뜨리게 된다.In such a case, a polymer or the like generated during the formation of the via hole 43 is more likely to remain in the hole, and if it comes into contact with the lower metal wiring, it may cause a short, and the deposition of barrier metal or tungsten during the tungsten plug process may occur. It is not made smoothly, voids are formed, which reduces the reliability of the device.
한편, 이와 같은 현상을 방지하기 위하여 과도식각타겟을 줄일 경우 층간절연물질의 두께가 불균일하여 단선(open failure)이 발생할 가능성이 높아지게 된다.On the other hand, if the excessive etching target is reduced in order to prevent this phenomenon, the thickness of the interlayer insulating material is non-uniform, thereby increasing the possibility of open failure.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 비아홀 형성공정시에 하드마스크로 질화막을 식각정지막으로 이용하여 보더리스 비아에서 발생할 수 있는 테일(tail)을 방지하고 과도식각마진을 확보할 수 있는 하드마스크를 이용한 비아홀 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, by using a nitride film as an etch stop layer as a hard mask during the via hole forming process to prevent the tail (tail) that can occur in the borderless via and transient etching An object of the present invention is to provide a method of forming a via hole using a hard mask that can secure a margin.
도 1은 일반적인 반도체소자의 비아홀 형성방법에 있어서, 정상적인 보더리스 비아 프로파일 (borderless via profile)을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a normal borderless via profile in a method of forming a via hole of a general semiconductor device.
도 2는 종래기술에 따른 반도체소자의 비아홀 형성방법에 있어서, 비정상적인 보더리스 비아 프로파일 (borderless via profile)을 설명하기 위한 단면도.FIG. 2 is a cross-sectional view illustrating an abnormal borderless via profile in a method of forming a via hole of a semiconductor device according to the related art. FIG.
도 3은 종래기술에 따른 반도체소자의 비아홀 형성방법에 있어서, 과도식각 에 따른 비정상적인 보더리스 비아 프로파일을 보여 주는 사진.3 is a photo showing an abnormal borderless via profile due to transient etching in a method of forming a via hole of a semiconductor device according to the related art.
도 4 내지 도 6은 본 발명에 따른 하드마스크를 이용한 비아홀 형성방법을 설명하기 위한 공정단면도.4 to 6 are cross-sectional views illustrating a method of forming a via hole using a hard mask according to the present invention.
[도면부호의설명][Description of Drawing Reference]
51 : 반도체기판53 : 식각정지막51 semiconductor substrate 53 etch stop film
55 : 금속배선57 : 산화막55 metal wiring 57 oxide film
59 : 층간절연막61 : 질화막59 interlayer insulating film 61 nitride film
63 : 감광막패턴65 : 비아홀63: photoresist pattern 65: via hole
67 : 플러그67: plug
상기 목적을 달성하기 위한 본 발명에 따른 하드마스크를 이용한 비아홀 형성방법은, 반도체기판상에 제1식각정지막을 형성하는 단계; 상기 제1식각정지막 상에 금속배선을 형성하는 단계; 상기 금속배선상에 층간절연막을 형성하는 단계; 상기 층간절연막상에 제2식각정지막을 형성하는 단계; 비아홀 형성지역에 해당하는 상기 제2식각정지막의 일부분을 선택적으로 제거하는 단계; 선택적으로 제거된 제2식각정지막아래의 층간절연막을 선택적으로 제거하여 상기 금속배선상면을 노출시키는 비아홀을 형성하는 단계; 및 상기 비아홀내에 플러그를 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.A via hole forming method using a hard mask according to the present invention for achieving the above object comprises the steps of: forming a first etch stop layer on a semiconductor substrate; Forming a metal wire on the first etch stop layer; Forming an interlayer insulating film on the metal wiring; Forming a second etch stop film on the interlayer insulating film; Selectively removing a portion of the second etch stop layer corresponding to the via hole formation region; Selectively removing the interlayer insulating layer under the selectively removed second etch stop layer to form a via hole exposing the upper surface of the metal wiring; And forming a plug in the via hole.
(실시예)(Example)
이하, 본 발명에 따른 하드마스크를 이용한 비아홀 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a via hole using a hard mask according to the present invention will be described in detail with reference to the accompanying drawings.
도 4 내지 도 6은 본 발명에 따른 하드마스크를 이용한 비아홀 형성방법을 설명하기 위한 공정단면도이다.4 through 6 are cross-sectional views illustrating a method of forming a via hole using a hard mask according to the present invention.
본 발명에 따른 하드마스크를 이용한 비아홀 형성방법은, 도 4에 도시된 바와같이, 먼저 반도체기판(51)상에 식각정지막(53)을 증착한후 그 위에 금속배선(55)을 형성한다.In the method of forming a via hole using a hard mask according to the present invention, as shown in FIG. 4, first, an etch stop layer 53 is deposited on a semiconductor substrate 51, and then a metal wiring 55 is formed thereon.
그다음, 상기 금속배선(55)을 포함한 전체 구조의 상면에 SOG 계열 또는 FSG 등의 산화막(57)을 증착한후 연속해서 PE-TEOS 등의 층간절연막(59)을 증착한다음 CMP 또는 전면식각에 의해 평탄화시킨다.Thereafter, an oxide film 57 such as SOG series or FSG is deposited on the upper surface of the entire structure including the metal interconnection 55, and then an interlayer dielectric layer 59 such as PE-TEOS is successively deposited, followed by CMP or full surface etching. By flattening.
이어서, 평탄화된 층간절연막(59)상에 식각중단층으로 이용하기 위해 질화막(61)을 증착한후 그 위에 비아홀을 형성하기 위해 감광물질을 도포하고, 이를 리소그라피공정기술을 이용하여 패터닝하여 감광막패턴(63)을 형성한다. 이때, 상기 질화막(61)은 산화막에 대한 선택비를 갖는 실리콘질화막이나 산화질화막을이용한다.Subsequently, a nitride film 61 is deposited on the planarized interlayer insulating film 59 to be used as an etch stop layer, and then a photosensitive material is coated to form a via hole thereon, and then patterned using a lithography process technique to form a photoresist pattern. (63) is formed. In this case, the nitride film 61 uses a silicon nitride film or an oxynitride film having a selectivity to an oxide film.
그다음, 도 5에 도시된 바와같이, 상기 감광막패턴(63)을 마스크로 비아홀이 형성될 부분의 상기 질화막(61)을 CxFy(x, y는 자연수), CHF3, O2, Ar 등의 가스를 조합하여 건식식각에 의해 식각한다. 이때, 상기 질화막(61) 식각후 비아홀 형성지역의 주위에 남아 있는 질화막은 포토레지스트의 마진을 증가시켜 주는 하드마스크의 역할을 할 수 있다.Next, as shown in FIG. 5, a gas such as CxFy (x, y is a natural number), CHF 3 , O 2 , Ar, or the like is used as the nitride film 61 of the portion where the via hole is to be formed using the photoresist pattern 63 as a mask. Etch by dry etching in combination. In this case, the nitride film remaining around the via hole forming region after etching the nitride film 61 may serve as a hard mask to increase the margin of the photoresist.
이어서, 도 6에 도시된 바와같이, 상기 감광막패턴(63)을 마스크로 상기 층간절연막(59)과 산화막(57)을 순차적으로 식각하여 비아홀(65)을 형성한다. 이때, 상기 금속배선(55)하부에 식각정지막(53)이 존재하므로 과도식각을 과도하게 실시하여도 보더리스 비아홀 지역의 경우 식각정지막(53)에서 식각중단이 일어나므로써 비아홀의 테일(tail)이 발생하지 않게 된다.6, the via hole 65 is formed by sequentially etching the interlayer insulating layer 59 and the oxide layer 57 using the photoresist pattern 63 as a mask. At this time, since the etch stop layer 53 is present under the metal wiring 55, even if excessive etching is excessively performed, in the borderless via hole region, the etch stop occurs at the etch stop layer 53, so that tail of the via hole may occur. ) Does not occur.
계속해서 배리어금속막(미도시)과 텅스텐(미도시)을 증착한 뒤 텅스텐 CMP로 플러그(67)를 형성한다. 이때, 텅스텐 CMP시에 후속 비어홀 공정에서 정지막으로 이용될 비아홀(67) 주위의 질화막(63a)은 제거되지 않도록 한다.Subsequently, a barrier metal film (not shown) and tungsten (not shown) are deposited, and a plug 67 is formed of tungsten CMP. At this time, the nitride film 63a around the via hole 67 to be used as the stop film in the subsequent via hole process at the time of tungsten CMP is not removed.
상기에서 설명한 바와같이, 본 발명에 따른 하드마스크를 이용한 비아홀 형성방법에 의하면, 고집적도를 요구하는 모든 디바이스의 비아홀 형성공정에 적용할 수 있다. 기존의 공정방식과는 달리 층간절연물질위에 질화막을 증착하므로 감광막에 대한 공정마진을 추가로 확보할 수 있다.As described above, according to the via hole forming method using the hard mask according to the present invention, it is applicable to the via hole forming process of all devices requiring high integration. Unlike the conventional process method, since the nitride film is deposited on the interlayer insulating material, the process margin for the photosensitive film can be additionally secured.
또한, 비아홀 형성공정후 비아홀 주위에 남아 있는 질화막은 후속 비아홀 공정의 보더리스 비아홀의 식각중단층으로 작용할 수 있다.In addition, the nitride film remaining around the via hole after the via hole forming process may serve as an etch stop layer of the borderless via hole of the subsequent via hole process.
그리고, 보더리스 비아홀의 과도식각마진을 충분히 확보할 수 있으므로 노출실패(open failure)에 대한 위험을 줄일 수 있으며, 비아홀의 테일이 발생하는 것을 방지하여 폴리머가 테일에 남아 디바이스의 신뢰성을 떨어뜨릴 가능성을 제거할 수 있다.In addition, since the excessive etching margin of the borderless via hole can be secured, the risk of open failure can be reduced, and the tail of the via hole can be prevented from occurring so that the polymer remains in the tail, thereby reducing the reliability of the device. Can be removed.
더욱이, 과도식각마진이 증가함에 따라 보더리스 비아홀과 금속배선과의 접촉면적이 증가하여 저항을 감소시킬 수 있다.Moreover, as the excessive etching margin increases, the contact area between the borderless via hole and the metal wiring increases, thereby reducing the resistance.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (5)
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| KR1020020036675A KR20040001459A (en) | 2002-06-28 | 2002-06-28 | Method for forming via hole of semiconductor device |
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| KR1020020036675A KR20040001459A (en) | 2002-06-28 | 2002-06-28 | Method for forming via hole of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7981308B2 (en) | 2007-12-31 | 2011-07-19 | Robert Bosch Gmbh | Method of etching a device using a hard mask and etch stop layer |
| KR101068142B1 (en) * | 2004-07-01 | 2011-09-27 | 매그나칩 반도체 유한회사 | method for fabricating contact plug of semiconductor device |
-
2002
- 2002-06-28 KR KR1020020036675A patent/KR20040001459A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101068142B1 (en) * | 2004-07-01 | 2011-09-27 | 매그나칩 반도체 유한회사 | method for fabricating contact plug of semiconductor device |
| US7981308B2 (en) | 2007-12-31 | 2011-07-19 | Robert Bosch Gmbh | Method of etching a device using a hard mask and etch stop layer |
| US8232143B2 (en) | 2007-12-31 | 2012-07-31 | Robert Bosch Gmbh | Device formed using a hard mask and etch stop layer |
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